Versuch 3 Hardware funktioniert Juhu!

hardware/signal_processing/crc.vhd

     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
+	-- function berechne_crc(crc_in : signed( 31 downto 0 ), data : signed( 31 downto 0 )) return signed;
+
 	--Selbst angelegte Signale
 	signal data_valid_flag : std_logic;
 	signal busy_flag : std_logic;
 	signal result_valid_flag : std_logic;
-	signal crc_vorher : signed( 31 downto 0);
-	signal crc_nachher :  signed( 31 downto 0 );
-	signal komplett_ergebnis : signed( 31 downto 0 ); --Ergebnis muss zum Schluss evtl invertiert werden (siehe Software)
-	signal wort : signed( 31 downto 0 );
-	signal byte : signed(  7 downto 0 );
+
+	signal flag_index : bit := '0';
+	signal crc_state : integer range 0 to 2;
+
+	signal crcOut : std_logic_vector( 31 downto 0);
+	signal crcIn : std_logic_vector( 31 downto 0) := x"FFFFFFFF";
 
 	--Zustände für die Zustandsmaschine für die Berechnung
 	type CalcState is (
 	--Signale für die Zustandsmaschine für die Berechnung
 	signal current_calc_state : CalcState;
 	signal next_calc_state : CalcState;
+	
 
 
 	-- Anmerkung zu CRC-Polynom:
 	-- in Software wurde 	0xEDB88320		CRC-32 Polynom (Invers) verwendet
 	-- nicht invers waere 	0x04C11DB7
 begin
-	-- Eigener Core verwendet 0xEDB88320 als Polynom
-	u_crc_core : entity work.crc_core					-- Das hier ist der Core
-	port map (
-		crcIn	=>	,	--in std_logic_vector(31 downto 0)
-		data	=>	,	--in std_logic_vector(7 downto 0);
-		crcOut	=>		--out std_logic_vector(31 downto 0)
-	);
 
 	-- Diesen Prozess nicht aendern
     task_state_transitions : process ( current_task_state, task_start, index ) is
                 index <= 0;
                 -- signal_write <= '0';
             when work.task.TASK_RUNNING =>
-                index <= index + 1;	
+				if ( flag_index = '1' ) then
+                	index <= index + 1;	
+				end if;
                 --signal_write <= '1';
                 --signal_writedata <= ( others => '0' );
             when work.task.TASK_DONE =>
 			when 1 =>
 				signal_read <= '0';
 				--Berechne hier crc_out
+				--Die Berechnung muss für jedes Byte wieder durchgeführt werden
 				--Einfacher als Berechnung mit IP Core waere genau hier den ganzen Code davon reinkopieren
+				crcOut(0) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(16) xor crcIn(20) xor crcIn(22) xor crcIn(23) xor crcIn(26) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(26);
+				crcOut(1) <= crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor crcIn(8) xor crcIn(9) xor crcIn(17) xor crcIn(21) xor crcIn(23) xor crcIn(24) xor crcIn(27) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(27);
+				crcOut(2) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(8) xor crcIn(9) xor crcIn(10) xor crcIn(18) xor crcIn(22) xor crcIn(24) xor crcIn(25) xor crcIn(28) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(28);
+				crcOut(3) <= crcIn(1) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(9) xor crcIn(10) xor crcIn(11) xor crcIn(19) xor crcIn(23) xor crcIn(25) xor crcIn(26) xor crcIn(29) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(19) xor signal_readdata(23) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(29);
+				crcOut(4) <= crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(10) xor crcIn(11) xor crcIn(12) xor crcIn(20) xor crcIn(24) xor crcIn(26) xor crcIn(27) xor crcIn(30) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(20) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(30);
+				crcOut(5) <= crcIn(0) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(9) xor crcIn(11) xor crcIn(12) xor crcIn(13) xor crcIn(21) xor crcIn(25) xor crcIn(27) xor crcIn(28) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(21) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(31);
+				crcOut(6) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(9) xor crcIn(10) xor crcIn(12) xor crcIn(13) xor crcIn(14) xor crcIn(16) xor crcIn(20) xor crcIn(23) xor crcIn(28) xor crcIn(29) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(28) xor signal_readdata(29);
+				crcOut(7) <= crcIn(1) xor crcIn(3) xor crcIn(4) xor crcIn(10) xor crcIn(11) xor crcIn(13) xor crcIn(14) xor crcIn(15) xor crcIn(17) xor crcIn(21) xor crcIn(24) xor crcIn(29) xor crcIn(30) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(29) xor signal_readdata(30);
+				crcOut(8) <= crcIn(0) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(11) xor crcIn(12) xor crcIn(14) xor crcIn(15) xor crcIn(16) xor crcIn(18) xor crcIn(22) xor crcIn(25) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(30) xor signal_readdata(31);
+				crcOut(9) <= crcIn(0) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor crcIn(8) xor crcIn(12) xor crcIn(13) xor crcIn(15) xor crcIn(17) xor crcIn(19) xor crcIn(20) xor crcIn(22) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(31);
+				crcOut(10) <= crcIn(0) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor crcIn(9) xor crcIn(13) xor crcIn(14) xor crcIn(18) xor crcIn(21) xor crcIn(22) xor crcIn(26) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(26);
+				crcOut(11) <= crcIn(1) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(8) xor crcIn(10) xor crcIn(14) xor crcIn(15) xor crcIn(19) xor crcIn(22) xor crcIn(23) xor crcIn(27) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(27);
+				crcOut(12) <= crcIn(2) xor crcIn(4) xor crcIn(6) xor crcIn(7) xor crcIn(9) xor crcIn(11) xor crcIn(15) xor crcIn(16) xor crcIn(20) xor crcIn(23) xor crcIn(24) xor crcIn(28) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(28);
+				crcOut(13) <= crcIn(0) xor crcIn(3) xor crcIn(5) xor crcIn(7) xor crcIn(8) xor crcIn(10) xor crcIn(12) xor crcIn(16) xor crcIn(17) xor crcIn(21) xor crcIn(24) xor crcIn(25) xor crcIn(29) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(29);
+				crcOut(14) <= crcIn(0) xor crcIn(1) xor crcIn(4) xor crcIn(6) xor crcIn(8) xor crcIn(9) xor crcIn(11) xor crcIn(13) xor crcIn(17) xor crcIn(18) xor crcIn(22) xor crcIn(25) xor crcIn(26) xor crcIn(30) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(30);
+				crcOut(15) <= crcIn(1) xor crcIn(2) xor crcIn(5) xor crcIn(7) xor crcIn(9) xor crcIn(10) xor crcIn(12) xor crcIn(14) xor crcIn(18) xor crcIn(19) xor crcIn(23) xor crcIn(26) xor crcIn(27) xor crcIn(31) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(23) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(31);
+				crcOut(16) <= crcIn(1) xor crcIn(4) xor crcIn(7) xor crcIn(10) xor crcIn(11) xor crcIn(13) xor crcIn(15) xor crcIn(16) xor crcIn(19) xor crcIn(22) xor crcIn(23) xor crcIn(24) xor crcIn(26) xor crcIn(27) xor crcIn(28) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(28);
+				crcOut(17) <= crcIn(2) xor crcIn(5) xor crcIn(8) xor crcIn(11) xor crcIn(12) xor crcIn(14) xor crcIn(16) xor crcIn(17) xor crcIn(20) xor crcIn(23) xor crcIn(24) xor crcIn(25) xor crcIn(27) xor crcIn(28) xor crcIn(29) xor signal_readdata(2) xor signal_readdata(5) xor signal_readdata(8) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(29);
+				crcOut(18) <= crcIn(0) xor crcIn(3) xor crcIn(6) xor crcIn(9) xor crcIn(12) xor crcIn(13) xor crcIn(15) xor crcIn(17) xor crcIn(18) xor crcIn(21) xor crcIn(24) xor crcIn(25) xor crcIn(26) xor crcIn(28) xor crcIn(29) xor crcIn(30) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(6) xor signal_readdata(9) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(30);
+				crcOut(19) <= crcIn(0) xor crcIn(1) xor crcIn(4) xor crcIn(7) xor crcIn(10) xor crcIn(13) xor crcIn(14) xor crcIn(16) xor crcIn(18) xor crcIn(19) xor crcIn(22) xor crcIn(25) xor crcIn(26) xor crcIn(27) xor crcIn(29) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30) xor signal_readdata(31);
+				crcOut(20) <= crcIn(0) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(11) xor crcIn(14) xor crcIn(15) xor crcIn(16) xor crcIn(17) xor crcIn(19) xor crcIn(22) xor crcIn(27) xor crcIn(28) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(11) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
+				crcOut(21) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(5) xor crcIn(12) xor crcIn(15) xor crcIn(17) xor crcIn(18) xor crcIn(22) xor crcIn(26) xor crcIn(28) xor crcIn(29) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(12) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
+				crcOut(22) <= crcIn(2) xor crcIn(7) xor crcIn(8) xor crcIn(13) xor crcIn(18) xor crcIn(19) xor crcIn(20) xor crcIn(22) xor crcIn(26) xor crcIn(27) xor crcIn(29) xor crcIn(30) xor signal_readdata(2) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(13) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30);
+				crcOut(23) <= crcIn(0) xor crcIn(3) xor crcIn(8) xor crcIn(9) xor crcIn(14) xor crcIn(19) xor crcIn(20) xor crcIn(21) xor crcIn(23) xor crcIn(27) xor crcIn(28) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(14) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
+				crcOut(24) <= crcIn(2) xor crcIn(3) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(9) xor crcIn(10) xor crcIn(15) xor crcIn(16) xor crcIn(21) xor crcIn(23) xor crcIn(24) xor crcIn(26) xor crcIn(28) xor crcIn(29) xor crcIn(31) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
+				crcOut(25) <= crcIn(1) xor crcIn(2) xor crcIn(6) xor crcIn(9) xor crcIn(10) xor crcIn(11) xor crcIn(17) xor crcIn(20) xor crcIn(23) xor crcIn(24) xor crcIn(25) xor crcIn(26) xor crcIn(27) xor crcIn(29) xor crcIn(30) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(6) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(17) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30);
+				crcOut(26) <= crcIn(2) xor crcIn(3) xor crcIn(7) xor crcIn(10) xor crcIn(11) xor crcIn(12) xor crcIn(18) xor crcIn(21) xor crcIn(24) xor crcIn(25) xor crcIn(26) xor crcIn(27) xor crcIn(28) xor crcIn(30) xor crcIn(31) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
+				crcOut(27) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(6) xor crcIn(7) xor crcIn(11) xor crcIn(12) xor crcIn(13) xor crcIn(16) xor crcIn(19) xor crcIn(20) xor crcIn(23) xor crcIn(25) xor crcIn(27) xor crcIn(28) xor crcIn(29) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(16) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
+				crcOut(28) <= crcIn(0) xor crcIn(4) xor crcIn(6) xor crcIn(12) xor crcIn(13) xor crcIn(14) xor crcIn(16) xor crcIn(17) xor crcIn(21) xor crcIn(22) xor crcIn(23) xor crcIn(24) xor crcIn(28) xor crcIn(29) xor crcIn(30) xor signal_readdata(0) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(30);
+				crcOut(29) <= crcIn(0) xor crcIn(1) xor crcIn(5) xor crcIn(7) xor crcIn(13) xor crcIn(14) xor crcIn(15) xor crcIn(17) xor crcIn(18) xor crcIn(22) xor crcIn(23) xor crcIn(24) xor crcIn(25) xor crcIn(29) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(29) xor signal_readdata(30) xor signal_readdata(31);
+				crcOut(30) <= crcIn(3) xor crcIn(4) xor crcIn(7) xor crcIn(14) xor crcIn(15) xor crcIn(18) xor crcIn(19) xor crcIn(20) xor crcIn(22) xor crcIn(24) xor crcIn(25) xor crcIn(30) xor crcIn(31) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(30) xor signal_readdata(31);
+				crcOut(31) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(15) xor crcIn(19) xor crcIn(21) xor crcIn(22) xor crcIn(25) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(15) xor signal_readdata(19) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(31);
 
 				crc_state <= 2;		--Calc Zustand aendern
 			when 2 =>
 				if ( current_task_state = work.task.TASK_DONE ) then
-					signal_writedata <= not(crc_out);	--Ergebnis invertieren
+					signal_writedata <= not crcOut;	--Ergebnis invertieren
 					signal_write <= '1';
 				end if;		
 				
 				flag_index <= '1';	--flag_index sagt nur, dass der index hochgezaehlt werden soll
 				crc_state <= 0;		--Calc Zustand aendern
 				-- assign new crc value
- 				crc_in <= crc_out;
+ 				crcIn <= crcOut;
 
 			end case;
 		end if;

tests/hardware/task_crc/transcript

+# //  Questa Sim-64
+# //  Version 2023.2 linux_x86_64 Apr 11 2023
+# //
+# //  Copyright 1991-2023 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# vsim -voptargs="+acc" work.test_task_crc -do "do vsim.wave; set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gGUI_MODE=true -gCHECK_RESULTS=true 
+# Start time: 09:14:29 on Dec 18,2024
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
+# ** Warning: (vopt-3040) Command line generic/parameter "GUI_MODE" not found in design.
+# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "crc(rtl)".
+# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=2.
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading ieee.fixed_float_types
+# Loading ieee.math_real(body)
+# Loading ieee.fixed_generic_pkg(body)
+# Loading ieee.float_generic_pkg(body)
+# Loading ieee.fixed_pkg
+# Loading ieee.float_pkg
+# Loading work.reg32(body)
+# Loading work.avalon_slave
+# Loading work.test_utility(body)
+# Loading work.test_avalon_slave(body)
+# Loading work.task(body)
+# Loading work.crc_data
+# Loading work.fft_data
+# Loading work.test_hardware_task(body)
+# Loading work.test_data_channel_pkg(body)
+# Loading std.env(body)
+# Loading work.test_task_crc(test)#1
+# Loading work.task_crc(struct)#1
+# Loading work.hardware_task_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#1
+# Loading work.crc(rtl)#1
+# Loading work.data_channel(struct)#1
+# Loading work.data_channel_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#2
+# Loading work.data_sink_mux(rtl)#1
+# Loading work.fifo(rtl)#1
+# Loading work.data_source_mux(rtl)#1
+# do vsim.wave
+#  set StdArithNoWarnings 1
+# 1
+#  set NumericStdNoWarnings 1
+# 1
+#  run -all
+#     test_execute ... [ OK ]
+#     test_crc_value ... [ OK ]
+# 1
+# Break in Process stimulus at test_task_crc.vhd line 131

tests/hardware/task_crc/work/_info

+m255
+K4
+z2
+Z0 !s12c _opt1
+Z1 !s99 nomlopt
+R0
+R1
+R0
+R1
+Z2 !s12c _opt
+R1
+R0
+R1
+R2
+R1
+!s11e vcom 2023.2 2023.04, Apr 11 2023
+13
+!s112 1.1
+!i10d 8192
+!i10e 25
+!i10f 100
+cModel Technology
+Z3 d/users/ads1/brandlfl78731/linux/A_VHDL/signal_processing_vorlage/tests/hardware/task_crc
+T_opt
+!s110 1734509438
+VUBT1hK[kg9oE01M9`41<e3
+Z4 04 13 4 work test_task_crc test 1
+=1-005056868618-6762837e-8cdbc-2dcdf5
+R1
+Z5 !s12b OEM100
+Z6 !s124 OEM100
+o-quiet -auto_acc_if_foreign -work work -g CHECK_RESULTS=true +acc
+Z7 tCvgOpt 0
+n@_opt
+Z8 OL;O;2023.2;77
+R3
+T_opt1
+!s110 1734509670
+VF9mF>E`9PeW8?CKY:EcC52
+R4
+=1-005056868618-67628465-d0174-2e0460
+R1
+R5
+R6
+o-quiet -auto_acc_if_foreign -work work -g GUI_MODE=true -g CHECK_RESULTS=true +acc
+R7
+n@_opt1
+R8
+Pavalon_slave
+Z9 DPx3 std 6 textio 0 22 LS[?81n5ZHWBI9JkBZTV<2
+Z10 DPx4 ieee 14 std_logic_1164 0 22 6<US`=mgl_dFdCEFF7J=m1
+!i122 194
+Z11 w1731485722
+R3
+8../../../hardware/system/avalon_slave.vhd
+F../../../hardware/system/avalon_slave.vhd
+l0
+L4 21
+V@?[Ba;=aE8=>@_SK1ec:a3
+!s100 Y_k7BU9XTbHdh188zDQLY2
+Z12 OL;C;2023.2;77
+33
+Z13 !s110 1734509666
+!i10b 1
+Z14 !s108 1734509666.000000
+!s90 -work|work|-2008|../../../hardware/system/avalon_slave.vhd|
+!s107 ../../../hardware/system/avalon_slave.vhd|
+!i113 0
+Z15 o-work work -2008
+Z16 tExplicit 1 CvgOpt 0
+Eavalon_slave_transitions
+R11
+Z17 DPx4 work 12 avalon_slave 0 22 @?[Ba;=aE8=>@_SK1ec:a3
+Z18 DPx4 work 5 reg32 0 22 ;CN4zHhK9B2g@^5<iAMU[3
+Z19 DPx4 ieee 11 numeric_std 0 22 F8@]:i<mFK7<TjIzKcTGi0
+R9
+R10
+!i122 195
+R3
+Z20 8../../../hardware/system/avalon_slave_transitions.vhd
+Z21 F../../../hardware/system/avalon_slave_transitions.vhd
+l0
+L9 1
+VIhEXFdOShEmn:n5_Y0goM1
+!s100 Afh4H06EPO3EJDWEfAN0=0
+R12
+33
+R13
+!i10b 1
+R14
+Z22 !s90 -work|work|-2008|../../../hardware/system/avalon_slave_transitions.vhd|
+Z23 !s107 ../../../hardware/system/avalon_slave_transitions.vhd|
+!i113 0
+R15
+R16
+Artl
+R17
+R18
+R19
+R9
+R10
+Z24 DEx4 work 24 avalon_slave_transitions 0 22 IhEXFdOShEmn:n5_Y0goM1
+!i122 195
+l37
+L25 65
+VYdE6:2ISUEd0Q>igSVnda1
+!s100 <eIJLiZFI;=RMSQL?3N_=0
+R12
+33
+R13
+!i10b 1
+R14
+R22
+R23
+!i113 0
+R15
+R16
+Ecrc
+Z25 w1734509580
+Z26 DPx4 ieee 9 math_real 0 22 :8NNHF3SFI6^on5?4X[S`1
+Z27 DPx4 work 4 task 0 22 <d2:SDhbOcDb;UZAR6XP<1
+R18
+R19
+R9
+R10
+!i122 203
+R3
+Z28 8../../../hardware/signal_processing/crc.vhd
+Z29 F../../../hardware/signal_processing/crc.vhd
+l0
+L9 1
+VA7c=Wbb69klk0>XAeYn5V3
+!s100 `TAkHjok[hdj;1O3O^KAA0
+R12
+33
+Z30 !s110 1734509667
+!i10b 1
+Z31 !s108 1734509667.000000
+Z32 !s90 -work|work|-2008|../../../hardware/signal_processing/crc.vhd|
+Z33 !s107 ../../../hardware/signal_processing/crc.vhd|
+!i113 0
+R15
+R16
+Artl
+R26
+R27
+R18
+R19
+R9
+R10
+Z34 DEx4 work 3 crc 0 22 A7c=Wbb69klk0>XAeYn5V3
+!i122 203
+l60
+L25 180
+V:Q_n16C6gQONhTa@miONG3
+!s100 81i4ZchkOI<nIZjY14O:]2
+R12
+33
+R30
+!i10b 1
+R31
+R32
+R33
+!i113 0
+R15
+R16
+Pcrc_data
+Z35 DPx4 ieee 9 fixed_pkg 0 22 PQo]@iK^QBglmSTZ7kJDK3
+Z36 DBx4 ieee 17 fixed_generic_pkg 4 body 22 oEANA[?]]:^NiaRa4al943
+Z37 DPx4 ieee 17 fixed_float_types 0 22 ffi_ZLQ=jLAmYO?69bja?3
+Z38 DBx4 ieee 17 float_generic_pkg 4 body 22 iiQGmCSgVf7:NDG@>Phz_1
+Z39 DPx4 ieee 9 float_pkg 0 22 1L7NOAf6nCQU:AJW`ogo60
+R19
+Z40 DPx4 work 12 test_utility 0 22 LfgjXoXNZO0oU:>3HOf]j0
+R9
+R10
+!i122 210
+R11
+R3
+8../../data/crc.vhd
+F../../data/crc.vhd
+l0
+L7 3
+Vcjk;^JQ2el?Q:O0S>fS5P2
+!s100 CzJ<h>03G;o;Ac>aCh2mB2
+R12
+33
+R30
+!i10b 1
+R31
+!s90 -work|work|-2008|../../data/crc.vhd|
+!s107 ../../data/crc.vhd|
+!i113 0
+R15
+R16
+Edata_channel
+R11
+R19
+R9
+R10
+!i122 202
+R3
+Z41 8../../../hardware/system/data_channel.vhd
+Z42 F../../../hardware/system/data_channel.vhd
+l0
+L5 1
+V9<<^ZdM>@cB0QDUkMjL>10
+!s100 ZUUh=EYiS87PRMT7WA;GU3
+R12
+33
+R30
+!i10b 1
+R14
+Z43 !s90 -work|work|-2008|../../../hardware/system/data_channel.vhd|
+Z44 !s107 ../../../hardware/system/data_channel.vhd|
+!i113 0
+R15
+R16
+Astruct
+Z45 DEx4 work 15 data_source_mux 0 22 D0Y0f1TgK@TR<B9B0INE<0
+Z46 DEx4 work 4 fifo 0 22 KUBJ[<P:a@BO_Llm71mO;2
+Z47 DEx4 work 13 data_sink_mux 0 22 Q;UazIGQH_4JT@02NeZQF1
+R17
+R18
+Z48 DEx4 work 20 data_channel_control 0 22 d;@dDzQKY9;^5F`HZgJ]n0
+R19
+R9
+R10
+Z49 DEx4 work 12 data_channel 0 22 9<<^ZdM>@cB0QDUkMjL>10
+!i122 202
+l49
+L27 96
+VBRGULPM[2ao<hm;i2Z=QM3
+!s100 d7KhW?4KEm?WNiOo_nAk?3
+R12
+33
+R30
+!i10b 1
+R14
+R43
+R44
+!i113 0
+R15
+R16
+Edata_channel_control
+R11
+R17
+R18
+R19
+R9
+R10
+!i122 198
+R3
+Z50 8../../../hardware/system/data_channel_control.vhd
+Z51 F../../../hardware/system/data_channel_control.vhd
+l0
+L9 1
+Vd;@dDzQKY9;^5F`HZgJ]n0
+!s100 7Q[gKi9=8QWCoahLW9?F:1
+R12
+33
+R13
+!i10b 1
+R14
+Z52 !s90 -work|work|-2008|../../../hardware/system/data_channel_control.vhd|
+Z53 !s107 ../../../hardware/system/data_channel_control.vhd|
+!i113 0
+R15
+R16
+Artl
+R24
+R17
+R18
+R19
+R9
+R10
+R48
+!i122 198
+l76
+L36 115
+VT[n0mi9@V7ZzHF`W37Wl;2
+!s100 ZhWS;YbG^c8OCMMEiBPY`2
+R12
+33
+R13
+!i10b 1
+R14
+R52
+R53
+!i113 0
+R15
+R16
+Edata_sink_mux
+R11
+R9
+R10
+!i122 199
+R3
+Z54 8../../../hardware/system/data_sink_mux.vhd
+Z55 F../../../hardware/system/data_sink_mux.vhd
+l0
+L4 1
+VQ;UazIGQH_4JT@02NeZQF1
+!s100 9om2d9W8<liMhCO0?O7c?3
+R12
+33
+R13
+!i10b 1
+R14
+Z56 !s90 -work|work|-2008|../../../hardware/system/data_sink_mux.vhd|
+Z57 !s107 ../../../hardware/system/data_sink_mux.vhd|
+!i113 0
+R15
+R16
+Artl
+R9
+R10
+R47
+!i122 199
+l20
+Z58 L19 8
+VT6[B`8W2EV7`PW0nM^4hE2
+!s100 HX?A2PlV_e4;55[jz@0_G0
+R12
+33
+R13
+!i10b 1
+R14
+R56
+R57
+!i113 0
+R15
+R16
+Edata_source_mux
+R11
+R9
+R10
+!i122 200
+R3
+Z59 8../../../hardware/system/data_source_mux.vhd
+Z60 F../../../hardware/system/data_source_mux.vhd
+l0
+L4 1
+VD0Y0f1TgK@TR<B9B0INE<0
+!s100 F0Q2bH8jIk04KD23?DUmZ3
+R12
+33
+R13
+!i10b 1
+R14
+Z61 !s90 -work|work|-2008|../../../hardware/system/data_source_mux.vhd|
+Z62 !s107 ../../../hardware/system/data_source_mux.vhd|
+!i113 0
+R15
+R16
+Artl
+R9
+R10
+R45
+!i122 200
+l20
+R58
+Vf3hlL7MSNTVeB<KRg5P=H2
+!s100 zfZ_NkW=P9InnaQDSjIEP3
+R12
+33
+R13
+!i10b 1
+R14
+R61
+R62
+!i113 0
+R15
+R16
+Pfft_data
+R35
+R36
+R37
+R38
+R39
+R19
+R40
+R9
+R10
+!i122 209
+R11
+R3
+8../../data/fft.vhd
+F../../data/fft.vhd
+l0
+L7 3
+Vfn;7IFao_fmD3zdSRV0oS0
+!s100 ;dIZYHBQ:mJ@of<GF]GbJ1
+R12
+33
+R30
+!i10b 1
+R31
+!s90 -work|work|-2008|../../data/fft.vhd|
+!s107 ../../data/fft.vhd|
+!i113 0
+R15
+R16
+Efifo
+R11
+R19
+R9
+R10
+!i122 201
+R3
+Z63 8../../../hardware/system/fifo.vhd
+Z64 F../../../hardware/system/fifo.vhd
+l0
+L5 1
+VKUBJ[<P:a@BO_Llm71mO;2
+!s100 fB69G?m:faBFLE=emg6dP2
+R12
+33
+R13
+!i10b 1
+R14
+Z65 !s90 -work|work|-2008|../../../hardware/system/fifo.vhd|
+Z66 !s107 ../../../hardware/system/fifo.vhd|
+!i113 0
+R15
+R16
+Artl
+R18
+R19
+R9
+R10
+R46
+!i122 201
+l58
+L24 94
+VkDRYW:RHk_FPUK@HP9RB?1
+!s100 eI8`Fk7X57C0hFH:N5;a`2
+R12
+33
+R13
+!i10b 1
+R14
+R65
+R66
+!i113 0
+R15
+R16
+Pfloat
+R19
+R9
+R10
+!i122 196
+R11
+R3
+Z67 8../../../hardware/system/float.vhd
+Z68 F../../../hardware/system/float.vhd
+l0
+L5 14
+VbdAlbAVYo`Kj2Wf`H<KJm1
+!s100 ALEWC9SfL62IOH<PP8FhY3
+R12
+33
+b1
+R13
+!i10b 1
+R14
+Z69 !s90 -work|work|-2008|../../../hardware/system/float.vhd|
+Z70 !s107 ../../../hardware/system/float.vhd|
+!i113 0
+R15
+R16
+Bbody
+DPx4 work 5 float 0 22 bdAlbAVYo`Kj2Wf`H<KJm1
+R19
+R9
+R10
+!i122 196
+l0
+L20 125
+V=GHO2V40MjKbK;i`E7cbY0
+!s100 5A>0@BDef8I>=aHM2m_Nb1
+R12
+33
+R13
+!i10b 1
+R14
+R69
+R70
+!i113 0
+R15
+R16
+Ehardware_task_control
+R11
+R17
+R26
+R27
+R18
+R19
+R9
+R10
+!i122 197
+R3
+Z71 8../../../hardware/system/hardware_task_control.vhd
+Z72 F../../../hardware/system/hardware_task_control.vhd
+l0
+L10 1
+VN_[hm^[`8P3C_?XhKfMiB1
+!s100 VTe[_8IFOO_mhIP<3miBi3
+R12
+33
+R13
+!i10b 1
+R14
+Z73 !s90 -work|work|-2008|../../../hardware/system/hardware_task_control.vhd|
+Z74 !s107 ../../../hardware/system/hardware_task_control.vhd|
+!i113 0
+R15
+R16
+Artl
+R24
+R17
+R26
+R27
+R18
+R19
+R9
+R10
+Z75 DEx4 work 21 hardware_task_control 0 22 N_[hm^[`8P3C_?XhKfMiB1
+!i122 197
+l65
+L27 110
+V>dkmQz3Q>[@^YR5baS3@T3
+!s100 H>[SQTM5XUD5DZRbn>>Qa1
+R12
+33
+R13
+!i10b 1
+R14
+R73
+R74
+!i113 0
+R15
+R16
+Preg32
+R9
+R10
+!i122 192
+R11
+R3
+Z76 8../../../hardware/system/reg32.vhd
+Z77 F../../../hardware/system/reg32.vhd
+l0
+L4 22
+V;CN4zHhK9B2g@^5<iAMU[3
+!s100 f@oDV2B4W88jjBzL>:J8Q2
+R12
+33
+b1
+R13
+!i10b 1
+R14
+Z78 !s90 -work|work|-2008|../../../hardware/system/reg32.vhd|
+Z79 !s107 ../../../hardware/system/reg32.vhd|
+!i113 0
+R15
+R16
+Bbody
+R18
+R9
+R10
+!i122 192
+l0
+L27 15
+Ve]>7^TdiV29fQSH02B]>g2
+!s100 Iz<N<87?GjQ^OeGg1HaMQ0
+R12
+33
+R13
+!i10b 1
+R14
+R78
+R79
+!i113 0
+R15
+R16
+Ptask
+R26
+R19
+R9
+R10
+!i122 193
+R11
+R3
+Z80 8../../../hardware/system/task.vhd
+Z81 F../../../hardware/system/task.vhd
+l0
+L7 13
+V<d2:SDhbOcDb;UZAR6XP<1
+!s100 <^>UfA]7TKPoiFleR9M]X0
+R12
+33
+b1
+R13
+!i10b 1
+R14
+Z82 !s90 -work|work|-2008|../../../hardware/system/task.vhd|
+Z83 !s107 ../../../hardware/system/task.vhd|
+!i113 0
+R15
+R16
+Bbody
+R27
+R26
+R19
+R9
+R10
+!i122 193
+l0
+L21 20
+V2oWBhb1Hn^eNWQoAZPWOT2
+!s100 SBmbLcWl_l6O`KN;FUj4R2
+R12
+33
+R13
+!i10b 1
+R14
+R82
+R83
+!i113 0
+R15
+R16
+Etask_crc
+R11
+R26
+R27
+R18
+R19
+R9
+R10
+!i122 204
+R3
+Z84 8../../../hardware/system/task_crc.vhd
+Z85 F../../../hardware/system/task_crc.vhd
+l0
+L9 1
+V=R0AIN5abJc>@4h<2Ljba0
+!s100 U_D>YB_c_ciY^57R;@9P61
+R12
+33
+R30
+!i10b 1
+R31
+Z86 !s90 -work|work|-2008|../../../hardware/system/task_crc.vhd|
+Z87 !s107 ../../../hardware/system/task_crc.vhd|
+!i113 0
+R15
+R16
+Astruct
+R34
+R17
+R75
+R26
+R27
+R18
+R19
+R9
+R10
+Z88 DEx4 work 8 task_crc 0 22 =R0AIN5abJc>@4h<2Ljba0
+!i122 204
+l34
+L28 39
+VaI`Z5_H2^I;<gD;96dC9m0
+!s100 W9n=OXeC3ALb?SO_TX<663
+R12
+33
+R30
+!i10b 1
+R31
+R86
+R87
+!i113 0
+R15
+R16
+Ptest_avalon_slave
+R17
+R18
+R19
+R9
+R10
+!i122 206
+R11
+R3
+Z89 8../test_avalon_slave.vhd
+Z90 F../test_avalon_slave.vhd
+l0
+L9 21
+V=E=BCE3fezo;=1No_WYez0
+!s100 B<V@o1?N<VH@1K9>Gj_k03
+R12
+33
+b1
+R30
+!i10b 1
+R31
+Z91 !s90 -work|work|-2008|../test_avalon_slave.vhd|
+Z92 !s107 ../test_avalon_slave.vhd|
+!i113 0
+R15
+R16
+Bbody
+Z93 DPx4 work 17 test_avalon_slave 0 22 =E=BCE3fezo;=1No_WYez0
+R17
+R18
+R19
+R9
+R10
+!i122 206
+l0
+L31 59
+VXI0nR060SQ12W38YkUD@C3
+!s100 WZd:QGO<Fo@g00TmEZhdj2
+R12
+33
+R30
+!i10b 1
+R31
+R91
+R92
+!i113 0
+R15
+R16
+Ptest_data_channel_pkg
+R40
+R17
+R35
+R36
+R37
+R38
+R39
+R19
+R9
+R10
+!i122 208
+R11
+R3
+Z94 8../test_data_channel.vhd
+Z95 F../test_data_channel.vhd
+l0
+L13 78
+VKg5O0U0o2_iFQ:8Ji]59T0
+!s100 ?HMWPiAL0EGF2jbU_G4oC2
+R12
+33
+b1
+R30
+!i10b 1
+R31
+Z96 !s90 -work|work|-2008|../test_data_channel.vhd|
+Z97 !s107 ../test_data_channel.vhd|
+!i113 0
+R15
+R16
+Bbody
+R18
+R93
+Z98 DPx4 work 21 test_data_channel_pkg 0 22 Kg5O0U0o2_iFQ:8Ji]59T0
+R40
+R17
+R35
+R36
+R37
+R38
+R39
+R19
+R9
+R10
+!i122 208
+l0
+L92 345
+VdkMIJzK4NfoaHXfJkP9oj1
+!s100 53=D5fAU:57UzWzz7;Ni10
+R12
+33
+R30
+!i10b 1
+R31
+R96
+R97
+!i113 0
+R15
+R16
+Ptest_hardware_task
+R26
+R27
+R93
+R35
+R36
+R37
+R38
+R39
+R40
+R17
+R18
+R19
+R9
+R10
+!i122 207
+R11
+R3
+Z99 8../test_hardware_task.vhd
+Z100 F../test_hardware_task.vhd
+l0
+L12 49
+V:1KX7@I_AdLVakB_BC2GX0
+!s100 _cAlH]K5VR7O5In0VH57R1
+R12
+33
+b1
+R30
+!i10b 1
+R31
+Z101 !s90 -work|work|-2008|../test_hardware_task.vhd|
+Z102 !s107 ../test_hardware_task.vhd|
+!i113 0
+R15
+R16
+Bbody
+Z103 DPx4 work 18 test_hardware_task 0 22 :1KX7@I_AdLVakB_BC2GX0
+R26
+R27
+R93
+R35
+R36
+R37
+R38
+R39
+R40
+R17
+R18
+R19
+R9
+R10
+!i122 207
+l0
+L62 155
+V20RoZA=[2aNU4Vk2d1E7o3
+!s100 jkFWoJ6kOFPXg3P>IR=JM3
+R12
+33
+R30
+!i10b 1
+R31
+R101
+R102
+!i113 0
+R15
+R16
+Etest_task_crc
+R11
+Z104 DPx3 std 3 env 0 22 QPZJVBPkV?55nUWhDzFik0
+R98
+R103
+Z105 DPx4 work 8 fft_data 0 22 fn;7IFao_fmD3zdSRV0oS0
+Z106 DPx4 work 8 crc_data 0 22 cjk;^JQ2el?Q:O0S>fS5P2
+R26
+R27
+R93
+R40
+R17
+R18
+R35
+Z107 DPx4 ieee 17 fixed_generic_pkg 0 22 2hf4dO<a7fz_fMXj:L2T^2
+R37
+Z108 DPx4 ieee 17 float_generic_pkg 0 22 ;UNER2c<j?_?>9[Ma=AYh2
+R39
+R19
+R9
+R10
+!i122 211
+R3
+Z109 8test_task_crc.vhd
+Z110 Ftest_task_crc.vhd
+l0
+L21 1
+VO5em_Fb^PTWXh_CNzfWQi0
+!s100 BRJj:2CQ>5bRK87X`_OAG2
+R12
+33
+R30
+!i10b 1
+R31
+Z111 !s90 -work|work|-2008|test_task_crc.vhd|
+Z112 !s107 test_task_crc.vhd|
+!i113 0
+R15
+R16
+Atest
+R49
+R88
+R104
+R98
+R103
+R105
+R106
+R26
+R27
+R93
+R40
+R17
+R18
+R35
+R107
+R37
+R108
+R39
+R19
+R9
+R10
+DEx4 work 13 test_task_crc 0 22 O5em_Fb^PTWXh_CNzfWQi0
+!i122 211
+l47
+L25 109
+V2<jh]3oekPSdaJ:2UP6Vf3
+!s100 09MLP9ZKn=h04fRCz64We3
+R12
+33
+R30
+!i10b 1
+R31
+R111
+R112
+!i113 0
+R15
+R16
+Ptest_utility
+R35
+R36
+R37
+R38
+R39
+R19
+R9
+R10
+!i122 205
+R11
+R3
+Z113 8../test_utility.vhd
+Z114 F../test_utility.vhd
+l0
+L9 18
+VLfgjXoXNZO0oU:>3HOf]j0
+!s100 YPd92oeJ9Vbb]_IQiX^Dd0
+R12
+33
+b1
+R30
+!i10b 1
+R31
+Z115 !s90 -work|work|-2008|../test_utility.vhd|
+Z116 !s107 ../test_utility.vhd|
+!i113 0
+R15
+R16
+Bbody
+R40
+R35
+R36
+R37
+R38
+R39
+R19
+R9
+R10
+!i122 205
+l0
+L28 43
+Vd1?l^cn8a]9M5=ZnIR0aW2
+!s100 eNzl<XFZ<9KmY24XR]RfW1
+R12
+33
+R30
+!i10b 1
+R31
+R115
+R116
+!i113 0
+R15
+R16

tests/hardware/task_crc/work/_opt1__lock

+brandlfl78731@efiapps0.ads1.fh-nuernberg.de, pid = 3015776

tests/hardware/task_crc/work/_vmake

+m255
+K4
+z0
+cModel Technology