hauselthe74767/signal_processing_vorlage
1
0
Fork 0
forked from KutningJo/signal_processing_vorlage
Code Issues Pull Requests Releases Wiki Activity

Versuch 2 Hardware funktioniert

Browse Source
This commit is contained in:
brandlfl78731
2024-11-27 10:19:31 +01:00
parent cfe1e2927c
commit de8d181dde
80 changed files with 4426 additions and 453 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/signal_processing/sine.vhd
+29 -33
View File
@@ -36,10 +36,12 @@ architecture rtl of sine is
signal result_valid_flag : std_logic;
signal angle_sig : signed( 31 downto 0);
signal ergebnis : signed( 31 downto 0 );
signal ampl_sig : signed( 31 downto 0 );
--Zustände für die Zustandsmaschine für die Berechnung
type CalcState is (
CALC_IDLE,
CALC_START,
CALC_SINE,
CALC_STORE_RESULT
);
@@ -49,6 +51,9 @@ architecture rtl of sine is
begin
u_float_sine : entity work.float_sine -- Das hier ist der Core!
generic map (
ITERATIONS => 8
)
port map (
clk => clk,
reset => reset,
@@ -60,7 +65,7 @@ begin
);
--Bei diesem task nichts ändern!
task_state_transitions : process ( current_task_state, task_start, index ) is
task_state_transitions : process ( all ) is
begin
next_task_state <= current_task_state;
case current_task_state is
@@ -87,14 +92,20 @@ begin
case current_calc_state is
when CALC_IDLE=>
if (current_task_state= work.task.TASK_RUNNING) then
next_calc_state <= CALC_SINE;
next_calc_state <= CALC_START;
end if;
when CALC_START=>
next_calc_state <= CALC_SINE;
when CALC_SINE =>
if (result_valid_flag = '1') then
if (result_valid_flag = '1' and busy_flag = '0') then --or falling_edge( busy) ?
next_calc_state <= CALC_STORE_RESULT;
end if;
when CALC_STORE_RESULT =>
next_calc_state <= CALC_IDLE;
if ( index = work.task.STREAM_LEN ) then
next_calc_state <= CALC_IDLE;
else
next_calc_state <= CALC_START;
end if;
end case;
end process calc_state_transitions;
@@ -120,50 +131,35 @@ begin
begin
if (reset = '1') then
index <= 0;
data_valid_flag <= '0';
current_calc_state <= CALC_IDLE;
ergebnis <= (others => '0');
--ergebnis <= (others => '0'); --Wird von IP Core gesteuert und darf deshalb hier nicht getrieben werden
signal_writedata <= (others => '0');
signal_write <= '0';
angle_sig <= (others => '0');
elsif (rising_edge( clk)) then
current_calc_state <= next_calc_state;
case next_calc_state is
when CALC_IDLE =>
data_valid_flag <= '0';
signal_write <= '0';
when CALC_SINE => --hier Berechnung mit IP Core?
angle_sig <= signed (phase);
ampl_sig <= signed (amplitude);
when CALC_START =>
data_valid_flag <= '1';
when CALC_STORE_RESULT =>
signal_write <= '0';
angle_sig <= angle_sig + signed(step_size); --step_size = 2 * PI / 32
when CALC_SINE => --hier Berechnung mit IP Core?
data_valid_flag <= '0';
when CALC_STORE_RESULT =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= std_logic_vector( ergebnis ); --Ergebnis schreiben, ergebnis direkt aus IP Core
--Berechne float multiplikation zu Fuss. Exponent + Exponent usw.
signal_writedata <= std_logic_vector( ergebnis(31 downto 31) & (ergebnis(30 downto 23) + (signed(ampl_sig(30 downto 23)) - 127)) & ergebnis(22 downto 0));
end case;
end if;
end process sync;
task_state <= current_task_state;
--Altes Programm
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
end case;
end if;
end process sync;
task_state <= current_task_state;
end architecture rtl;