hardware/signal_processing/sine.vhd

@@ -36,12 +36,10 @@ architecture rtl of sine is
 	signal result_valid_flag : std_logic;
 	signal angle_sig : signed( 31 downto 0);
 	signal ergebnis :  signed( 31 downto 0 );
-	signal ampl_sig : signed( 31 downto 0 );
 
 	--Zustände für die Zustandsmaschine für die Berechnung
 	type CalcState is (
 		CALC_IDLE,
-		CALC_START,
 		CALC_SINE,
 		CALC_STORE_RESULT
 	);
@@ -51,9 +49,6 @@ architecture rtl of sine is
 
 begin
     u_float_sine : entity work.float_sine -- Das hier ist der Core!
-	generic map (
-		ITERATIONS => 8
-	)
     port map (
         clk 	=> 		clk,
         reset 	=>		reset,
@@ -65,7 +60,7 @@ begin
     );
 
 	--Bei diesem task nichts ändern!
-    task_state_transitions : process ( all ) is
+    task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
         case current_task_state is
@@ -92,20 +87,14 @@ begin
 		case current_calc_state is
 			when CALC_IDLE=>
 				if (current_task_state= work.task.TASK_RUNNING) then 
-					next_calc_state <= CALC_START;
-				end if;
-			when CALC_START=>
 					next_calc_state <= CALC_SINE;
+				end if;
 			when CALC_SINE =>
-				if (result_valid_flag = '1' and busy_flag = '0') then 	--or falling_edge( busy) ?
+				if (result_valid_flag = '1') then
 					next_calc_state <= CALC_STORE_RESULT;
 				end if;
 			when CALC_STORE_RESULT =>
-				if ( index = work.task.STREAM_LEN ) then
 				next_calc_state <= CALC_IDLE;
-				else
-					next_calc_state <= CALC_START;
-				end if;
 		end case;
 	end process calc_state_transitions;
 
@@ -131,35 +120,50 @@ begin
 	begin
 		if (reset = '1') then
 			index <= 0;
-			data_valid_flag <= '0';
 			current_calc_state <= CALC_IDLE;
-			--ergebnis <= (others => '0');  --Wird von IP Core gesteuert und darf deshalb hier nicht getrieben werden
-			signal_writedata <= (others => '0');
+			ergebnis <= (others => '0'); 
 			signal_write <= '0';
-			angle_sig <= (others => '0');
 		elsif (rising_edge( clk)) then
 			current_calc_state <= next_calc_state; 
 			case next_calc_state is 
 				when CALC_IDLE =>
 					data_valid_flag <= '0';
 					signal_write <= '0';
-					angle_sig <= signed (phase);
-					ampl_sig <= signed (amplitude);
-				when CALC_START =>
-					data_valid_flag <= '1';
-					signal_write <= '0';
-					angle_sig <= angle_sig + signed(step_size); --step_size = 2 * PI / 32
 				when CALC_SINE => 				--hier Berechnung mit IP Core?
-					data_valid_flag <= '0';
+					data_valid_flag <= '1';
 				when CALC_STORE_RESULT =>
+					data_valid_flag <= '0';
 					index <= index + 1;
 					signal_write <= '1';
-					--Berechne float multiplikation zu Fuss. Exponent + Exponent usw.
-					signal_writedata <= std_logic_vector( ergebnis(31 downto 31) & (ergebnis(30 downto 23) + (signed(ampl_sig(30 downto 23)) - 127)) & ergebnis(22 downto 0));
-
+					signal_writedata <= std_logic_vector( ergebnis ); --Ergebnis schreiben, ergebnis direkt aus IP Core
 			end case;
 		end if;
 	end process sync;
 	task_state <= current_task_state;
 
+--Altes Programm
+    sync : process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            current_task_state <= work.task.TASK_IDLE;
+            index <= 0;
+        elsif ( rising_edge( clk ) ) then
+            current_task_state <= next_task_state;
+            case next_task_state is
+            when work.task.TASK_IDLE =>
+                index <= 0;
+                signal_write <= '0';
+            when work.task.TASK_RUNNING =>
+                index <= index + 1;
+                signal_write <= '1';
+                signal_writedata <= ( others => '0' );
+            when work.task.TASK_DONE =>
+                index <= 0;
+                signal_write <= '0';
+            end case;
+        end if;
+    end process sync;
+
+    task_state <= current_task_state;
+
 end architecture rtl;

software/signal_processing/crc.c

@@ -5,66 +5,7 @@
 int task_crc_run( void * task ) {
 
     // TODO
-	crc_config * config = ( crc_config *) task;
-
-	uint32_t value = config->start; // Startwert CRC vom gewaehlten Algorithmus (wird erst in der Funktion invertiert)
-
-	// Nachfolgende Antworten Lesen den FIFO der ersten Datenquelle aus und multiplizieren
-	// den jeweils gelesenen Wert mit 4 und speichern das Ergebnis in der Datensenke
-	for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
-		float_word a;
-		data_channel_read(config->base.sources[0], (uint32_t * ) & a.word );
-		float_word c;
-		//c.value = 4*a; //Hier mit Werten aus CRC FIFO multiplizieren
-		c.value = 0;
-
-		for (uint32_t j = 0; j < 32; j++) {
-			if (a.word & (1<<31)) {
-				c.word = (c.word * 2 + ((a.word & (1<<j))>>j)) ^ CRC32POLY;
-			} else {
-				c.word = (c.word * 2 + ((a.word & (1<<j))>>j));
-			}
-		}
-
-/*
-		for (uint32_t j = 0; j < 4; j++) {
-			if (a.word & (1<<31)) {
-				c.word = (c.word * 2 + ((a.word & (0xff<<j*8))>>j*8)) ^ CRC32POLY;
-			} else {
-				c.word = (c.word * 2 + ((a.word & (0xff<<j*8))>>j*8));
-			}
-		}
-*/
-		data_channel_write( config->base.sink, c.word );
-		printf("a= %08x c= %08x\n", a.word, c.word);
-	}
 
     return 0;
 }
 
-/*
-crc := 0000… (Startwert)
-für alle Bits b im Datenstrom:
-  wenn  das am weitesten links stehende Bit von crc 1 ist:
-    crc := (crc * 2 + b) xor CRC-Polynom
-  sonst:
-    crc := crc * 2 + b
-crc enthält das Ergebnis.
-*/
-/*
-const uint8_t   bitstream[] = { 1,0,0,0,1,1,0,0 };
-const int       bitcount    = 8;
-uint32_t        crc32       = 0;    // Schieberegister
-
-int main ()
-{
-    for (int i = 0; i < bitcount; i++)
-    {
-        if ( ((crc32 >> 31) & 1) != bitstream[i])
-            crc32 = (crc32 << 1) ^ CRC32POLY;
-        else
-            crc32 = (crc32 << 1);
-    }
-    printf ("0x%08X\n", crc32);
-}
-*/

software/signal_processing/system/task_crc.h

@@ -9,8 +9,7 @@ extern "C" {
 
 extern crc_config CRC_CONFIG;
 
-//#define CRC32POLY   0xEDB88320        /* CRC-32 Polynom (Invers)*/
-#define CRC32POLY   0x04C11DB7
+#define CRC32POLY   0xEDB88320        /* CRC-32 Polynom (Invers)*/
 
 int task_crc_run( void * task );
 

tests/hardware/task_cosine/transcript

@@ -1,65 +0,0 @@
-# vsim -voptargs="+acc" -c work.test_task_cosine -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false 
-# Start time: 10:17:57 on Nov 27,2024
-# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
-# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
-# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "sine(rtl)".
-# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
-# //  Questa Sim-64
-# //  Version 2023.2 linux_x86_64 Apr 11 2023
-# //
-# //  Copyright 1991-2023 Mentor Graphics Corporation
-# //  All Rights Reserved.
-# //
-# //  QuestaSim and its associated documentation contain trade
-# //  secrets and commercial or financial information that are the property of
-# //  Mentor Graphics Corporation and are privileged, confidential,
-# //  and exempt from disclosure under the Freedom of Information Act,
-# //  5 U.S.C. Section 552. Furthermore, this information
-# //  is prohibited from disclosure under the Trade Secrets Act,
-# //  18 U.S.C. Section 1905.
-# //
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.numeric_std(body)
-# Loading ieee.fixed_float_types
-# Loading ieee.math_real(body)
-# Loading ieee.fixed_generic_pkg(body)
-# Loading ieee.float_generic_pkg(body)
-# Loading ieee.fixed_pkg
-# Loading ieee.float_pkg
-# Loading work.reg32(body)
-# Loading work.avalon_slave
-# Loading work.test_utility(body)
-# Loading work.test_avalon_slave(body)
-# Loading work.task(body)
-# Loading work.cosine_data
-# Loading work.test_hardware_task(body)
-# Loading work.test_data_channel_pkg(body)
-# Loading std.env(body)
-# Loading work.test_task_cosine(test)#1
-# Loading work.float(body)
-# Loading work.task_sine(struct)#1
-# Loading work.hardware_task_control(rtl)#1
-# Loading work.avalon_slave_transitions(rtl)#1
-# Loading work.cordic_pkg(body)
-# Loading work.sine(rtl)#1
-# Loading work.float_sine(rtl)#1
-# Loading work.fixed_sine(rtl)#1
-# Loading work.cordic(rtl)#1
-# Loading work.data_channel(struct)#1
-# Loading work.data_channel_control(rtl)#1
-# Loading work.avalon_slave_transitions(rtl)#2
-# Loading work.data_sink_mux(rtl)#1
-# Loading work.fifo(rtl)#1
-# Loading work.data_source_mux(rtl)#1
-# set StdArithNoWarnings 1
-# 1
-#  set NumericStdNoWarnings 1
-# 1
-#  run -all
-#     test_configure ... [ OK ]
-#     test_execute ... [ OK ]
-#     write_content ... [ OK ]
-# End time: 10:17:57 on Nov 27,2024, Elapsed time: 0:00:00
-# Errors: 0, Warnings: 1

tests/hardware/task_cosine/work/_vmake

@@ -1,4 +0,0 @@
-m255
-K4
-z0
-cModel Technology

tests/hardware/task_sine/transcript

@@ -1,65 +0,0 @@
-# vsim -voptargs="+acc" -c work.test_task_sine -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false 
-# Start time: 10:15:59 on Nov 27,2024
-# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
-# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
-# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "sine(rtl)".
-# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
-# //  Questa Sim-64
-# //  Version 2023.2 linux_x86_64 Apr 11 2023
-# //
-# //  Copyright 1991-2023 Mentor Graphics Corporation
-# //  All Rights Reserved.
-# //
-# //  QuestaSim and its associated documentation contain trade
-# //  secrets and commercial or financial information that are the property of
-# //  Mentor Graphics Corporation and are privileged, confidential,
-# //  and exempt from disclosure under the Freedom of Information Act,
-# //  5 U.S.C. Section 552. Furthermore, this information
-# //  is prohibited from disclosure under the Trade Secrets Act,
-# //  18 U.S.C. Section 1905.
-# //
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.numeric_std(body)
-# Loading ieee.fixed_float_types
-# Loading ieee.math_real(body)
-# Loading ieee.fixed_generic_pkg(body)
-# Loading ieee.float_generic_pkg(body)
-# Loading ieee.fixed_pkg
-# Loading ieee.float_pkg
-# Loading work.reg32(body)
-# Loading work.avalon_slave
-# Loading work.test_utility(body)
-# Loading work.test_avalon_slave(body)
-# Loading work.task(body)
-# Loading work.sine_data
-# Loading work.test_hardware_task(body)
-# Loading work.test_data_channel_pkg(body)
-# Loading std.env(body)
-# Loading work.test_task_sine(test)#1
-# Loading work.float(body)
-# Loading work.task_sine(struct)#1
-# Loading work.hardware_task_control(rtl)#1
-# Loading work.avalon_slave_transitions(rtl)#1
-# Loading work.cordic_pkg(body)
-# Loading work.sine(rtl)#1
-# Loading work.float_sine(rtl)#1
-# Loading work.fixed_sine(rtl)#1
-# Loading work.cordic(rtl)#1
-# Loading work.data_channel(struct)#1
-# Loading work.data_channel_control(rtl)#1
-# Loading work.avalon_slave_transitions(rtl)#2
-# Loading work.data_sink_mux(rtl)#1
-# Loading work.fifo(rtl)#1
-# Loading work.data_source_mux(rtl)#1
-# set StdArithNoWarnings 1
-# 1
-#  set NumericStdNoWarnings 1
-# 1
-#  run -all
-#     test_configure ... [ OK ]
-#     test_execute ... [ OK ]
-#     write_content ... [ OK ]
-# End time: 10:16:00 on Nov 27,2024, Elapsed time: 0:00:01
-# Errors: 0, Warnings: 1