/*
 * system.h - SOPC Builder system and BSP software package information
 *
 * Machine generated for CPU 'core' in SOPC Builder design 'niosII'
 * SOPC Builder design path: ../../niosII.sopcinfo
 *
 * Generated: Wed Dec 18 09:45:17 CET 2024
 */

/*
 * DO NOT MODIFY THIS FILE
 *
 * Changing this file will have subtle consequences
 * which will almost certainly lead to a nonfunctioning
 * system. If you do modify this file, be aware that your
 * changes will be overwritten and lost when this file
 * is generated again.
 *
 * DO NOT MODIFY THIS FILE
 */

/*
 * License Agreement
 *
 * Copyright (c) 2008
 * Altera Corporation, San Jose, California, USA.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * This agreement shall be governed in all respects by the laws of the State
 * of California and by the laws of the United States of America.
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/* Include definitions from linker script generator */
#include "linker.h"


/*
 * CPU configuration
 *
 */

#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"
#define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x00060820
#define ALT_CPU_CPU_ARCH_NIOS2_R1
#define ALT_CPU_CPU_FREQ 200000000u
#define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x00000000
#define ALT_CPU_CPU_IMPLEMENTATION "fast"
#define ALT_CPU_DATA_ADDR_WIDTH 0x13
#define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000
#define ALT_CPU_DCACHE_LINE_SIZE 32
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_DCACHE_SIZE 32768
#define ALT_CPU_EXCEPTION_ADDR 0x00040020
#define ALT_CPU_FLASH_ACCELERATOR_LINES 0
#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
#define ALT_CPU_FLUSHDA_SUPPORTED
#define ALT_CPU_FREQ 200000000
#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 1
#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1
#define ALT_CPU_HARDWARE_MULX_PRESENT 0
#define ALT_CPU_HAS_DEBUG_CORE 1
#define ALT_CPU_HAS_DEBUG_STUB
#define ALT_CPU_HAS_DIVISION_ERROR_EXCEPTION
#define ALT_CPU_HAS_EXTRA_EXCEPTION_INFO
#define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
#define ALT_CPU_HAS_JMPI_INSTRUCTION
#define ALT_CPU_ICACHE_LINE_SIZE 32
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_ICACHE_SIZE 32768
#define ALT_CPU_INITDA_SUPPORTED
#define ALT_CPU_INST_ADDR_WIDTH 0x13
#define ALT_CPU_NAME "core"
#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0
#define ALT_CPU_OCI_VERSION 1
#define ALT_CPU_RESET_ADDR 0x00040000


/*
 * CPU configuration (with legacy prefix - don't use these anymore)
 *
 */

#define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x00060820
#define NIOS2_CPU_ARCH_NIOS2_R1
#define NIOS2_CPU_FREQ 200000000u
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x00000000
#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_DATA_ADDR_WIDTH 0x13
#define NIOS2_DCACHE_BYPASS_MASK 0x80000000
#define NIOS2_DCACHE_LINE_SIZE 32
#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_SIZE 32768
#define NIOS2_EXCEPTION_ADDR 0x00040020
#define NIOS2_FLASH_ACCELERATOR_LINES 0
#define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0
#define NIOS2_FLUSHDA_SUPPORTED
#define NIOS2_HARDWARE_DIVIDE_PRESENT 1
#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1
#define NIOS2_HARDWARE_MULX_PRESENT 0
#define NIOS2_HAS_DEBUG_CORE 1
#define NIOS2_HAS_DEBUG_STUB
#define NIOS2_HAS_DIVISION_ERROR_EXCEPTION
#define NIOS2_HAS_EXTRA_EXCEPTION_INFO
#define NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
#define NIOS2_HAS_JMPI_INSTRUCTION
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_ICACHE_SIZE 32768
#define NIOS2_INITDA_SUPPORTED
#define NIOS2_INST_ADDR_WIDTH 0x13
#define NIOS2_NUM_OF_SHADOW_REG_SETS 0
#define NIOS2_OCI_VERSION 1
#define NIOS2_RESET_ADDR 0x00040000


/*
 * Define for each module class mastered by the CPU
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SYSID_QSYS
#define __ALTERA_NIOS2_GEN2
#define __DATA_CHANNEL
#define __HARDWARE_TASK
#define __HARDWARE_TIMESTAMP


/*
 * System configuration
 *
 */

#define ALT_DEVICE_FAMILY "Cyclone V"
#define ALT_ENHANCED_INTERRUPT_API_PRESENT
#define ALT_IRQ_BASE NULL
#define ALT_LOG_PORT "/dev/null"
#define ALT_LOG_PORT_BASE 0x0
#define ALT_LOG_PORT_DEV null
#define ALT_LOG_PORT_TYPE ""
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_BASE 0x613e8
#define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_BASE 0x613e8
#define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_BASE 0x613e8
#define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_SYSTEM_NAME "niosII"
#define ALT_SYS_CLK_TICKS_PER_SEC NONE_TICKS_PER_SEC
#define ALT_TIMESTAMP_CLK_TIMER_DEVICE_TYPE NONE_TIMER_DEVICE_TYPE


/*
 * data_channel_0 configuration
 *
 */

#define ALT_MODULE_CLASS_data_channel_0 data_channel
#define DATA_CHANNEL_0_BASE 0x611c0
#define DATA_CHANNEL_0_IRQ -1
#define DATA_CHANNEL_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define DATA_CHANNEL_0_NAME "/dev/data_channel_0"
#define DATA_CHANNEL_0_SPAN 64
#define DATA_CHANNEL_0_TYPE "data_channel"


/*
 * data_channel_1 configuration
 *
 */

#define ALT_MODULE_CLASS_data_channel_1 data_channel
#define DATA_CHANNEL_1_BASE 0x61180
#define DATA_CHANNEL_1_IRQ -1
#define DATA_CHANNEL_1_IRQ_INTERRUPT_CONTROLLER_ID -1
#define DATA_CHANNEL_1_NAME "/dev/data_channel_1"
#define DATA_CHANNEL_1_SPAN 64
#define DATA_CHANNEL_1_TYPE "data_channel"


/*
 * data_channel_2 configuration
 *
 */

#define ALT_MODULE_CLASS_data_channel_2 data_channel
#define DATA_CHANNEL_2_BASE 0x61140
#define DATA_CHANNEL_2_IRQ -1
#define DATA_CHANNEL_2_IRQ_INTERRUPT_CONTROLLER_ID -1
#define DATA_CHANNEL_2_NAME "/dev/data_channel_2"
#define DATA_CHANNEL_2_SPAN 64
#define DATA_CHANNEL_2_TYPE "data_channel"


/*
 * data_channel_3 configuration
 *
 */

#define ALT_MODULE_CLASS_data_channel_3 data_channel
#define DATA_CHANNEL_3_BASE 0x61100
#define DATA_CHANNEL_3_IRQ -1
#define DATA_CHANNEL_3_IRQ_INTERRUPT_CONTROLLER_ID -1
#define DATA_CHANNEL_3_NAME "/dev/data_channel_3"
#define DATA_CHANNEL_3_SPAN 64
#define DATA_CHANNEL_3_TYPE "data_channel"


/*
 * data_channel_4 configuration
 *
 */

#define ALT_MODULE_CLASS_data_channel_4 data_channel
#define DATA_CHANNEL_4_BASE 0x610c0
#define DATA_CHANNEL_4_IRQ -1
#define DATA_CHANNEL_4_IRQ_INTERRUPT_CONTROLLER_ID -1
#define DATA_CHANNEL_4_NAME "/dev/data_channel_4"
#define DATA_CHANNEL_4_SPAN 64
#define DATA_CHANNEL_4_TYPE "data_channel"


/*
 * data_channel_5 configuration
 *
 */

#define ALT_MODULE_CLASS_data_channel_5 data_channel
#define DATA_CHANNEL_5_BASE 0x61080
#define DATA_CHANNEL_5_IRQ -1
#define DATA_CHANNEL_5_IRQ_INTERRUPT_CONTROLLER_ID -1
#define DATA_CHANNEL_5_NAME "/dev/data_channel_5"
#define DATA_CHANNEL_5_SPAN 64
#define DATA_CHANNEL_5_TYPE "data_channel"


/*
 * data_channel_6 configuration
 *
 */

#define ALT_MODULE_CLASS_data_channel_6 data_channel
#define DATA_CHANNEL_6_BASE 0x61040
#define DATA_CHANNEL_6_IRQ -1
#define DATA_CHANNEL_6_IRQ_INTERRUPT_CONTROLLER_ID -1
#define DATA_CHANNEL_6_NAME "/dev/data_channel_6"
#define DATA_CHANNEL_6_SPAN 64
#define DATA_CHANNEL_6_TYPE "data_channel"


/*
 * hal configuration
 *
 */

#define ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
#define ALT_MAX_FD 32
#define ALT_SYS_CLK none
#define ALT_TIMESTAMP_CLK none


/*
 * hardware_task_0 configuration
 *
 */

#define ALT_MODULE_CLASS_hardware_task_0 hardware_task
#define HARDWARE_TASK_0_BASE 0x61000
#define HARDWARE_TASK_0_IRQ -1
#define HARDWARE_TASK_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HARDWARE_TASK_0_NAME "/dev/hardware_task_0"
#define HARDWARE_TASK_0_SPAN 64
#define HARDWARE_TASK_0_TYPE "hardware_task"


/*
 * hardware_task_1 configuration
 *
 */

#define ALT_MODULE_CLASS_hardware_task_1 hardware_task
#define HARDWARE_TASK_1_BASE 0x61340
#define HARDWARE_TASK_1_IRQ -1
#define HARDWARE_TASK_1_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HARDWARE_TASK_1_NAME "/dev/hardware_task_1"
#define HARDWARE_TASK_1_SPAN 64
#define HARDWARE_TASK_1_TYPE "hardware_task"


/*
 * hardware_task_2 configuration
 *
 */

#define ALT_MODULE_CLASS_hardware_task_2 hardware_task
#define HARDWARE_TASK_2_BASE 0x61300
#define HARDWARE_TASK_2_IRQ -1
#define HARDWARE_TASK_2_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HARDWARE_TASK_2_NAME "/dev/hardware_task_2"
#define HARDWARE_TASK_2_SPAN 64
#define HARDWARE_TASK_2_TYPE "hardware_task"


/*
 * hardware_task_3 configuration
 *
 */

#define ALT_MODULE_CLASS_hardware_task_3 hardware_task
#define HARDWARE_TASK_3_BASE 0x612c0
#define HARDWARE_TASK_3_IRQ -1
#define HARDWARE_TASK_3_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HARDWARE_TASK_3_NAME "/dev/hardware_task_3"
#define HARDWARE_TASK_3_SPAN 64
#define HARDWARE_TASK_3_TYPE "hardware_task"


/*
 * hardware_task_4 configuration
 *
 */

#define ALT_MODULE_CLASS_hardware_task_4 hardware_task
#define HARDWARE_TASK_4_BASE 0x61280
#define HARDWARE_TASK_4_IRQ -1
#define HARDWARE_TASK_4_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HARDWARE_TASK_4_NAME "/dev/hardware_task_4"
#define HARDWARE_TASK_4_SPAN 64
#define HARDWARE_TASK_4_TYPE "hardware_task"


/*
 * hardware_task_5 configuration
 *
 */

#define ALT_MODULE_CLASS_hardware_task_5 hardware_task
#define HARDWARE_TASK_5_BASE 0x61240
#define HARDWARE_TASK_5_IRQ -1
#define HARDWARE_TASK_5_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HARDWARE_TASK_5_NAME "/dev/hardware_task_5"
#define HARDWARE_TASK_5_SPAN 64
#define HARDWARE_TASK_5_TYPE "hardware_task"


/*
 * hardware_task_6 configuration
 *
 */

#define ALT_MODULE_CLASS_hardware_task_6 hardware_task
#define HARDWARE_TASK_6_BASE 0x61200
#define HARDWARE_TASK_6_IRQ -1
#define HARDWARE_TASK_6_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HARDWARE_TASK_6_NAME "/dev/hardware_task_6"
#define HARDWARE_TASK_6_SPAN 64
#define HARDWARE_TASK_6_TYPE "hardware_task"


/*
 * hardware_timestamp configuration
 *
 */

#define ALT_MODULE_CLASS_hardware_timestamp hardware_timestamp
#define HARDWARE_TIMESTAMP_BASE 0x61380
#define HARDWARE_TIMESTAMP_IRQ -1
#define HARDWARE_TIMESTAMP_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HARDWARE_TIMESTAMP_NAME "/dev/hardware_timestamp"
#define HARDWARE_TIMESTAMP_SPAN 64
#define HARDWARE_TIMESTAMP_TYPE "hardware_timestamp"


/*
 * jtag_uart configuration
 *
 */

#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart
#define JTAG_UART_BASE 0x613e8
#define JTAG_UART_IRQ 0
#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_SPAN 8
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8


/*
 * key_start configuration
 *
 */

#define ALT_MODULE_CLASS_key_start altera_avalon_pio
#define KEY_START_BASE 0x613d0
#define KEY_START_BIT_CLEARING_EDGE_REGISTER 1
#define KEY_START_BIT_MODIFYING_OUTPUT_REGISTER 0
#define KEY_START_CAPTURE 1
#define KEY_START_DATA_WIDTH 1
#define KEY_START_DO_TEST_BENCH_WIRING 0
#define KEY_START_DRIVEN_SIM_VALUE 0
#define KEY_START_EDGE_TYPE "RISING"
#define KEY_START_FREQ 200000000
#define KEY_START_HAS_IN 1
#define KEY_START_HAS_OUT 0
#define KEY_START_HAS_TRI 0
#define KEY_START_IRQ 2
#define KEY_START_IRQ_INTERRUPT_CONTROLLER_ID 0
#define KEY_START_IRQ_TYPE "EDGE"
#define KEY_START_NAME "/dev/key_start"
#define KEY_START_RESET_VALUE 0
#define KEY_START_SPAN 16
#define KEY_START_TYPE "altera_avalon_pio"


/*
 * leds configuration
 *
 */

#define ALT_MODULE_CLASS_leds altera_avalon_pio
#define LEDS_BASE 0x613c0
#define LEDS_BIT_CLEARING_EDGE_REGISTER 0
#define LEDS_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LEDS_CAPTURE 0
#define LEDS_DATA_WIDTH 8
#define LEDS_DO_TEST_BENCH_WIRING 0
#define LEDS_DRIVEN_SIM_VALUE 0
#define LEDS_EDGE_TYPE "NONE"
#define LEDS_FREQ 200000000
#define LEDS_HAS_IN 0
#define LEDS_HAS_OUT 1
#define LEDS_HAS_TRI 0
#define LEDS_IRQ -1
#define LEDS_IRQ_INTERRUPT_CONTROLLER_ID -1
#define LEDS_IRQ_TYPE "NONE"
#define LEDS_NAME "/dev/leds"
#define LEDS_RESET_VALUE 0
#define LEDS_SPAN 16
#define LEDS_TYPE "altera_avalon_pio"


/*
 * ram configuration
 *
 */

#define ALT_MODULE_CLASS_ram altera_avalon_onchip_memory2
#define RAM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define RAM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define RAM_BASE 0x20000
#define RAM_CONTENTS_INFO ""
#define RAM_DUAL_PORT 0
#define RAM_GUI_RAM_BLOCK_TYPE "AUTO"
#define RAM_INIT_CONTENTS_FILE "niosII_ram"
#define RAM_INIT_MEM_CONTENT 1
#define RAM_INSTANCE_ID "NONE"
#define RAM_IRQ -1
#define RAM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define RAM_NAME "/dev/ram"
#define RAM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define RAM_RAM_BLOCK_TYPE "AUTO"
#define RAM_READ_DURING_WRITE_MODE "DONT_CARE"
#define RAM_SINGLE_CLOCK_OP 0
#define RAM_SIZE_MULTIPLE 1
#define RAM_SIZE_VALUE 131072
#define RAM_SPAN 131072
#define RAM_TYPE "altera_avalon_onchip_memory2"
#define RAM_WRITABLE 1


/*
 * rom configuration
 *
 */

#define ALT_MODULE_CLASS_rom altera_avalon_onchip_memory2
#define ROM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ROM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ROM_BASE 0x40000
#define ROM_CONTENTS_INFO ""
#define ROM_DUAL_PORT 0
#define ROM_GUI_RAM_BLOCK_TYPE "M10K"
#define ROM_INIT_CONTENTS_FILE "niosII_rom"
#define ROM_INIT_MEM_CONTENT 1
#define ROM_INSTANCE_ID "NONE"
#define ROM_IRQ -1
#define ROM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ROM_NAME "/dev/rom"
#define ROM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ROM_RAM_BLOCK_TYPE "M10K"
#define ROM_READ_DURING_WRITE_MODE "DONT_CARE"
#define ROM_SINGLE_CLOCK_OP 0
#define ROM_SIZE_MULTIPLE 1
#define ROM_SIZE_VALUE 131072
#define ROM_SPAN 131072
#define ROM_TYPE "altera_avalon_onchip_memory2"
#define ROM_WRITABLE 0


/*
 * sysid configuration
 *
 */

#define ALT_MODULE_CLASS_sysid altera_avalon_sysid_qsys
#define SYSID_BASE 0x613e0
#define SYSID_ID 0
#define SYSID_IRQ -1
#define SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SYSID_NAME "/dev/sysid"
#define SYSID_SPAN 8
#define SYSID_TIMESTAMP 1734510477
#define SYSID_TYPE "altera_avalon_sysid_qsys"

#endif /* __SYSTEM_H_ */