Studentenversion des ESY6/A Praktikums "signal_processing".
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signal_processing.qsf 4.4KB

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  1. # -------------------------------------------------------------------------- #
  2. #
  3. # Copyright (C) 2020 Intel Corporation. All rights reserved.
  4. # Your use of Intel Corporation's design tools, logic functions
  5. # and other software and tools, and any partner logic
  6. # functions, and any output files from any of the foregoing
  7. # (including device programming or simulation files), and any
  8. # associated documentation or information are expressly subject
  9. # to the terms and conditions of the Intel Program License
  10. # Subscription Agreement, the Intel Quartus Prime License Agreement,
  11. # the Intel FPGA IP License Agreement, or other applicable license
  12. # agreement, including, without limitation, that your use is for
  13. # the sole purpose of programming logic devices manufactured by
  14. # Intel and sold by Intel or its authorized distributors. Please
  15. # refer to the applicable agreement for further details, at
  16. # https://fpgasoftware.intel.com/eula.
  17. #
  18. # -------------------------------------------------------------------------- #
  19. #
  20. # Quartus Prime
  21. # Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
  22. # Date created = 23:07:58 June 12, 2022
  23. #
  24. # -------------------------------------------------------------------------- #
  25. #
  26. # Notes:
  27. #
  28. # 1) The default values for assignments are stored in the file:
  29. # signal_processing_assignment_defaults.qdf
  30. # If this file doesn't exist, see file:
  31. # assignment_defaults.qdf
  32. #
  33. # 2) Altera recommends that you do not modify this file. This
  34. # file is updated automatically by the Quartus Prime software
  35. # and any changes you make may be lost or overwritten.
  36. #
  37. # -------------------------------------------------------------------------- #
  38. set_global_assignment -name FAMILY "Cyclone V"
  39. set_global_assignment -name DEVICE 5CSEBA6U23I7
  40. set_global_assignment -name TOP_LEVEL_ENTITY signal_processing
  41. set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
  42. set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:07:58 JUNE 12, 2022"
  43. set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.1 Standard Edition"
  44. set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
  45. set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
  46. set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
  47. set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
  48. set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
  49. set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
  50. set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
  51. set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
  52. set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
  53. set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
  54. set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
  55. set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
  56. set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
  57. set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
  58. set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
  59. set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
  60. set_location_assignment PIN_V11 -to clk_input
  61. set_location_assignment PIN_AH17 -to reset_n
  62. set_location_assignment PIN_AA23 -to leds[7]
  63. set_location_assignment PIN_Y16 -to leds[6]
  64. set_location_assignment PIN_AE26 -to leds[5]
  65. set_location_assignment PIN_AF26 -to leds[4]
  66. set_location_assignment PIN_V15 -to leds[3]
  67. set_location_assignment PIN_V16 -to leds[2]
  68. set_location_assignment PIN_AA24 -to leds[1]
  69. set_location_assignment PIN_W15 -to leds[0]
  70. set_global_assignment -name ENABLE_SIGNALTAP ON
  71. set_global_assignment -name USE_SIGNALTAP_FILE output_files/data_channel_control.stp
  72. #set_global_assignment -name QSYS_FILE niosII.qsys
  73. set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
  74. set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
  75. set_global_assignment -name QIP_FILE niosII/synthesis/niosII.qip
  76. set_global_assignment -name QIP_FILE hardware/system/pll/pll_main.qip
  77. set_global_assignment -name SIP_FILE hardware/system/pll/pll_main.sip
  78. source hdl_sources.qsf
  79. set_global_assignment -name SDC_FILE hardware/signal_processing.sdc
  80. set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top