sachen für task1 und task2
This commit is contained in:
+227
@@ -9328,3 +9328,230 @@ Command-line arguments: -os linux -ws gtk -arch x86_64
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!ENTRY com.st.stm32cube.ide.mcu.debug 4 0 2026-03-24 14:18:01.013
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!MESSAGE Existing sessions are:
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!SESSION 2026-03-24 14:21:01.018 -----------------------------------------------
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eclipse.buildId=Version 1.16.0
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java.version=17.0.11
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java.vendor=Eclipse Adoptium
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BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=de_DE
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Command-line arguments: -os linux -ws gtk -arch x86_64
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!ENTRY com.st.stm32cube.ide.mcu.informationcenter 4 4 2026-03-24 14:21:05.958
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!MESSAGE CubeMX plugin appears to be active, Log4j initialization might be too late.
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!ENTRY com.st.stm32cube.ide.mcu.informationcenter 1 1 2026-03-24 14:21:05.959
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!MESSAGE Log4j2 initialized with config file /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/.metadata/.log4j2.xml
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!ENTRY com.st.stm32cube.ide.mcu.ide 1 1 2026-03-24 14:21:11.141
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!MESSAGE Started RMI Server, listening on port 41337
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!SESSION 2026-03-31 11:20:25.522 -----------------------------------------------
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eclipse.buildId=Version 1.16.0
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java.version=17.0.11
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java.vendor=Eclipse Adoptium
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BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=de_DE
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Command-line arguments: -os linux -ws gtk -arch x86_64
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!ENTRY com.st.stm32cube.ide.mcu.informationcenter 4 4 2026-03-31 11:20:29.815
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!MESSAGE CubeMX plugin appears to be active, Log4j initialization might be too late.
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!ENTRY com.st.stm32cube.ide.mcu.informationcenter 1 1 2026-03-31 11:20:29.816
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!MESSAGE Log4j2 initialized with config file /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/.metadata/.log4j2.xml
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!ENTRY com.st.stm32cube.ide.mcu.ide 1 1 2026-03-31 11:20:33.229
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!MESSAGE Started RMI Server, listening on port 41337
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!SESSION 2026-03-31 13:41:50.718 -----------------------------------------------
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eclipse.buildId=Version 1.16.0
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java.version=17.0.11
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java.vendor=Eclipse Adoptium
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BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=de_DE
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Command-line arguments: -os linux -ws gtk -arch x86_64
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!ENTRY org.eclipse.core.resources 2 10035 2026-03-31 13:41:52.576
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!MESSAGE The workspace exited with unsaved changes in the previous session; refreshing workspace to recover changes.
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!ENTRY com.st.stm32cube.ide.mcu.informationcenter 4 4 2026-03-31 13:41:55.091
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!MESSAGE CubeMX plugin appears to be active, Log4j initialization might be too late.
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!ENTRY com.st.stm32cube.ide.mcu.informationcenter 1 1 2026-03-31 13:41:55.092
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!MESSAGE Log4j2 initialized with config file /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/.metadata/.log4j2.xml
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!ENTRY com.st.stm32cube.ide.mcu.ide 1 1 2026-03-31 13:41:58.079
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!MESSAGE Started RMI Server, listening on port 41337
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!ENTRY org.eclipse.equinox.p2.transport.ecf 4 1002 2026-03-31 13:42:20.010
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!MESSAGE Unable to connect to repository https://sw-center.st.com/stm32cubeide/openstlinux/updatesite1/compositeContent.xml
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!STACK 0
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java.net.ConnectException
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at java.net.http/jdk.internal.net.http.common.Utils.toConnectException(Utils.java:1055)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:198)
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at java.net.http/jdk.internal.net.http.AsyncSSLConnection.connectAsync(AsyncSSLConnection.java:56)
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at java.net.http/jdk.internal.net.http.Http2Connection.createAsync(Http2Connection.java:378)
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at java.net.http/jdk.internal.net.http.Http2ClientImpl.getConnectionFor(Http2ClientImpl.java:126)
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at java.net.http/jdk.internal.net.http.ExchangeImpl.get(ExchangeImpl.java:93)
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at java.net.http/jdk.internal.net.http.Exchange.establishExchange(Exchange.java:343)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl0(Exchange.java:475)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl(Exchange.java:380)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsync(Exchange.java:372)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:408)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsyncImpl$7(MultiExchange.java:449)
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at java.base/java.util.concurrent.CompletableFuture.uniHandle(CompletableFuture.java:934)
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at java.base/java.util.concurrent.CompletableFuture.uniHandleStage(CompletableFuture.java:950)
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at java.base/java.util.concurrent.CompletableFuture.handle(CompletableFuture.java:2340)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:439)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsync0$2(MultiExchange.java:341)
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at java.base/java.util.concurrent.CompletableFuture$UniCompose.tryFire(CompletableFuture.java:1150)
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at java.base/java.util.concurrent.CompletableFuture.postComplete(CompletableFuture.java:510)
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at java.base/java.util.concurrent.CompletableFuture$AsyncSupply.run(CompletableFuture.java:1773)
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at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1136)
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at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:635)
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at java.base/java.lang.Thread.run(Thread.java:840)
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Caused by: java.nio.channels.UnresolvedAddressException
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:149)
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:157)
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at java.base/sun.nio.ch.SocketChannelImpl.checkRemote(SocketChannelImpl.java:816)
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at java.base/sun.nio.ch.SocketChannelImpl.connect(SocketChannelImpl.java:839)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.lambda$connectAsync$0(PlainHttpConnection.java:183)
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at java.base/java.security.AccessController.doPrivileged(AccessController.java:569)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:185)
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... 21 more
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!ENTRY org.eclipse.equinox.p2.transport.ecf 4 1002 2026-03-31 13:42:20.015
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!MESSAGE Unable to connect to repository https://sw-center.st.com/stm32cubeide/updatesite1/compositeContent.xml
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!STACK 0
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java.net.ConnectException
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at java.net.http/jdk.internal.net.http.common.Utils.toConnectException(Utils.java:1055)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:198)
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at java.net.http/jdk.internal.net.http.AsyncSSLConnection.connectAsync(AsyncSSLConnection.java:56)
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at java.net.http/jdk.internal.net.http.Http2Connection.createAsync(Http2Connection.java:378)
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at java.net.http/jdk.internal.net.http.Http2ClientImpl.getConnectionFor(Http2ClientImpl.java:126)
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at java.net.http/jdk.internal.net.http.ExchangeImpl.get(ExchangeImpl.java:93)
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at java.net.http/jdk.internal.net.http.Exchange.establishExchange(Exchange.java:343)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl0(Exchange.java:475)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl(Exchange.java:380)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsync(Exchange.java:372)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:408)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsyncImpl$7(MultiExchange.java:449)
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at java.base/java.util.concurrent.CompletableFuture.uniHandle(CompletableFuture.java:934)
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at java.base/java.util.concurrent.CompletableFuture.uniHandleStage(CompletableFuture.java:950)
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at java.base/java.util.concurrent.CompletableFuture.handle(CompletableFuture.java:2340)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:439)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsync0$2(MultiExchange.java:341)
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at java.base/java.util.concurrent.CompletableFuture$UniCompose.tryFire(CompletableFuture.java:1150)
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at java.base/java.util.concurrent.CompletableFuture.postComplete(CompletableFuture.java:510)
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at java.base/java.util.concurrent.CompletableFuture$AsyncSupply.run(CompletableFuture.java:1773)
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at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1136)
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at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:635)
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at java.base/java.lang.Thread.run(Thread.java:840)
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Caused by: java.nio.channels.UnresolvedAddressException
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:149)
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:157)
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at java.base/sun.nio.ch.SocketChannelImpl.checkRemote(SocketChannelImpl.java:816)
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at java.base/sun.nio.ch.SocketChannelImpl.connect(SocketChannelImpl.java:839)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.lambda$connectAsync$0(PlainHttpConnection.java:183)
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at java.base/java.security.AccessController.doPrivileged(AccessController.java:569)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:185)
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... 21 more
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!ENTRY org.eclipse.equinox.p2.transport.ecf 4 1002 2026-03-31 13:42:20.022
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!MESSAGE Unable to connect to repository https://download.eclipse.org/tools/cdt/releases/latest/compositeContent.xml
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!STACK 0
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java.net.ConnectException
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at java.net.http/jdk.internal.net.http.common.Utils.toConnectException(Utils.java:1055)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:198)
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at java.net.http/jdk.internal.net.http.AsyncSSLConnection.connectAsync(AsyncSSLConnection.java:56)
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at java.net.http/jdk.internal.net.http.Http2Connection.createAsync(Http2Connection.java:378)
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at java.net.http/jdk.internal.net.http.Http2ClientImpl.getConnectionFor(Http2ClientImpl.java:126)
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at java.net.http/jdk.internal.net.http.ExchangeImpl.get(ExchangeImpl.java:93)
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at java.net.http/jdk.internal.net.http.Exchange.establishExchange(Exchange.java:343)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl0(Exchange.java:475)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl(Exchange.java:380)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsync(Exchange.java:372)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:408)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsyncImpl$7(MultiExchange.java:449)
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at java.base/java.util.concurrent.CompletableFuture.uniHandle(CompletableFuture.java:934)
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at java.base/java.util.concurrent.CompletableFuture.uniHandleStage(CompletableFuture.java:950)
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at java.base/java.util.concurrent.CompletableFuture.handle(CompletableFuture.java:2340)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:439)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsync0$2(MultiExchange.java:341)
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at java.base/java.util.concurrent.CompletableFuture$UniCompose.tryFire(CompletableFuture.java:1150)
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at java.base/java.util.concurrent.CompletableFuture.postComplete(CompletableFuture.java:510)
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at java.base/java.util.concurrent.CompletableFuture$AsyncSupply.run(CompletableFuture.java:1773)
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at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1136)
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at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:635)
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at java.base/java.lang.Thread.run(Thread.java:840)
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Caused by: java.nio.channels.UnresolvedAddressException
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:149)
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:157)
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at java.base/sun.nio.ch.SocketChannelImpl.checkRemote(SocketChannelImpl.java:816)
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at java.base/sun.nio.ch.SocketChannelImpl.connect(SocketChannelImpl.java:839)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.lambda$connectAsync$0(PlainHttpConnection.java:183)
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at java.base/java.security.AccessController.doPrivileged(AccessController.java:569)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:185)
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... 21 more
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!ENTRY org.eclipse.equinox.p2.transport.ecf 4 1002 2026-03-31 13:42:20.028
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!MESSAGE Unable to connect to repository https://download.eclipse.org/releases/2023-12/compositeContent.xml
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!STACK 0
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java.net.ConnectException
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at java.net.http/jdk.internal.net.http.common.Utils.toConnectException(Utils.java:1055)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:198)
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at java.net.http/jdk.internal.net.http.AsyncSSLConnection.connectAsync(AsyncSSLConnection.java:56)
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at java.net.http/jdk.internal.net.http.Http2Connection.createAsync(Http2Connection.java:378)
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at java.net.http/jdk.internal.net.http.Http2ClientImpl.getConnectionFor(Http2ClientImpl.java:126)
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at java.net.http/jdk.internal.net.http.ExchangeImpl.get(ExchangeImpl.java:93)
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at java.net.http/jdk.internal.net.http.Exchange.establishExchange(Exchange.java:343)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl0(Exchange.java:475)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl(Exchange.java:380)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsync(Exchange.java:372)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:408)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsyncImpl$7(MultiExchange.java:449)
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at java.base/java.util.concurrent.CompletableFuture.uniHandle(CompletableFuture.java:934)
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at java.base/java.util.concurrent.CompletableFuture.uniHandleStage(CompletableFuture.java:950)
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at java.base/java.util.concurrent.CompletableFuture.handle(CompletableFuture.java:2340)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:439)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsync0$2(MultiExchange.java:341)
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at java.base/java.util.concurrent.CompletableFuture$UniCompose.tryFire(CompletableFuture.java:1150)
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at java.base/java.util.concurrent.CompletableFuture.postComplete(CompletableFuture.java:510)
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at java.base/java.util.concurrent.CompletableFuture$AsyncSupply.run(CompletableFuture.java:1773)
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at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1136)
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at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:635)
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at java.base/java.lang.Thread.run(Thread.java:840)
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Caused by: java.nio.channels.UnresolvedAddressException
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:149)
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:157)
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at java.base/sun.nio.ch.SocketChannelImpl.checkRemote(SocketChannelImpl.java:816)
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at java.base/sun.nio.ch.SocketChannelImpl.connect(SocketChannelImpl.java:839)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.lambda$connectAsync$0(PlainHttpConnection.java:183)
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at java.base/java.security.AccessController.doPrivileged(AccessController.java:569)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:185)
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... 21 more
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!ENTRY org.eclipse.cdt.dsf.gdb 4 104 2026-03-31 13:56:39.797
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!MESSAGE Program file does not exist
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!STACK 0
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java.io.FileNotFoundException: /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/task1/Debug/task1.elf not found
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at org.eclipse.cdt.dsf.gdb.launching.LaunchUtils.verifyProgramPath(LaunchUtils.java:130)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.checkBinaryDetails(GdbLaunchDelegate.java:330)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launchDebugSession(GdbLaunchDelegate.java:152)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launchDebugger(GdbLaunchDelegate.java:109)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launch(GdbLaunchDelegate.java:97)
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at com.st.stm32cube.ide.mcu.debug.launch.DSFDelegate.launch(DSFDelegate.java:334)
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at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:805)
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at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:716)
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at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1040)
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at org.eclipse.debug.internal.ui.DebugUIPlugin$1.run(DebugUIPlugin.java:1243)
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at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63)
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!SUBENTRY 1 org.eclipse.cdt.dsf.gdb 4 104 2026-03-31 13:56:39.797
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!MESSAGE /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/task1/Debug/task1.elf not found
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!STACK 0
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java.io.FileNotFoundException: /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/task1/Debug/task1.elf not found
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||||
at org.eclipse.cdt.dsf.gdb.launching.LaunchUtils.verifyProgramPath(LaunchUtils.java:130)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.checkBinaryDetails(GdbLaunchDelegate.java:330)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launchDebugSession(GdbLaunchDelegate.java:152)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launchDebugger(GdbLaunchDelegate.java:109)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launch(GdbLaunchDelegate.java:97)
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at com.st.stm32cube.ide.mcu.debug.launch.DSFDelegate.launch(DSFDelegate.java:334)
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at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:805)
|
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at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:716)
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at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1040)
|
||||
at org.eclipse.debug.internal.ui.DebugUIPlugin$1.run(DebugUIPlugin.java:1243)
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||||
at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63)
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||||
@@ -52,3 +52,5 @@
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||||
*** SESSION März 13, 2026 10:49:11.272 -----------------------------------------
|
||||
*** SESSION März 16, 2026 12:55:55.445 -----------------------------------------
|
||||
*** SESSION März 24, 2026 14:01:49.132 -----------------------------------------
|
||||
*** SESSION März 24, 2026 14:11:29.704 -----------------------------------------
|
||||
*** SESSION März 24, 2026 14:21:04.465 -----------------------------------------
|
||||
|
||||
Binary file not shown.
@@ -553,3 +553,93 @@ Target all ready
|
||||
14:19:07 **** Incremental Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
Target all ready
|
||||
14:56:35 **** Incremental Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
Target all ready
|
||||
14:57:35 **** Clean-only build of configuration Debug for project task2 ****
|
||||
make -j12 clean
|
||||
14:57:51 **** Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
|
||||
arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
|
||||
arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
|
||||
arm-none-eabi-size task2.elf
|
||||
text data bss dec hex filename
|
||||
648 0 0 648 288 task2.elf
|
||||
Target all ready
|
||||
14:58:02 **** Incremental Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
Target all ready
|
||||
14:58:10 **** Incremental Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
Target all ready
|
||||
13:53:05 **** Incremental Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
|
||||
task2.s: Assembler messages:
|
||||
task2.s:346: Error: junk at end of line, first unrecognized character is `h'
|
||||
make: *** [makefile:74: task2.o] Error 1
|
||||
"make -j12 all" terminated with exit code 2. Build might be incomplete.
|
||||
13:53:51 **** Incremental Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
|
||||
arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
|
||||
arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
|
||||
arm-none-eabi-size task2.elf
|
||||
text data bss dec hex filename
|
||||
532 0 0 532 214 task2.elf
|
||||
Target all ready
|
||||
13:56:03 **** Build of configuration Debug for project task1 ****
|
||||
make -j12 all
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"Startup/startup_stm32g431kbtx.d" -MT"Startup/startup_stm32g431kbtx.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Startup/startup_stm32g431kbtx.o" "../Startup/startup_stm32g431kbtx.s"
|
||||
arm-none-eabi-gcc "../Startup/syscalls.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Startup/syscalls.d" -MT"Startup/syscalls.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Startup/syscalls.o"
|
||||
arm-none-eabi-gcc "../Startup/sysmem.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Startup/sysmem.d" -MT"Startup/sysmem.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Startup/sysmem.o"
|
||||
arm-none-eabi-gcc "../Src/sketch.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/sketch.d" -MT"Src/sketch.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/sketch.o"
|
||||
arm-none-eabi-gcc "../Src/task1.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/task1.d" -MT"Src/task1.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/task1.o"
|
||||
arm-none-eabi-gcc "../Src/task1_it.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/task1_it.d" -MT"Src/task1_it.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/task1_it.o"
|
||||
../Src/sketch.c: In function 'main':
|
||||
../Src/sketch.c:11:42: error: expected expression before ')' token
|
||||
11 | while(/*schalter nicht gedrückt*/){}
|
||||
| ^
|
||||
../Src/sketch.c:12:9: warning: implicit declaration of function 'delay' [-Wimplicit-function-declaration]
|
||||
12 | delay(10);
|
||||
| ^~~~~
|
||||
../Src/sketch.c:13:39: error: expected expression before ')' token
|
||||
13 | while(/*schalter losgelassen*/){}
|
||||
| ^
|
||||
../Src/sketch.c:18:39: error: request for member 'length' in something not a structure or union
|
||||
18 | for(int i; i < reihenfolge.length - 1 && aktiv = 1; i ++){
|
||||
| ^
|
||||
../Src/sketch.c:20:20: warning: suggest parentheses around assignment used as truth value [-Wparentheses]
|
||||
20 | if(i = 0){/*alles bis auf LED0 auschalten*/}
|
||||
| ^
|
||||
../Src/sketch.c:21:20: warning: suggest parentheses around assignment used as truth value [-Wparentheses]
|
||||
21 | if(i = 1){/*..*/}
|
||||
| ^
|
||||
../Src/sketch.c:24:44: error: expected expression before ')' token
|
||||
24 | if(/*schalter gerückt*/){
|
||||
| ^
|
||||
../Src/sketch.c:32:42: error: expected expression before ')' token
|
||||
32 | while(/*Taster gedrückt*/){}
|
||||
| ^
|
||||
make: *** [Src/subdir.mk:25: Src/sketch.o] Error 1
|
||||
make: *** Waiting for unfinished jobs....
|
||||
../Src/task1.c: In function 'GPIO_init':
|
||||
../Src/task1.c:169:22: error: expected expression before '<<' token
|
||||
169 | GPIOA->MODER &= ~(3 ^<< 2); // Versuch: LED 1 Mode löschen :klappt so
|
||||
| ^~
|
||||
make: *** [Src/subdir.mk:25: Src/task1.o] Error 1
|
||||
"make -j12 all" terminated with exit code 2. Build might be incomplete.
|
||||
13:56:35 **** Incremental Build of configuration Debug for project task1 ****
|
||||
make -j12 all
|
||||
arm-none-eabi-gcc "../Src/sketch.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/sketch.d" -MT"Src/sketch.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/sketch.o"
|
||||
arm-none-eabi-gcc "../Src/task1.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/task1.d" -MT"Src/task1.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/task1.o"
|
||||
../Src/task1.c: In function 'GPIO_init':
|
||||
../Src/task1.c:169:22: error: expected expression before '<<' token
|
||||
169 | GPIOA->MODER &= ~(3 ^<< 2); // Versuch: LED 1 Mode löschen :klappt so
|
||||
| ^~
|
||||
make: *** [Src/subdir.mk:25: Src/task1.o] Error 1
|
||||
"make -j12 all" terminated with exit code 2. Build might be incomplete.
|
||||
14:02:22 **** Incremental Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
Target all ready
|
||||
|
||||
@@ -1,9 +1,13 @@
|
||||
14:13:43 **** Clean-only build of configuration Debug for project task1 ****
|
||||
make -j12 clean
|
||||
rm -rf ./Startup/startup_stm32g431kbtx.d ./Startup/startup_stm32g431kbtx.o ./Startup/syscalls.cyclo ./Startup/syscalls.d ./Startup/syscalls.o ./Startup/syscalls.su ./Startup/sysmem.cyclo ./Startup/sysmem.d ./Startup/sysmem.o ./Startup/sysmem.su
|
||||
rm -rf ./Src/task1.cyclo ./Src/task1.d ./Src/task1.o ./Src/task1.su ./Src/task1_it.cyclo ./Src/task1_it.d ./Src/task1_it.o ./Src/task1_it.su
|
||||
rm -rf default.size.stdout task1.elf task1.list task1.map
|
||||
|
||||
13:56:35 **** Incremental Build of configuration Debug for project task1 ****
|
||||
make -j12 all
|
||||
arm-none-eabi-gcc "../Src/sketch.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/sketch.d" -MT"Src/sketch.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/sketch.o"
|
||||
arm-none-eabi-gcc "../Src/task1.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/task1.d" -MT"Src/task1.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/task1.o"
|
||||
../Src/task1.c: In function 'GPIO_init':
|
||||
../Src/task1.c:169:22: error: expected expression before '<<' token
|
||||
169 | GPIOA->MODER &= ~(3 ^<< 2); // Versuch: LED 1 Mode löschen :klappt so
|
||||
| ^~
|
||||
make: *** [Src/subdir.mk:25: Src/task1.o] Error 1
|
||||
"make -j12 all" terminated with exit code 2. Build might be incomplete.
|
||||
|
||||
14:13:44 Build Finished. 0 errors, 0 warnings. (took 187ms)
|
||||
13:56:35 Build Failed. 2 errors, 0 warnings. (took 166ms)
|
||||
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
14:19:07 **** Incremental Build of configuration Debug for project task2 ****
|
||||
14:02:22 **** Incremental Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
Target all ready
|
||||
|
||||
14:19:07 Build Finished. 0 errors, 0 warnings. (took 182ms)
|
||||
14:02:22 Build Finished. 0 errors, 0 warnings. (took 121ms)
|
||||
|
||||
|
||||
+328
@@ -0,0 +1,328 @@
|
||||
#****************************************************************************************#
|
||||
# Project: task2 - ASM: Interrupts
|
||||
# File: task2.s
|
||||
# Hardware: STefi Light v1.1
|
||||
# Processor: STM32G431KBT6U
|
||||
#****************************************************************************************#
|
||||
|
||||
.include "G431_addr.s"
|
||||
|
||||
// Zusätzliche und benötigte Adressen
|
||||
.equ RCC_AHB2ENR, 0x4002104C
|
||||
.equ RCC_APB2ENR, 0x40021060
|
||||
|
||||
.equ GPIOA_MODER, 0x48000000
|
||||
.equ GPIOA_ODR, 0x48000014
|
||||
|
||||
.equ GPIOC_MODER, 0x48000800
|
||||
.equ GPIOC_PUPDR, 0x4800080C
|
||||
.equ GPIOC_IDR, 0x48000810
|
||||
|
||||
.equ SYSCFG_BASE, 0x40010000
|
||||
.equ SYSCFG_EXTICR4, (SYSCFG_BASE + 0x14)
|
||||
|
||||
.equ EXTI_BASE, 0x40010400
|
||||
.equ EXTI_IMR1, (EXTI_BASE + 0x00)
|
||||
.equ EXTI_FTSR1, (EXTI_BASE + 0x0C)
|
||||
.equ EXTI_PR1, (EXTI_BASE + 0x14)
|
||||
|
||||
.equ NVIC_ISER1, 0xE000E104
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.section .vectortable,"a" // vector table at begin of ROM
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
|
||||
.word 0x20004000 // initial Stack Pointer
|
||||
.word 0x08000401 // initial Program Counter
|
||||
.word _ISR_NMI // non-masking interrupt
|
||||
.word _ISR_HARDF // hard fault interrupt
|
||||
|
||||
.space 0xD0 // padding 208 Bytes bis Offset 0xE0 (EXTI15_10 IRQ 40)
|
||||
.word _ISR_S0_S1 // gemeinsamer Interrupt für PC13 (S0) und PC14 (S1)
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.text // section .text (default section for program code)
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global init
|
||||
.type init, %function
|
||||
init:
|
||||
CPSID i // disable interrupts globally
|
||||
|
||||
MOVS r0, #0 // safely initialize the GPRs
|
||||
MOVS r1, #0
|
||||
MOVS r2, #0
|
||||
MOVS r3, #0
|
||||
MOVS r4, #0
|
||||
MOVS r5, #0
|
||||
MOVS r6, #0
|
||||
MOVS r7, #0
|
||||
MOV r8, r0
|
||||
MOV r9, r0
|
||||
MOV r10, r0
|
||||
MOV r11, r0
|
||||
MOV r12, r0
|
||||
|
||||
#--- enable port clocking
|
||||
LDR r1, =RCC_AHB2ENR
|
||||
MOVS r2, #0x05 // Bit 0 (GPIOA) und Bit 2 (GPIOC)
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#--- port init
|
||||
#- LEDs (PA0-PA3)
|
||||
LDR r1, =GPIOA_MODER
|
||||
LDR r2, =0x000000FF // Maske PA0-PA3
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
LDR r2, =0x00000055 // Maske Output 0101 0101
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- switch LED off
|
||||
LDR r1, =GPIOA_ODR
|
||||
MOVS r2, #0x0F // Maske LED0-3
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- buttons (PC13, PC14 als Input)
|
||||
LDR r1, =GPIOC_MODER
|
||||
LDR r2, =0x3C000000 // Maske Bits 26-29
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- Pull-Up für PC13, PC14
|
||||
LDR r1, =GPIOC_PUPDR
|
||||
LDR r2, =0x3C000000
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
LDR r2, =0x14000000 // 01 = Pull-Up für PC13 (Bits 27:26) und PC14 (Bits 29:28)
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#--- button interrupt config
|
||||
|
||||
#- enable clock for SYSCFG module
|
||||
LDR r1, =RCC_APB2ENR
|
||||
MOVS r2, #0x01
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
|
||||
LDR r1, =SYSCFG_EXTICR4
|
||||
LDR r2, =0x00000FF0 // Maske für EXTI13 (Bits 7:4) und EXTI14 (Bits 11:8)
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
LDR r2, =0x00000220 // Port C (0010) für EXTI13 und EXTI14
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- configure lines in EXTI module (EXTI_* registers)
|
||||
LDR r1, =EXTI_FTSR1 // Fallende Flanke
|
||||
LDR r2, =0x00006000 // Bits 13 und 14
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =EXTI_IMR1 // Maskierung aufheben
|
||||
LDR r2, =0x00006000
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- NVIC: set interrupt priority, clear pending bits
|
||||
LDR r1, =NVIC_ISER1
|
||||
LDR r2, =0x00000100 // Bit 8 für IRQ 40 (EXTI15_10)
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
CPSIE i // enable interrupts globally
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global main
|
||||
.type main, %function
|
||||
main:
|
||||
WFI
|
||||
B main
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global delay
|
||||
.type delay, %function
|
||||
delay:
|
||||
LDR r0, =106000 // Entprell-Zeit ~20ms
|
||||
.L1:
|
||||
SUBS r0, r0, #1
|
||||
BNE .L1
|
||||
BX lr
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.global stop
|
||||
stop:
|
||||
NOP
|
||||
B stop
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.lp1:
|
||||
.ltorg
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.section .exhand,"ax" // section for exception handlers
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_NMI, %function
|
||||
_ISR_NMI:
|
||||
LDR r1, =RCC_AHB2ENR
|
||||
MOV r2, #0x01
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_MODER
|
||||
MOVS r2, #0xFF
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
MOVS r2, #0x44
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_ODR
|
||||
MOVS r2, #0x0A
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
B _ISR_NMI
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_HARDF, %function
|
||||
_ISR_HARDF:
|
||||
LDR r1, =RCC_AHB2ENR
|
||||
MOV r2, #0x01
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_MODER
|
||||
MOVS r2, #0xFF
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
MOVS r2, #0x11
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_ODR
|
||||
MOVS r2, #0x05
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
B _ISR_HARDF
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_S0_S1, %function
|
||||
_ISR_S0_S1:
|
||||
PUSH {r4, r5, lr} // Wichtig: Register sichern gemäß AAPCS
|
||||
|
||||
_check_S0:
|
||||
LDR r4, =EXTI_PR1
|
||||
LDR r5, [r4, #0]
|
||||
LDR r2, =0x2000 // Maske für S0 (PC13 / Bit 13)
|
||||
TST r5, r2
|
||||
BEQ _check_S1 // Wenn Bit 13 nicht gesetzt, überspringen
|
||||
|
||||
#--- do the work S0
|
||||
BL delay // Entprellen
|
||||
|
||||
LDR r0, =GPIOC_IDR
|
||||
LDR r1, [r0, #0]
|
||||
LDR r2, =0x2000
|
||||
TST r1, r2
|
||||
BNE _clear_S0 // Abbruch, wenn High (Taster prellt / schon losgelassen)
|
||||
|
||||
LDR r0, =GPIOA_ODR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x09 // LED0 & LED3 toggeln (1001)
|
||||
EORS r1, r2
|
||||
STR r1, [r0, #0]
|
||||
|
||||
_clear_S0:
|
||||
#--- clear interrupt flag S0
|
||||
LDR r4, =EXTI_PR1
|
||||
LDR r5, =0x2000
|
||||
STR r5, [r4, #0]
|
||||
|
||||
_check_S1:
|
||||
LDR r4, =EXTI_PR1
|
||||
LDR r5, [r4, #0]
|
||||
LDR r2, =0x4000 // Maske für S1 (PC14 / Bit 14)
|
||||
TST r5, r2
|
||||
BEQ _leave_ISR // Wenn Bit 14 nicht gesetzt, Ende
|
||||
|
||||
#--- do the work S1
|
||||
BL delay
|
||||
|
||||
LDR r0, =GPIOC_IDR
|
||||
LDR r1, [r0, #0]
|
||||
LDR r2, =0x4000
|
||||
TST r1, r2
|
||||
BNE _clear_S1 // Abbruch, wenn High
|
||||
|
||||
LDR r0, =GPIOA_ODR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x06 // LED1 & LED2 toggeln (0110)
|
||||
EORS r1, r2
|
||||
STR r1, [r0, #0]
|
||||
|
||||
_clear_S1:
|
||||
#--- clear interrupt flag S1
|
||||
LDR r4, =EXTI_PR1
|
||||
LDR r5, =0x4000
|
||||
STR r5, [r4, #0]
|
||||
|
||||
_leave_ISR:
|
||||
#--- leave ISR
|
||||
POP {r4, r5, pc} // Register wiederherstellen und zurückkehren
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.lp2:
|
||||
.ltorg
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.end
|
||||
|
||||
#************************************** E O F *******************************************#
|
||||
+347
@@ -0,0 +1,347 @@
|
||||
#****************************************************************************************#
|
||||
# Project: task2 - ASM: Interrupts
|
||||
# File: task2.s
|
||||
# Hardware: STefi Light v1.1
|
||||
# Processor: STM32G431KBT6U
|
||||
#****************************************************************************************#
|
||||
|
||||
.include "G431_addr.s"
|
||||
|
||||
// Falls in G431_addr.s vorhanden, diesen Block löschen um Fehler zu vermeiden:
|
||||
.equ RCC_AHB2ENR, 0x4002104C
|
||||
.equ RCC_APB2ENR, 0x40021060
|
||||
|
||||
.equ GPIOA_MODER, 0x48000000
|
||||
.equ GPIOA_ODR, 0x48000014
|
||||
|
||||
.equ GPIOB_MODER, 0x48000400
|
||||
.equ GPIOB_PUPDR, 0x4800040C
|
||||
.equ GPIOB_IDR, 0x48000410
|
||||
|
||||
.equ SYSCFG_BASE, 0x40010000
|
||||
.equ SYSCFG_EXTICR1, (SYSCFG_BASE + 0x08)
|
||||
.equ SYSCFG_EXTICR2, (SYSCFG_BASE + 0x0C)
|
||||
|
||||
.equ EXTI_BASE, 0x40010400
|
||||
.equ EXTI_IMR1, (EXTI_BASE + 0x00)
|
||||
.equ EXTI_FTSR1, (EXTI_BASE + 0x0C)
|
||||
.equ EXTI_PR1, (EXTI_BASE + 0x14)
|
||||
|
||||
.equ NVIC_ISER0, 0xE000E100
|
||||
|
||||
.equ DBGMCU_CR, 0xE0042004 // Adresse des Debug Configuration Registers
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.section .vectortable,"a"
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
|
||||
.word 0x20004000 // initial Stack Pointer
|
||||
.word init // initial Program Counter
|
||||
.word _ISR_NMI // non-masking interrupt
|
||||
.word _ISR_HARDF // hard fault interrupt
|
||||
|
||||
.space 0x48 // Padding 72 Bytes (Offset 0x10 -> 0x58)
|
||||
.word _ISR_EXTI0 // EXTI0_IRQHandler (PB0 / S0) - IRQ 6
|
||||
|
||||
.space 0x0C // Padding 12 Bytes (Offset 0x5C -> 0x68)
|
||||
.word _ISR_EXTI4 // EXTI4_IRQHandler (PB4 / S1) - IRQ 10
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.text
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global init
|
||||
.type init, %function
|
||||
init:
|
||||
CPSID i
|
||||
|
||||
MOVS r0, #0
|
||||
MOVS r1, #0
|
||||
MOVS r2, #0
|
||||
MOVS r3, #0
|
||||
MOVS r4, #0
|
||||
MOVS r5, #0
|
||||
MOVS r6, #0
|
||||
MOVS r7, #0
|
||||
MOV r8, r0
|
||||
MOV r9, r0
|
||||
MOV r10, r0
|
||||
MOV r11, r0
|
||||
MOV r12, r0
|
||||
|
||||
#--- enable port clocking (GPIOA, GPIOB)
|
||||
LDR r1, =RCC_AHB2ENR
|
||||
MOVS r2, #0x03 // Bit 0 (GPIOA) und Bit 1 (GPIOB)
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#--- port init
|
||||
#- LEDs (PA0 - PA3) als Output
|
||||
LDR r1, =GPIOA_MODER
|
||||
LDR r2, =0x000000FF
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
LDR r2, =0x00000055
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- switch LED off
|
||||
LDR r1, =GPIOA_ODR
|
||||
MOVS r2, #0x0F
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- buttons (PB0, PB4) als Input
|
||||
LDR r1, =GPIOB_MODER
|
||||
LDR r2, =0x00000303 // Maske Bits 0:1 (PB0) und 8:9 (PB4)
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- Pull-Up für PB0, PB4
|
||||
LDR r1, =GPIOB_PUPDR
|
||||
LDR r2, =0x00000303
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
LDR r2, =0x00000101 // 01 = Pull-Up für PB0 und PB4
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#--- button interrupt config
|
||||
|
||||
#- enable clock for SYSCFG module
|
||||
LDR r1, =RCC_APB2ENR
|
||||
MOVS r2, #0x01
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- connect GPIO pins to EXTI lines
|
||||
LDR r1, =SYSCFG_EXTICR1 // EXTI0 (PB0)
|
||||
LDR r2, =0x000F // Maske EXTI0 (Bits 3:0)
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
MOVS r2, #0x0001 // Port B (0001)
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =SYSCFG_EXTICR2 // EXTI4 (PB4)
|
||||
LDR r2, =0x000F // Maske EXTI4 (Bits 3:0)
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
MOVS r2, #0x0001 // Port B (0001)
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- configure EXTI lines (falling edge, unmask)
|
||||
LDR r1, =EXTI_FTSR1
|
||||
MOVS r2, #0x11 // Bit 0 (EXTI0) und Bit 4 (EXTI4)
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =EXTI_IMR1
|
||||
MOVS r2, #0x11 // Bit 0 und Bit 4
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- NVIC: enable interrupts EXTI0 (IRQ 6) & EXTI4 (IRQ 10)
|
||||
LDR r1, =NVIC_ISER0
|
||||
LDR r2, =0x00000440 // Bit 6 (EXTI0) und Bit 10 (EXTI4)
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#--- wachhalten während WFI
|
||||
LDR r1, =DBGMCU_CR
|
||||
LDR r0, [r1, #0]
|
||||
MOVS r2, #0x07 // Setzt DBG_SLEEP, DBG_STOP und DBG_STANDBY Bits
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
CPSIE i
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global main
|
||||
.type main, %function
|
||||
main:
|
||||
WFI
|
||||
B main
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global delay
|
||||
.type delay, %function
|
||||
delay:
|
||||
LDR r0, =106000
|
||||
.L1:
|
||||
SUBS r0, r0, #1
|
||||
BNE .L1
|
||||
BX lr
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.global stop
|
||||
stop:
|
||||
NOP
|
||||
B stop
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.lp1:
|
||||
.ltorg
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.section .exhand,"ax"
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_NMI, %function
|
||||
_ISR_NMI:
|
||||
LDR r1, =RCC_AHB2ENR
|
||||
MOV r2, #0x01
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_MODER
|
||||
MOVS r2, #0xFF
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
MOVS r2, #0x44
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_ODR
|
||||
MOVS r2, #0x0A
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
B _ISR_NMI
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_HARDF, %function
|
||||
_ISR_HARDF:
|
||||
LDR r1, =RCC_AHB2ENR
|
||||
MOV r2, #0x01
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_MODER
|
||||
MOVS r2, #0xFF
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
MOVS r2, #0x11
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_ODR
|
||||
MOVS r2, #0x05
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
B _ISR_HARDF
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_EXTI0, %function
|
||||
_ISR_EXTI0:
|
||||
PUSH {lr}
|
||||
|
||||
#--- Entprellen
|
||||
BL delay
|
||||
|
||||
#--- Überprüfen, ob Taster noch gedrückt ist (PB0)
|
||||
LDR r0, =GPIOB_IDR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x01
|
||||
TST r1, r2
|
||||
BNE _clear_exti0
|
||||
|
||||
#--- LED0 & LED3 toggeln (1001 = 0x09)
|
||||
LDR r0, =GPIOA_ODR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x09
|
||||
EORS r1, r2
|
||||
STR r1, [r0, #0]
|
||||
|
||||
_clear_exti0:
|
||||
#--- Interrupt Flag löschen
|
||||
LDR r0, =EXTI_PR1
|
||||
MOVS r1, #0x01
|
||||
STR r1, [r0, #0]
|
||||
|
||||
POP {pc}
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_EXTI4, %function
|
||||
_ISR_EXTI4:
|
||||
PUSH {lr}
|
||||
|
||||
#--- Entprellen
|
||||
BL delay
|
||||
|
||||
#--- Überprüfen, ob Taster noch gedrückt ist (PB4)
|
||||
LDR r0, =GPIOB_IDR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x10
|
||||
TST r1, r2
|
||||
BNE _clear_exti4
|
||||
|
||||
#--- LED1 & LED2 toggeln (0110 = 0x06)
|
||||
LDR r0, =GPIOA_ODR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x06
|
||||
EORS r1, r2
|
||||
STR r1, [r0, #0]
|
||||
|
||||
_clear_exti4:
|
||||
#--- Interrupt Flag löschen
|
||||
LDR r0, =EXTI_PR1
|
||||
MOVS r1, #0x10
|
||||
STR r1, [r0, #0]
|
||||
|
||||
POP {pc}
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.lp2:
|
||||
.ltorg
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.end
|
||||
hu
|
||||
+764
@@ -0,0 +1,764 @@
|
||||
#*****************************************************************************************
|
||||
# Project: task2 - switch triggered LEDs
|
||||
# File: G431_addr.s
|
||||
#
|
||||
# Language: ASM
|
||||
#
|
||||
# Hardware: STefi v1.1
|
||||
# Processor: STM32G431KBT6U
|
||||
#
|
||||
# Author: Manuel Lederhofer
|
||||
# Datum: 20.08.2015
|
||||
#
|
||||
# Version: 3.0
|
||||
# History:
|
||||
# 20.08.2015 ML create file
|
||||
# 07.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
|
||||
# 27.02.2019 ML change from absolute addresses to BASE + OFFSET notation and
|
||||
# add more timer modules
|
||||
# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
|
||||
#
|
||||
# Status: working
|
||||
#
|
||||
# Description:
|
||||
# Connects assembly addresses for STM32G431 MCU to symbolic register names
|
||||
# used in the datasheets.
|
||||
#
|
||||
# Notes:
|
||||
# - default MCU speed at startup is 16 MHz.
|
||||
#
|
||||
# ToDo:
|
||||
# - none -
|
||||
#*****************************************************************************************
|
||||
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# MCU Bus Base Addresses
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ APB1_BASE, 0x40000000
|
||||
.equ APB2_BASE, 0x40010000
|
||||
.equ AHB1_BASE, 0x40020000
|
||||
.equ AHB2_BASE, 0x48000000
|
||||
.equ AHB3_BASE, 0xA0000000 //!!! FSMC + QSPI registers = AHB3 ?
|
||||
.equ PPB_BASE, 0xE0000000 /* Cortex M4 with FPU Internal Peripherals */
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# System Configuration Controller
|
||||
#
|
||||
# address space: 0x4001_0000 .. 0x4001_0029
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ SYSCFG_BASE, APB2_BASE
|
||||
|
||||
.equ SYSCFG_MEMRMP, SYSCFG_BASE + 0x00
|
||||
.equ SYSCFG_CFGR1, SYSCFG_BASE + 0x04
|
||||
.equ SYSCFG_EXTICR1, SYSCFG_BASE + 0x08
|
||||
.equ SYSCFG_EXTICR2, SYSCFG_BASE + 0x0C
|
||||
.equ SYSCFG_EXTICR3, SYSCFG_BASE + 0x10
|
||||
.equ SYSCFG_EXTICR4, SYSCFG_BASE + 0x14
|
||||
.equ SYSCFG_SCSR, SYSCFG_BASE + 0x18
|
||||
.equ SYSCFG_CFGR2, SYSCFG_BASE + 0x1C
|
||||
.equ SYSCFG_SWPR, SYSCFG_BASE + 0x20
|
||||
.equ SYSCFG_SKR, SYSCFG_BASE + 0x24
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# Extended Interrupts And Events Controller
|
||||
#
|
||||
# address space: 0x4001_0400 .. 0x4001_07FF
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ EXTI_BASE, APB2_BASE + 0x400
|
||||
|
||||
.equ EXTI_IMR1, EXTI_BASE + 0x00
|
||||
.equ EXTI_EMR1, EXTI_BASE + 0x04
|
||||
.equ EXTI_RTSR1, EXTI_BASE + 0x08
|
||||
.equ EXTI_FTSR1, EXTI_BASE + 0x0C
|
||||
.equ EXTI_SWIER1, EXTI_BASE + 0x10
|
||||
.equ EXTI_PR1, EXTI_BASE + 0x14
|
||||
|
||||
.equ EXTI_IMR2, EXTI_BASE + 0x20
|
||||
.equ EXTI_EMR2, EXTI_BASE + 0x24
|
||||
.equ EXTI_RTSR2, EXTI_BASE + 0x28
|
||||
.equ EXTI_FTSR2, EXTI_BASE + 0x2C
|
||||
.equ EXTI_SWIER2, EXTI_BASE + 0x30
|
||||
.equ EXTI_PR2, EXTI_BASE + 0x34
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# TIM module common configuration
|
||||
#
|
||||
# Every timer has 1 KB address space:
|
||||
#
|
||||
# TIM2 .. TIM7: 0x4000_0000 .. 0x4000_17FF (APB1)
|
||||
# TIM1: 0x4001_2C00 .. 0x4001_2FFF (APB2)
|
||||
# TIM8: 0x4001_3400 .. 0x4001_37FF (APB2)
|
||||
# TIM15 .. TIM17: 0x4001_4000 .. 0x4001_4BFF (APB2)
|
||||
# TIM20: 0x4001_5000 .. 0x4001_53FF (APB2)
|
||||
#
|
||||
# note:
|
||||
# TIM2 + TIM5 are 32 bit timers. All others have a width of 16 bit.
|
||||
# Below, the timers on one line share a common register set description.
|
||||
#
|
||||
# TIM 1, 8, 20 advances control timers
|
||||
# TIM 2, 3, 4, 5 general purpose timers (TIM2/5 = 32 bit)
|
||||
# TIM 15 general purpose timers
|
||||
# TIM 16, 17 general purpose timers
|
||||
# TIM 6, 7 basic timers
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ TIM_CR1_OFFSET, 0x00
|
||||
.equ TIM_CR2_OFFSET, 0x04
|
||||
.equ TIM_SMCR_OFFSET, 0x08
|
||||
.equ TIM_DIER_OFFSET, 0x0C
|
||||
.equ TIM_SR_OFFSET, 0x10
|
||||
.equ TIM_EGR_OFFSET, 0x14
|
||||
.equ TIM_CCMR1_OFFSET, 0x18
|
||||
.equ TIM_CCMR2_OFFSET, 0x1C
|
||||
.equ TIM_CCER_OFFSET, 0x20
|
||||
.equ TIM_CNT_OFFSET, 0x24
|
||||
.equ TIM_PSC_OFFSET, 0x28
|
||||
.equ TIM_ARR_OFFSET, 0x2C
|
||||
.equ TIM_RCR_OFFSET, 0x30
|
||||
.equ TIM_CCR1_OFFSET, 0x34
|
||||
.equ TIM_CCR2_OFFSET, 0x38
|
||||
.equ TIM_CCR3_OFFSET, 0x3C
|
||||
.equ TIM_CCR4_OFFSET, 0x40
|
||||
.equ TIM_BDTR_OFFSET, 0x44
|
||||
.equ TIM_CCR5_OFFSET, 0x48
|
||||
.equ TIM_CCR6_OFFSET, 0x4C
|
||||
.equ TIM_CCMR3_OFFSET, 0x50
|
||||
.equ TIM_DTR2_OFFSET, 0x54
|
||||
.equ TIM_ECR_OFFSET, 0x58
|
||||
.equ TIM_TISEL_OFFSET, 0x5C
|
||||
.equ TIM_AF1_OFFSET, 0x60
|
||||
.equ TIM_AF2_OFFSET, 0x64
|
||||
.equ TIM_OR1_OFFSET, 0x68
|
||||
|
||||
.equ TIM_DCR_OFFSET, 0x3DC
|
||||
.equ TIM_DMAR_OFFSET, 0x3E0
|
||||
|
||||
#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
|
||||
|
||||
#--- Genral Purpose Timer - TIM2 / address space: 0x4000_0000 .. 0x4000_03FF
|
||||
|
||||
.equ TIM2_BASE, APB1_BASE
|
||||
|
||||
.equ TIM2_CR1, TIM2_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM2_CR2, TIM2_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM2_SMCR, TIM2_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM2_DIER, TIM2_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM2_SR, TIM2_BASE + TIM_SR_OFFSET
|
||||
.equ TIM2_EGR, TIM2_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM2_CCMR1, TIM2_BASE + TIM_CCMR1_OFFSET
|
||||
.equ TIM2_CCMR2, TIM2_BASE + TIM_CCMR2_OFFSET
|
||||
.equ TIM2_CCER, TIM2_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM2_CNT, TIM2_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM2_PSC, TIM2_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM2_ARR, TIM2_BASE + TIM_ARR_OFFSET
|
||||
|
||||
.equ TIM2_CCR1, TIM2_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM2_CCR2, TIM2_BASE + TIM_CCR2_OFFSET
|
||||
.equ TIM2_CCR3, TIM2_BASE + TIM_CCR3_OFFSET
|
||||
.equ TIM2_CCR4, TIM2_BASE + TIM_CCR4_OFFSET
|
||||
|
||||
.equ TIM2_ECR, TIM2_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM2_TISEL, TIM2_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM2_AF1, TIM2_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM2_AF2, TIM2_BASE + TIM_ECR_OFFSET
|
||||
|
||||
.equ TIM2_DCR, TIM2_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM2_DMAR, TIM2_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Genral Purpose Timer - TIM3 / address space: 0x4000_0400 .. 0x4000_07FF
|
||||
|
||||
.equ TIM3_BASE, APB1_BASE + 0x400
|
||||
|
||||
.equ TIM3_CR1, TIM3_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM3_CR2, TIM3_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM3_SMCR, TIM3_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM3_DIER, TIM3_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM3_SR, TIM3_BASE + TIM_SR_OFFSET
|
||||
.equ TIM3_EGR, TIM3_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM3_CCMR1, TIM3_BASE + TIM_CCMR1_OFFSET
|
||||
.equ TIM3_CCMR2, TIM3_BASE + TIM_CCMR2_OFFSET
|
||||
.equ TIM3_CCER, TIM3_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM3_CNT, TIM3_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM3_PSC, TIM3_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM3_ARR, TIM3_BASE + TIM_ARR_OFFSET
|
||||
|
||||
.equ TIM3_CCR1, TIM3_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM3_CCR2, TIM3_BASE + TIM_CCR2_OFFSET
|
||||
.equ TIM3_CCR3, TIM3_BASE + TIM_CCR3_OFFSET
|
||||
.equ TIM3_CCR4, TIM3_BASE + TIM_CCR4_OFFSET
|
||||
|
||||
.equ TIM3_ECR, TIM3_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM3_TISEL, TIM3_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM3_AF1, TIM3_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM3_AF2, TIM3_BASE + TIM_ECR_OFFSET
|
||||
|
||||
.equ TIM3_DCR, TIM3_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM3_DMAR, TIM3_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Genral Purpose Timer - TIM4 / address space: 0x4000_0800 .. 0x4000_0BFF
|
||||
|
||||
.equ TIM4_BASE, APB1_BASE + 0x800
|
||||
|
||||
.equ TIM4_CR1, TIM4_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM4_CR2, TIM4_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM4_SMCR, TIM4_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM4_DIER, TIM4_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM4_SR, TIM4_BASE + TIM_SR_OFFSET
|
||||
.equ TIM4_EGR, TIM4_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM4_CCMR1, TIM4_BASE + TIM_CCMR1_OFFSET
|
||||
.equ TIM4_CCMR2, TIM4_BASE + TIM_CCMR2_OFFSET
|
||||
.equ TIM4_CCER, TIM4_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM4_CNT, TIM4_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM4_PSC, TIM4_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM4_ARR, TIM4_BASE + TIM_ARR_OFFSET
|
||||
|
||||
.equ TIM4_CCR1, TIM4_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM4_CCR2, TIM4_BASE + TIM_CCR2_OFFSET
|
||||
.equ TIM4_CCR3, TIM4_BASE + TIM_CCR3_OFFSET
|
||||
.equ TIM4_CCR4, TIM4_BASE + TIM_CCR4_OFFSET
|
||||
|
||||
.equ TIM4_ECR, TIM4_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM4_TISEL, TIM4_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM4_AF1, TIM4_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM4_AF2, TIM4_BASE + TIM_ECR_OFFSET
|
||||
|
||||
.equ TIM4_DCR, TIM4_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM4_DMAR, TIM4_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Genral Purpose Timer - TIM5 / address space: 0x4000_0C00 .. 0x4000_0FFF
|
||||
|
||||
.equ TIM5_BASE, APB1_BASE + 0xC00
|
||||
|
||||
.equ TIM5_CR1, TIM5_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM5_CR2, TIM5_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM5_SMCR, TIM5_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM5_DIER, TIM5_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM5_SR, TIM5_BASE + TIM_SR_OFFSET
|
||||
.equ TIM5_EGR, TIM5_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM5_CCMR1, TIM5_BASE + TIM_CCMR1_OFFSET
|
||||
.equ TIM5_CCMR2, TIM5_BASE + TIM_CCMR2_OFFSET
|
||||
.equ TIM5_CCER, TIM5_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM5_CNT, TIM5_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM5_PSC, TIM5_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM5_ARR, TIM5_BASE + TIM_ARR_OFFSET
|
||||
|
||||
.equ TIM5_CCR1, TIM5_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM5_CCR2, TIM5_BASE + TIM_CCR2_OFFSET
|
||||
.equ TIM5_CCR3, TIM5_BASE + TIM_CCR3_OFFSET
|
||||
.equ TIM5_CCR4, TIM5_BASE + TIM_CCR4_OFFSET
|
||||
|
||||
.equ TIM5_ECR, TIM5_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM5_TISEL, TIM5_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM5_AF1, TIM5_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM5_AF2, TIM5_BASE + TIM_ECR_OFFSET
|
||||
|
||||
.equ TIM5_DCR, TIM5_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM5_DMAR, TIM5_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Basic Timer - TIM6 / address space: 0x4000_1000 .. 0x4000_13FF
|
||||
|
||||
.equ TIM6_BASE, APB1_BASE + 0x1000
|
||||
|
||||
.equ TIM6_CR1, TIM6_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM6_CR2, TIM6_BASE + TIM_CR2_OFFSET
|
||||
|
||||
.equ TIM6_DIER, TIM6_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM6_SR, TIM6_BASE + TIM_SR_OFFSET
|
||||
.equ TIM6_EGR, TIM6_BASE + TIM_EGR_OFFSET
|
||||
|
||||
.equ TIM6_CNT, TIM6_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM6_PSC, TIM6_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM6_ARR, TIM6_BASE + TIM_ARR_OFFSET
|
||||
|
||||
#--- Basic Timer - TIM7 / address space: 0x4000_1400 .. 0x4000_17FF
|
||||
|
||||
.equ TIM7_BASE, APB1_BASE + 0x1400
|
||||
|
||||
.equ TIM7_CR1, TIM7_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM7_CR2, TIM7_BASE + TIM_CR2_OFFSET
|
||||
|
||||
.equ TIM7_DIER, TIM7_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM7_SR, TIM7_BASE + TIM_SR_OFFSET
|
||||
.equ TIM7_EGR, TIM7_BASE + TIM_EGR_OFFSET
|
||||
|
||||
.equ TIM7_CNT, TIM7_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM7_PSC, TIM7_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM7_ARR, TIM7_BASE + TIM_ARR_OFFSET
|
||||
|
||||
#--- Advanced Control Timer - TIM1 / address space: 0x4001_2C00 .. 0x4001_2FFF
|
||||
|
||||
.equ TIM1_BASE, APB2_BASE + 0x2C00
|
||||
|
||||
.equ TIM1_CR1, TIM1_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM1_CR2, TIM1_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM1_SMCR, TIM1_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM1_DIER, TIM1_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM1_SR, TIM1_BASE + TIM_SR_OFFSET
|
||||
.equ TIM1_EGR, TIM1_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM1_CCMR1, TIM1_BASE + TIM_CCMR1_OFFSET
|
||||
.equ TIM1_CCMR2, TIM1_BASE + TIM_CCMR2_OFFSET
|
||||
.equ TIM1_CCER, TIM1_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM1_CNT, TIM1_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM1_PSC, TIM1_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM1_ARR, TIM1_BASE + TIM_ARR_OFFSET
|
||||
.equ TIM1_RCR, TIM1_BASE + TIM_RCR_OFFSET
|
||||
.equ TIM1_CCR1, TIM1_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM1_CCR2, TIM1_BASE + TIM_CCR2_OFFSET
|
||||
.equ TIM1_CCR3, TIM1_BASE + TIM_CCR3_OFFSET
|
||||
.equ TIM1_CCR4, TIM1_BASE + TIM_CCR4_OFFSET
|
||||
.equ TIM1_BDTR, TIM1_BASE + TIM_BDTR_OFFSET
|
||||
.equ TIM1_CCR5, TIM1_BASE + TIM_CCR5_OFFSET
|
||||
.equ TIM1_CCR6, TIM1_BASE + TIM_CCR6_OFFSET
|
||||
.equ TIM1_CCMR3, TIM1_BASE + TIM_CCMR3_OFFSET
|
||||
.equ TIM1_DTR2, TIM1_BASE + TIM_DTR2_OFFSET
|
||||
.equ TIM1_ECR, TIM1_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM1_TISEL, TIM1_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM1_AF1, TIM1_BASE + TIM_AF1_OFFSET
|
||||
.equ TIM1_AF2, TIM1_BASE + TIM_AF2_OFFSET
|
||||
|
||||
.equ TIM1_DCR, TIM1_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM1_DMAR, TIM1_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Advanced Control Timer - TIM8 / address space: 0x4001_3400 .. 0x4001_37FF
|
||||
|
||||
.equ TIM8_BASE, APB2_BASE + 0x3400
|
||||
|
||||
.equ TIM8_CR1, TIM8_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM8_CR2, TIM8_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM8_SMCR, TIM8_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM8_DIER, TIM8_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM8_SR, TIM8_BASE + TIM_SR_OFFSET
|
||||
.equ TIM8_EGR, TIM8_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM8_CCMR1, TIM8_BASE + TIM_CCMR1_OFFSET
|
||||
.equ TIM8_CCMR2, TIM8_BASE + TIM_CCMR2_OFFSET
|
||||
.equ TIM8_CCER, TIM8_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM8_CNT, TIM8_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM8_PSC, TIM8_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM8_ARR, TIM8_BASE + TIM_ARR_OFFSET
|
||||
.equ TIM8_RCR, TIM8_BASE + TIM_RCR_OFFSET
|
||||
.equ TIM8_CCR1, TIM8_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM8_CCR2, TIM8_BASE + TIM_CCR2_OFFSET
|
||||
.equ TIM8_CCR3, TIM8_BASE + TIM_CCR3_OFFSET
|
||||
.equ TIM8_CCR4, TIM8_BASE + TIM_CCR4_OFFSET
|
||||
.equ TIM8_BDTR, TIM8_BASE + TIM_BDTR_OFFSET
|
||||
.equ TIM8_CCR5, TIM8_BASE + TIM_CCR5_OFFSET
|
||||
.equ TIM8_CCR6, TIM8_BASE + TIM_CCR6_OFFSET
|
||||
.equ TIM8_CCMR3, TIM8_BASE + TIM_CCMR3_OFFSET
|
||||
.equ TIM8_DTR2, TIM8_BASE + TIM_DTR2_OFFSET
|
||||
.equ TIM8_ECR, TIM8_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM8_TISEL, TIM8_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM8_AF1, TIM8_BASE + TIM_AF1_OFFSET
|
||||
.equ TIM8_AF2, TIM8_BASE + TIM_AF2_OFFSET
|
||||
|
||||
.equ TIM8_DCR, TIM8_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM8_DMAR, TIM8_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Advanced Control Timer - TIM20 / address space: 0x4001_5000 .. 0x4001_53FF
|
||||
|
||||
.equ TIM20_BASE, APB2_BASE + 0x5000
|
||||
|
||||
.equ TIM20_CR1, TIM20_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM20_CR2, TIM20_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM20_SMCR, TIM20_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM20_DIER, TIM20_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM20_SR, TIM20_BASE + TIM_SR_OFFSET
|
||||
.equ TIM20_EGR, TIM20_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM20_CCMR1, TIM20_BASE + TIM_CCMR1_OFFSET
|
||||
.equ TIM20_CCMR2, TIM20_BASE + TIM_CCMR2_OFFSET
|
||||
.equ TIM20_CCER, TIM20_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM20_CNT, TIM20_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM20_PSC, TIM20_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM20_ARR, TIM20_BASE + TIM_ARR_OFFSET
|
||||
.equ TIM20_RCR, TIM20_BASE + TIM_RCR_OFFSET
|
||||
.equ TIM20_CCR1, TIM20_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM20_CCR2, TIM20_BASE + TIM_CCR2_OFFSET
|
||||
.equ TIM20_CCR3, TIM20_BASE + TIM_CCR3_OFFSET
|
||||
.equ TIM20_CCR4, TIM20_BASE + TIM_CCR4_OFFSET
|
||||
.equ TIM20_BDTR, TIM20_BASE + TIM_BDTR_OFFSET
|
||||
.equ TIM20_CCR5, TIM20_BASE + TIM_CCR5_OFFSET
|
||||
.equ TIM20_CCR6, TIM20_BASE + TIM_CCR6_OFFSET
|
||||
.equ TIM20_CCMR3, TIM20_BASE + TIM_CCMR3_OFFSET
|
||||
.equ TIM20_DTR2, TIM20_BASE + TIM_DTR2_OFFSET
|
||||
.equ TIM20_ECR, TIM20_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM20_TISEL, TIM20_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM20_AF1, TIM20_BASE + TIM_AF1_OFFSET
|
||||
.equ TIM20_AF2, TIM20_BASE + TIM_AF2_OFFSET
|
||||
|
||||
.equ TIM20_DCR, TIM20_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM20_DMAR, TIM20_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Genral Purpose Timer - TIM15 / address space: 0x4001_4000 .. 0x4001_43FF
|
||||
|
||||
.equ TIM15_BASE, APB2_BASE + 0x4000
|
||||
|
||||
.equ TIM15_CR1, TIM15_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM15_CR2, TIM15_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM15_SMCR, TIM15_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM15_DIER, TIM15_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM15_SR, TIM15_BASE + TIM_SR_OFFSET
|
||||
.equ TIM15_EGR, TIM15_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM15_CCMR1, TIM15_BASE + TIM_CCMR1_OFFSET
|
||||
|
||||
.equ TIM15_CCER, TIM15_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM15_CNT, TIM15_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM15_PSC, TIM15_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM15_ARR, TIM15_BASE + TIM_ARR_OFFSET
|
||||
.equ TIM15_RCR, TIM15_BASE + TIM_RCR_OFFSET
|
||||
.equ TIM15_CCR1, TIM15_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM15_CCR2, TIM15_BASE + TIM_CCR2_OFFSET
|
||||
|
||||
.equ TIM15_BDTR, TIM15_BASE + TIM_BDTR_OFFSET
|
||||
|
||||
.equ TIM15_DTR2, TIM15_BASE + TIM_DTR2_OFFSET
|
||||
|
||||
.equ TIM15_TISEL, TIM15_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM15_AF1, TIM15_BASE + TIM_AF1_OFFSET
|
||||
.equ TIM15_AF2, TIM15_BASE + TIM_AF2_OFFSET
|
||||
|
||||
.equ TIM15_DCR, TIM15_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM15_DMAR, TIM15_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Genral Purpose Timer - TIM16 / address space: 0x4001_4400 .. 0x4001_47FF
|
||||
|
||||
.equ TIM16_BASE, APB2_BASE + 0x4400
|
||||
|
||||
.equ TIM16_CR1, TIM16_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM16_CR2, TIM16_BASE + TIM_CR2_OFFSET
|
||||
|
||||
.equ TIM16_DIER, TIM16_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM16_SR, TIM16_BASE + TIM_SR_OFFSET
|
||||
.equ TIM16_EGR, TIM16_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM16_CCMR1, TIM16_BASE + TIM_CCMR1_OFFSET
|
||||
|
||||
.equ TIM16_CCER, TIM16_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM16_CNT, TIM16_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM16_PSC, TIM16_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM16_ARR, TIM16_BASE + TIM_ARR_OFFSET
|
||||
.equ TIM16_RCR, TIM16_BASE + TIM_RCR_OFFSET
|
||||
.equ TIM16_CCR1, TIM16_BASE + TIM_CCR1_OFFSET
|
||||
|
||||
.equ TIM16_BDTR, TIM16_BASE + TIM_BDTR_OFFSET
|
||||
|
||||
.equ TIM16_DTR2, TIM16_BASE + TIM_DTR2_OFFSET
|
||||
|
||||
.equ TIM16_TISEL, TIM16_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM16_AF1, TIM16_BASE + TIM_AF1_OFFSET
|
||||
.equ TIM16_AF2, TIM16_BASE + TIM_AF2_OFFSET
|
||||
.equ TIM16_OR1, TIM16_BASE + TIM_OR1_OFFSET
|
||||
|
||||
.equ TIM16_DCR, TIM16_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM16_DMAR, TIM16_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Genral Purpose Timer - TIM17 / address space: 0x4001_4800 .. 0x4001_4BFF
|
||||
|
||||
.equ TIM17_BASE, APB2_BASE + 0x4800
|
||||
|
||||
.equ TIM17_CR1, TIM17_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM17_CR2, TIM17_BASE + TIM_CR2_OFFSET
|
||||
|
||||
.equ TIM17_DIER, TIM17_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM17_SR, TIM17_BASE + TIM_SR_OFFSET
|
||||
.equ TIM17_EGR, TIM17_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM17_CCMR1, TIM17_BASE + TIM_CCMR1_OFFSET
|
||||
|
||||
.equ TIM17_CCER, TIM17_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM17_CNT, TIM17_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM17_PSC, TIM17_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM17_ARR, TIM17_BASE + TIM_ARR_OFFSET
|
||||
.equ TIM17_RCR, TIM17_BASE + TIM_RCR_OFFSET
|
||||
.equ TIM17_CCR1, TIM17_BASE + TIM_CCR1_OFFSET
|
||||
|
||||
.equ TIM17_BDTR, TIM17_BASE + TIM_BDTR_OFFSET
|
||||
|
||||
.equ TIM17_DTR2, TIM17_BASE + TIM_DTR2_OFFSET
|
||||
|
||||
.equ TIM17_TISEL, TIM17_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM17_AF1, TIM17_BASE + TIM_AF1_OFFSET
|
||||
.equ TIM17_AF2, TIM17_BASE + TIM_AF2_OFFSET
|
||||
.equ TIM17_OR1, TIM17_BASE + TIM_OR1_OFFSET
|
||||
|
||||
.equ TIM17_DCR, TIM17_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM17_DMAR, TIM17_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# Reset and Clock Control
|
||||
#
|
||||
# address space: 0x4002_1000 .. 0x4002_13FF
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ RCC_BASE, AHB1_BASE + 0x1000
|
||||
|
||||
.equ RCC_CR, RCC_BASE + 0x00
|
||||
.equ RCC_ICSCR, RCC_BASE + 0x04
|
||||
.equ RCC_CFGR, RCC_BASE + 0x08
|
||||
.equ RCC_PLLCFGR, RCC_BASE + 0x0C
|
||||
|
||||
.equ RCC_CIER, RCC_BASE + 0x18
|
||||
.equ RCC_CIFR, RCC_BASE + 0x1C
|
||||
.equ RCC_CICR, RCC_BASE + 0x20
|
||||
|
||||
.equ RCC_AHB1RSTR, RCC_BASE + 0x28
|
||||
.equ RCC_AHB2RSTR, RCC_BASE + 0x2C
|
||||
.equ RCC_AHB3RSTR, RCC_BASE + 0x30
|
||||
|
||||
.equ RCC_APB1RSTR1, RCC_BASE + 0x38
|
||||
.equ RCC_APB1RSTR2, RCC_BASE + 0x3C
|
||||
.equ RCC_APB2RSTR, RCC_BASE + 0x40
|
||||
|
||||
.equ RCC_AHB1ENR, RCC_BASE + 0x48
|
||||
.equ RCC_AHB2ENR, RCC_BASE + 0x4C
|
||||
.equ RCC_AHB3ENR, RCC_BASE + 0x50
|
||||
|
||||
.equ RCC_APB1ENR1, RCC_BASE + 0x58
|
||||
.equ RCC_APB1ENR2, RCC_BASE + 0x5C
|
||||
.equ RCC_APB2ENR, RCC_BASE + 0x60
|
||||
|
||||
.equ RCC_AHB1SMENR, RCC_BASE + 0x68
|
||||
.equ RCC_AHB2SMENR, RCC_BASE + 0x6C
|
||||
.equ RCC_AHB3SMENR, RCC_BASE + 0x70
|
||||
|
||||
.equ RCC_APB1SMENR1, RCC_BASE + 0x78
|
||||
.equ RCC_APB1SMENR2, RCC_BASE + 0x7C
|
||||
.equ RCC_APB2SMENR, RCC_BASE + 0x80
|
||||
|
||||
.equ RCC_CCIPR, RCC_BASE + 0x88
|
||||
|
||||
.equ RCC_BDCR, RCC_BASE + 0x90
|
||||
.equ RCC_CSR, RCC_BASE + 0x94
|
||||
.equ RCC_CRRCR, RCC_BASE + 0x98
|
||||
.equ RCC_CCIPR2, RCC_BASE + 0x9C
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# GPIO module common configuration
|
||||
#
|
||||
# address space: 0x4800_0000 .. 0x4800_1FFF
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ GPIO_BASE, AHB2_BASE
|
||||
|
||||
.equ GPIO_MODER_OFFSET, 0x00
|
||||
.equ GPIO_OTYPER_OFFSET, 0x04
|
||||
.equ GPIO_OSPEEDR_OFFSET, 0x08
|
||||
.equ GPIO_PUPDR_OFFSET, 0x0C
|
||||
.equ GPIO_IDR_OFFSET, 0x10
|
||||
.equ GPIO_ODR_OFFSET, 0x14
|
||||
.equ GPIO_BSRR_OFFSET, 0x18
|
||||
.equ GPIO_LCKR_OFFSET, 0x1C
|
||||
.equ GPIO_AFRL_OFFSET, 0x20
|
||||
.equ GPIO_AFRH_OFFSET, 0x24
|
||||
.equ GPIO_BRR_OFFSET, 0x28
|
||||
|
||||
#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
|
||||
|
||||
#--- Port A GPIO configuration / address space: 0x4800_0000 .. 0x4800_03FF
|
||||
|
||||
.equ GPIOA_BASE, GPIO_BASE
|
||||
|
||||
.equ GPIOA_MODER, GPIOA_BASE + GPIO_MODER_OFFSET
|
||||
.equ GPIOA_OTYPER, GPIOA_BASE + GPIO_OTYPER_OFFSET
|
||||
.equ GPIOA_OSPEEDR, GPIOA_BASE + GPIO_OSPEEDR_OFFSET
|
||||
.equ GPIOA_PUPDR, GPIOA_BASE + GPIO_PUPDR_OFFSET
|
||||
.equ GPIOA_IDR, GPIOA_BASE + GPIO_IDR_OFFSET
|
||||
.equ GPIOA_ODR, GPIOA_BASE + GPIO_ODR_OFFSET
|
||||
.equ GPIOA_BSRR, GPIOA_BASE + GPIO_BSRR_OFFSET
|
||||
.equ GPIOA_LCKR, GPIOA_BASE + GPIO_LCKR_OFFSET
|
||||
.equ GPIOA_AFRL, GPIOA_BASE + GPIO_AFRL_OFFSET
|
||||
.equ GPIOA_AFRH, GPIOA_BASE + GPIO_AFRH_OFFSET
|
||||
.equ GPIOA_BRR, GPIOA_BASE + GPIO_BRR_OFFSET
|
||||
|
||||
#--- Port B GPIO configuration / address space: 0x4800_0400 .. 0x4800_07FF
|
||||
|
||||
.equ GPIOB_BASE, GPIO_BASE + 0x400
|
||||
|
||||
.equ GPIOB_MODER, GPIOB_BASE + GPIO_MODER_OFFSET
|
||||
.equ GPIOB_OTYPER, GPIOB_BASE + GPIO_OTYPER_OFFSET
|
||||
.equ GPIOB_OSPEEDR, GPIOB_BASE + GPIO_OSPEEDR_OFFSET
|
||||
.equ GPIOB_PUPDR, GPIOB_BASE + GPIO_PUPDR_OFFSET
|
||||
.equ GPIOB_IDR, GPIOB_BASE + GPIO_IDR_OFFSET
|
||||
.equ GPIOB_ODR, GPIOB_BASE + GPIO_ODR_OFFSET
|
||||
.equ GPIOB_BSRR, GPIOB_BASE + GPIO_BSRR_OFFSET
|
||||
.equ GPIOB_LCKR, GPIOB_BASE + GPIO_LCKR_OFFSET
|
||||
.equ GPIOB_AFRL, GPIOB_BASE + GPIO_AFRL_OFFSET
|
||||
.equ GPIOB_AFRH, GPIOB_BASE + GPIO_AFRH_OFFSET
|
||||
.equ GPIOB_BRR, GPIOB_BASE + GPIO_BRR_OFFSET
|
||||
|
||||
#--- Port C GPIO configuration / address space: 0x4800_0800 .. 0x4800_0BFF
|
||||
|
||||
.equ GPIOC_BASE, GPIO_BASE + 0x800
|
||||
|
||||
.equ GPIOC_MODER, GPIOC_BASE + GPIO_MODER_OFFSET
|
||||
.equ GPIOC_OTYPER, GPIOC_BASE + GPIO_OTYPER_OFFSET
|
||||
.equ GPIOC_OSPEEDR, GPIOC_BASE + GPIO_OSPEEDR_OFFSET
|
||||
.equ GPIOC_PUPDR, GPIOC_BASE + GPIO_PUPDR_OFFSET
|
||||
.equ GPIOC_IDR, GPIOC_BASE + GPIO_IDR_OFFSET
|
||||
.equ GPIOC_ODR, GPIOC_BASE + GPIO_ODR_OFFSET
|
||||
.equ GPIOC_BSRR, GPIOC_BASE + GPIO_BSRR_OFFSET
|
||||
.equ GPIOC_LCKR, GPIOC_BASE + GPIO_LCKR_OFFSET
|
||||
.equ GPIOC_AFRL, GPIOC_BASE + GPIO_AFRL_OFFSET
|
||||
.equ GPIOC_AFRH, GPIOC_BASE + GPIO_AFRH_OFFSET
|
||||
.equ GPIOC_BRR, GPIOC_BASE + GPIO_BRR_OFFSET
|
||||
|
||||
#--- Port D GPIO configuration / address space: 0x4800_0C00 .. 0x4800_0FFF
|
||||
|
||||
.equ GPIOD_BASE, GPIO_BASE + 0xC00
|
||||
|
||||
.equ GPIOD_MODER, GPIOD_BASE + GPIO_MODER_OFFSET
|
||||
.equ GPIOD_OTYPER, GPIOD_BASE + GPIO_OTYPER_OFFSET
|
||||
.equ GPIOD_OSPEEDR, GPIOD_BASE + GPIO_OSPEEDR_OFFSET
|
||||
.equ GPIOD_PUPDR, GPIOD_BASE + GPIO_PUPDR_OFFSET
|
||||
.equ GPIOD_IDR, GPIOD_BASE + GPIO_IDR_OFFSET
|
||||
.equ GPIOD_ODR, GPIOD_BASE + GPIO_ODR_OFFSET
|
||||
.equ GPIOD_BSRR, GPIOD_BASE + GPIO_BSRR_OFFSET
|
||||
.equ GPIOD_LCKR, GPIOD_BASE + GPIO_LCKR_OFFSET
|
||||
.equ GPIOD_AFRL, GPIOD_BASE + GPIO_AFRL_OFFSET
|
||||
.equ GPIOD_AFRH, GPIOD_BASE + GPIO_AFRH_OFFSET
|
||||
.equ GPIOD_BRR, GPIOD_BASE + GPIO_BRR_OFFSET
|
||||
|
||||
#--- Port E GPIO configuration / address space: 0x4800_1000 .. 0x4800_13FF
|
||||
|
||||
.equ GPIOE_BASE, GPIO_BASE + 0x1000
|
||||
|
||||
.equ GPIOE_MODER, GPIOE_BASE + GPIO_MODER_OFFSET
|
||||
.equ GPIOE_OTYPER, GPIOE_BASE + GPIO_OTYPER_OFFSET
|
||||
.equ GPIOE_OSPEEDR, GPIOE_BASE + GPIO_OSPEEDR_OFFSET
|
||||
.equ GPIOE_PUPDR, GPIOE_BASE + GPIO_PUPDR_OFFSET
|
||||
.equ GPIOE_IDR, GPIOE_BASE + GPIO_IDR_OFFSET
|
||||
.equ GPIOE_ODR, GPIOE_BASE + GPIO_ODR_OFFSET
|
||||
.equ GPIOE_BSRR, GPIOE_BASE + GPIO_BSRR_OFFSET
|
||||
.equ GPIOE_LCKR, GPIOE_BASE + GPIO_LCKR_OFFSET
|
||||
.equ GPIOE_AFRL, GPIOE_BASE + GPIO_AFRL_OFFSET
|
||||
.equ GPIOE_AFRH, GPIOE_BASE + GPIO_AFRH_OFFSET
|
||||
.equ GPIOE_BRR, GPIOE_BASE + GPIO_BRR_OFFSET
|
||||
|
||||
#--- Port F GPIO configuration / address space: 0x4800_1400 .. 0x4800_17FF
|
||||
|
||||
.equ GPIOF_BASE, GPIO_BASE + 0x1400
|
||||
|
||||
.equ GPIOF_MODER, GPIOF_BASE + GPIO_MODER_OFFSET
|
||||
.equ GPIOF_OTYPER, GPIOF_BASE + GPIO_OTYPER_OFFSET
|
||||
.equ GPIOF_OSPEEDR, GPIOF_BASE + GPIO_OSPEEDR_OFFSET
|
||||
.equ GPIOF_PUPDR, GPIOF_BASE + GPIO_PUPDR_OFFSET
|
||||
.equ GPIOF_IDR, GPIOF_BASE + GPIO_IDR_OFFSET
|
||||
.equ GPIOF_ODR, GPIOF_BASE + GPIO_ODR_OFFSET
|
||||
.equ GPIOF_BSRR, GPIOF_BASE + GPIO_BSRR_OFFSET
|
||||
.equ GPIOF_LCKR, GPIOF_BASE + GPIO_LCKR_OFFSET
|
||||
.equ GPIOF_AFRL, GPIOF_BASE + GPIO_AFRL_OFFSET
|
||||
.equ GPIOF_AFRH, GPIOF_BASE + GPIO_AFRH_OFFSET
|
||||
.equ GPIOF_BRR, GPIOF_BASE + GPIO_BRR_OFFSET
|
||||
|
||||
#--- Port G GPIO configuration / address space: 0x4800_1800 .. 0x4800_1BFF
|
||||
|
||||
.equ GPIOG_BASE, GPIO_BASE + 0x1800
|
||||
|
||||
.equ GPIOG_MODER, GPIOG_BASE + GPIO_MODER_OFFSET
|
||||
.equ GPIOG_OTYPER, GPIOG_BASE + GPIO_OTYPER_OFFSET
|
||||
.equ GPIOG_OSPEEDR, GPIOG_BASE + GPIO_OSPEEDR_OFFSET
|
||||
.equ GPIOG_PUPDR, GPIOG_BASE + GPIO_PUPDR_OFFSET
|
||||
.equ GPIOG_IDR, GPIOG_BASE + GPIO_IDR_OFFSET
|
||||
.equ GPIOG_ODR, GPIOG_BASE + GPIO_ODR_OFFSET
|
||||
.equ GPIOG_BSRR, GPIOG_BASE + GPIO_BSRR_OFFSET
|
||||
.equ GPIOG_LCKR, GPIOG_BASE + GPIO_LCKR_OFFSET
|
||||
.equ GPIOG_AFRL, GPIOG_BASE + GPIO_AFRL_OFFSET
|
||||
.equ GPIOG_AFRH, GPIOG_BASE + GPIO_AFRH_OFFSET
|
||||
.equ GPIOG_BRR, GPIOG_BASE + GPIO_BRR_OFFSET
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# System Control Space
|
||||
#
|
||||
# address space: 0xE000_E000 .. 0xE000_EFFF
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ SCS_BASE, PPB_BASE + 0xE000
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# System Timer (SysTick)
|
||||
#
|
||||
# address space: 0xE000_E010 .. 0xE000_E01F
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ STK_BASE, SCS_BASE + 10 // 0xE000_E010
|
||||
|
||||
.equ STK_CTRL, SCS_BASE + 0x00
|
||||
.equ STK_LOAD, SCS_BASE + 0x04
|
||||
.equ STK_VAL, SCS_BASE + 0x08
|
||||
.equ STK_CALIB, SCS_BASE + 0x0C
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# Nested Vector Interrupt Controller
|
||||
#
|
||||
# address space: 0xE000_E100 .. 0xE000_E4EF
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ NVIC_BASE, SCS_BASE + 0x100 // 0xE000_E100
|
||||
|
||||
.equ NVIC_ISER0, NVIC_BASE + 0x00
|
||||
.equ NVIC_ISER1, NVIC_BASE + 0x04
|
||||
.equ NVIC_ISER2, NVIC_BASE + 0x08
|
||||
.equ NVIC_ISER3, NVIC_BASE + 0x0C
|
||||
|
||||
.equ NVIC_ICER0, NVIC_BASE + 0x80
|
||||
.equ NVIC_ICER1, NVIC_BASE + 0x84
|
||||
.equ NVIC_ICER2, NVIC_BASE + 0x88
|
||||
.equ NVIC_ICER3, NVIC_BASE + 0x8C
|
||||
|
||||
.equ NVIC_ISPR0, NVIC_BASE + 0x100
|
||||
.equ NVIC_ISPR1, NVIC_BASE + 0x104
|
||||
.equ NVIC_ISPR2, NVIC_BASE + 0x108
|
||||
.equ NVIC_ISPR3, NVIC_BASE + 0x10C
|
||||
|
||||
.equ NVIC_ICPR0, NVIC_BASE + 0x180
|
||||
.equ NVIC_ICPR1, NVIC_BASE + 0x184
|
||||
.equ NVIC_ICPR2, NVIC_BASE + 0x188
|
||||
.equ NVIC_ICPR3, NVIC_BASE + 0x18C
|
||||
|
||||
.equ NVIC_IABR0, NVIC_BASE + 0x200
|
||||
.equ NVIC_IABR1, NVIC_BASE + 0x204
|
||||
.equ NVIC_IABR2, NVIC_BASE + 0x208
|
||||
.equ NVIC_IABR3, NVIC_BASE + 0x20C
|
||||
|
||||
.equ NVIC_IPR0, NVIC_BASE + 0x300
|
||||
.equ NVIC_IPR1, NVIC_BASE + 0x304
|
||||
.equ NVIC_IPR2, NVIC_BASE + 0x308
|
||||
.equ NVIC_IPR3, NVIC_BASE + 0x30C
|
||||
.equ NVIC_IPR4, NVIC_BASE + 0x310
|
||||
.equ NVIC_IPR5, NVIC_BASE + 0x314
|
||||
.equ NVIC_IPR6, NVIC_BASE + 0x318
|
||||
.equ NVIC_IPR7, NVIC_BASE + 0x31C
|
||||
.equ NVIC_IPR8, NVIC_BASE + 0x320
|
||||
.equ NVIC_IPR9, NVIC_BASE + 0x324
|
||||
.equ NVIC_IPR10, NVIC_BASE + 0x328
|
||||
.equ NVIC_IPR11, NVIC_BASE + 0x32C
|
||||
.equ NVIC_IPR12, NVIC_BASE + 0x330
|
||||
.equ NVIC_IPR13, NVIC_BASE + 0x334
|
||||
.equ NVIC_IPR14, NVIC_BASE + 0x338
|
||||
.equ NVIC_IPR15, NVIC_BASE + 0x33C
|
||||
.equ NVIC_IPR16, NVIC_BASE + 0x340
|
||||
.equ NVIC_IPR17, NVIC_BASE + 0x344
|
||||
.equ NVIC_IPR18, NVIC_BASE + 0x348
|
||||
.equ NVIC_IPR19, NVIC_BASE + 0x34C
|
||||
.equ NVIC_IPR20, NVIC_BASE + 0x350
|
||||
.equ NVIC_IPR21, NVIC_BASE + 0x354
|
||||
.equ NVIC_IPR22, NVIC_BASE + 0x358
|
||||
.equ NVIC_IPR23, NVIC_BASE + 0x35C
|
||||
.equ NVIC_IPR24, NVIC_BASE + 0x360
|
||||
.equ NVIC_IPR25, NVIC_BASE + 0x364
|
||||
|
||||
.equ STIR, NVIC_BASE + 0xE00
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# MCU Debug Component
|
||||
#
|
||||
# address space: 0xE004_2000 .. 0xE004_2013
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ DBGMCU_BASE, PPB_BASE + 0x42000
|
||||
|
||||
.equ DBGMCU_IDCODE, DBGMCU_BASE + 0x00
|
||||
.equ DBGMCU_CR, DBGMCU_BASE + 0x04
|
||||
.equ DBGMCU_APB1FZR1, DBGMCU_BASE + 0x08
|
||||
.equ DBGMCU_APB1FZR2, DBGMCU_BASE + 0x0C
|
||||
.equ DBGMCU_APB2DZR, DBGMCU_BASE + 0x10
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* sketch.c
|
||||
*
|
||||
* Created on: Mar 18, 2026
|
||||
* Author: tobii
|
||||
*/
|
||||
int reihenfolge[6] = {0, 1, 2, 3, 2, 1};
|
||||
|
||||
int main(){
|
||||
while(1){
|
||||
while(/*schalter nicht gedrückt*/){}
|
||||
delay(10);
|
||||
while(/*schalter losgelassen*/){}
|
||||
delay(150);
|
||||
|
||||
int aktiv = 1;
|
||||
while(aktiv){
|
||||
for(int i; i < reihenfolge.length - 1 && aktiv = 1; i ++){
|
||||
//alle LED einschalten
|
||||
if(i = 0){/*alles bis auf LED0 auschalten*/}
|
||||
if(i = 1){/*..*/}
|
||||
//...
|
||||
for(int zähler = 0; zähler < 333 && aktiv == 1; zähler++){
|
||||
if(/*schalter gerückt*/){
|
||||
aktiv = 0;
|
||||
break;
|
||||
}
|
||||
else{
|
||||
delay(1);
|
||||
}
|
||||
}
|
||||
while(/*Taster gedrückt*/){}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
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+4
@@ -0,0 +1,4 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<session version="1.0">
|
||||
<refactoring comment="Delete resource 'task2/task2_tobi.s'" deleteContents="false" description="Delete resource 'task2/task2_tobi.s'" element1="/task2/task2_tobi.s" flags="7" id="org.eclipse.ltk.core.refactoring.delete.resources" resources="1" stamp="1774360637158"/>
|
||||
</session>
|
||||
+1
@@ -0,0 +1 @@
|
||||
1774360637158 Delete resource 'task2/task2_tobi.s'
|
||||
@@ -1,15 +1,15 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<section name="Workbench">
|
||||
<section name="RefactoringWizard.preview">
|
||||
<item key="width" value="600"/>
|
||||
<item key="height" value="400"/>
|
||||
</section>
|
||||
<section name="ShowRefactoringHistoryWizard">
|
||||
<item key="org.eclipse.ltk.ui.refactoring.sortRefactorings" value="true"/>
|
||||
</section>
|
||||
<section name="RefactoringStatusDialog">
|
||||
<item key="DIALOG_WIDTH" value="816"/>
|
||||
<item key="DIALOG_HEIGHT" value="490"/>
|
||||
<item key="DIALOG_FONT_NAME" value="1|Segoe UI|9.0|0|WINDOWS|1|-12|0|0|0|400|0|0|0|1|0|0|0|0|Segoe UI"/>
|
||||
</section>
|
||||
</section>
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<section name="Workbench">
|
||||
<section name="RefactoringWizard.preview">
|
||||
<item key="width" value="600"/>
|
||||
<item key="height" value="400"/>
|
||||
</section>
|
||||
<section name="ShowRefactoringHistoryWizard">
|
||||
<item key="org.eclipse.ltk.ui.refactoring.sortRefactorings" value="true"/>
|
||||
</section>
|
||||
<section name="RefactoringStatusDialog">
|
||||
<item key="DIALOG_WIDTH" value="816"/>
|
||||
<item key="DIALOG_HEIGHT" value="490"/>
|
||||
<item key="DIALOG_FONT_NAME" value="1|Segoe UI|9.0|0|WINDOWS|1|-12|0|0|0|400|0|0|0|1|0|0|0|0|Segoe UI"/>
|
||||
</section>
|
||||
</section>
|
||||
|
||||
@@ -17,7 +17,7 @@
|
||||
<section name="CleanDialogSettings">
|
||||
<item key="BUILD_NOW" value="false"/>
|
||||
<item key="BUILD_ALL" value="true"/>
|
||||
<item key="TOGGLE_SELECTED" value="false"/>
|
||||
<item key="TOGGLE_SELECTED" value="true"/>
|
||||
<item key="DIALOG_WIDTH" value="731"/>
|
||||
<item key="DIALOG_HEIGHT" value="569"/>
|
||||
<item key="DIALOG_FONT_NAME" value="1|Noto Sans|10.0|0|GTK|1|"/>
|
||||
|
||||
@@ -1,3 +1,3 @@
|
||||
#Tue Mar 24 14:11:27 CET 2026
|
||||
#Tue Mar 31 13:41:52 CEST 2026
|
||||
org.eclipse.core.runtime=2
|
||||
org.eclipse.platform=4.30.0.v20231201-0110
|
||||
|
||||
Reference in New Issue
Block a user