sachen für task1 und task2
This commit is contained in:
parent
b19c7f6b51
commit
8f074b6f72
227
.metadata/.log
227
.metadata/.log
@ -9328,3 +9328,230 @@ Command-line arguments: -os linux -ws gtk -arch x86_64
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!ENTRY com.st.stm32cube.ide.mcu.debug 4 0 2026-03-24 14:18:01.013
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!MESSAGE Existing sessions are:
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!SESSION 2026-03-24 14:21:01.018 -----------------------------------------------
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eclipse.buildId=Version 1.16.0
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java.version=17.0.11
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java.vendor=Eclipse Adoptium
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BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=de_DE
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Command-line arguments: -os linux -ws gtk -arch x86_64
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!ENTRY com.st.stm32cube.ide.mcu.informationcenter 4 4 2026-03-24 14:21:05.958
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!MESSAGE CubeMX plugin appears to be active, Log4j initialization might be too late.
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!ENTRY com.st.stm32cube.ide.mcu.informationcenter 1 1 2026-03-24 14:21:05.959
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!MESSAGE Log4j2 initialized with config file /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/.metadata/.log4j2.xml
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!ENTRY com.st.stm32cube.ide.mcu.ide 1 1 2026-03-24 14:21:11.141
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!MESSAGE Started RMI Server, listening on port 41337
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!SESSION 2026-03-31 11:20:25.522 -----------------------------------------------
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eclipse.buildId=Version 1.16.0
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java.version=17.0.11
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java.vendor=Eclipse Adoptium
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BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=de_DE
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Command-line arguments: -os linux -ws gtk -arch x86_64
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!ENTRY com.st.stm32cube.ide.mcu.informationcenter 4 4 2026-03-31 11:20:29.815
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!MESSAGE CubeMX plugin appears to be active, Log4j initialization might be too late.
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!ENTRY com.st.stm32cube.ide.mcu.informationcenter 1 1 2026-03-31 11:20:29.816
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!MESSAGE Log4j2 initialized with config file /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/.metadata/.log4j2.xml
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!ENTRY com.st.stm32cube.ide.mcu.ide 1 1 2026-03-31 11:20:33.229
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!MESSAGE Started RMI Server, listening on port 41337
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!SESSION 2026-03-31 13:41:50.718 -----------------------------------------------
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eclipse.buildId=Version 1.16.0
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java.version=17.0.11
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java.vendor=Eclipse Adoptium
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BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=de_DE
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Command-line arguments: -os linux -ws gtk -arch x86_64
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!ENTRY org.eclipse.core.resources 2 10035 2026-03-31 13:41:52.576
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!MESSAGE The workspace exited with unsaved changes in the previous session; refreshing workspace to recover changes.
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!ENTRY com.st.stm32cube.ide.mcu.informationcenter 4 4 2026-03-31 13:41:55.091
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!MESSAGE CubeMX plugin appears to be active, Log4j initialization might be too late.
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!ENTRY com.st.stm32cube.ide.mcu.informationcenter 1 1 2026-03-31 13:41:55.092
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!MESSAGE Log4j2 initialized with config file /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/.metadata/.log4j2.xml
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!ENTRY com.st.stm32cube.ide.mcu.ide 1 1 2026-03-31 13:41:58.079
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!MESSAGE Started RMI Server, listening on port 41337
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!ENTRY org.eclipse.equinox.p2.transport.ecf 4 1002 2026-03-31 13:42:20.010
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!MESSAGE Unable to connect to repository https://sw-center.st.com/stm32cubeide/openstlinux/updatesite1/compositeContent.xml
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!STACK 0
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java.net.ConnectException
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at java.net.http/jdk.internal.net.http.common.Utils.toConnectException(Utils.java:1055)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:198)
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at java.net.http/jdk.internal.net.http.AsyncSSLConnection.connectAsync(AsyncSSLConnection.java:56)
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at java.net.http/jdk.internal.net.http.Http2Connection.createAsync(Http2Connection.java:378)
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at java.net.http/jdk.internal.net.http.Http2ClientImpl.getConnectionFor(Http2ClientImpl.java:126)
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at java.net.http/jdk.internal.net.http.ExchangeImpl.get(ExchangeImpl.java:93)
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at java.net.http/jdk.internal.net.http.Exchange.establishExchange(Exchange.java:343)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl0(Exchange.java:475)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl(Exchange.java:380)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsync(Exchange.java:372)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:408)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsyncImpl$7(MultiExchange.java:449)
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at java.base/java.util.concurrent.CompletableFuture.uniHandle(CompletableFuture.java:934)
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at java.base/java.util.concurrent.CompletableFuture.uniHandleStage(CompletableFuture.java:950)
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at java.base/java.util.concurrent.CompletableFuture.handle(CompletableFuture.java:2340)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:439)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsync0$2(MultiExchange.java:341)
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at java.base/java.util.concurrent.CompletableFuture$UniCompose.tryFire(CompletableFuture.java:1150)
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at java.base/java.util.concurrent.CompletableFuture.postComplete(CompletableFuture.java:510)
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at java.base/java.util.concurrent.CompletableFuture$AsyncSupply.run(CompletableFuture.java:1773)
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at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1136)
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at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:635)
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at java.base/java.lang.Thread.run(Thread.java:840)
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Caused by: java.nio.channels.UnresolvedAddressException
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:149)
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:157)
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at java.base/sun.nio.ch.SocketChannelImpl.checkRemote(SocketChannelImpl.java:816)
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at java.base/sun.nio.ch.SocketChannelImpl.connect(SocketChannelImpl.java:839)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.lambda$connectAsync$0(PlainHttpConnection.java:183)
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at java.base/java.security.AccessController.doPrivileged(AccessController.java:569)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:185)
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... 21 more
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!ENTRY org.eclipse.equinox.p2.transport.ecf 4 1002 2026-03-31 13:42:20.015
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!MESSAGE Unable to connect to repository https://sw-center.st.com/stm32cubeide/updatesite1/compositeContent.xml
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!STACK 0
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java.net.ConnectException
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at java.net.http/jdk.internal.net.http.common.Utils.toConnectException(Utils.java:1055)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:198)
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at java.net.http/jdk.internal.net.http.AsyncSSLConnection.connectAsync(AsyncSSLConnection.java:56)
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at java.net.http/jdk.internal.net.http.Http2Connection.createAsync(Http2Connection.java:378)
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at java.net.http/jdk.internal.net.http.Http2ClientImpl.getConnectionFor(Http2ClientImpl.java:126)
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at java.net.http/jdk.internal.net.http.ExchangeImpl.get(ExchangeImpl.java:93)
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at java.net.http/jdk.internal.net.http.Exchange.establishExchange(Exchange.java:343)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl0(Exchange.java:475)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl(Exchange.java:380)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsync(Exchange.java:372)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:408)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsyncImpl$7(MultiExchange.java:449)
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at java.base/java.util.concurrent.CompletableFuture.uniHandle(CompletableFuture.java:934)
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at java.base/java.util.concurrent.CompletableFuture.uniHandleStage(CompletableFuture.java:950)
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at java.base/java.util.concurrent.CompletableFuture.handle(CompletableFuture.java:2340)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:439)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsync0$2(MultiExchange.java:341)
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at java.base/java.util.concurrent.CompletableFuture$UniCompose.tryFire(CompletableFuture.java:1150)
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at java.base/java.util.concurrent.CompletableFuture.postComplete(CompletableFuture.java:510)
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at java.base/java.util.concurrent.CompletableFuture$AsyncSupply.run(CompletableFuture.java:1773)
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at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1136)
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at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:635)
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at java.base/java.lang.Thread.run(Thread.java:840)
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Caused by: java.nio.channels.UnresolvedAddressException
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:149)
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:157)
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at java.base/sun.nio.ch.SocketChannelImpl.checkRemote(SocketChannelImpl.java:816)
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at java.base/sun.nio.ch.SocketChannelImpl.connect(SocketChannelImpl.java:839)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.lambda$connectAsync$0(PlainHttpConnection.java:183)
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at java.base/java.security.AccessController.doPrivileged(AccessController.java:569)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:185)
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... 21 more
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!ENTRY org.eclipse.equinox.p2.transport.ecf 4 1002 2026-03-31 13:42:20.022
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!MESSAGE Unable to connect to repository https://download.eclipse.org/tools/cdt/releases/latest/compositeContent.xml
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!STACK 0
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java.net.ConnectException
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at java.net.http/jdk.internal.net.http.common.Utils.toConnectException(Utils.java:1055)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:198)
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at java.net.http/jdk.internal.net.http.AsyncSSLConnection.connectAsync(AsyncSSLConnection.java:56)
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at java.net.http/jdk.internal.net.http.Http2Connection.createAsync(Http2Connection.java:378)
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at java.net.http/jdk.internal.net.http.Http2ClientImpl.getConnectionFor(Http2ClientImpl.java:126)
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at java.net.http/jdk.internal.net.http.ExchangeImpl.get(ExchangeImpl.java:93)
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at java.net.http/jdk.internal.net.http.Exchange.establishExchange(Exchange.java:343)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl0(Exchange.java:475)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl(Exchange.java:380)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsync(Exchange.java:372)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:408)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsyncImpl$7(MultiExchange.java:449)
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at java.base/java.util.concurrent.CompletableFuture.uniHandle(CompletableFuture.java:934)
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at java.base/java.util.concurrent.CompletableFuture.uniHandleStage(CompletableFuture.java:950)
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at java.base/java.util.concurrent.CompletableFuture.handle(CompletableFuture.java:2340)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:439)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsync0$2(MultiExchange.java:341)
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at java.base/java.util.concurrent.CompletableFuture$UniCompose.tryFire(CompletableFuture.java:1150)
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at java.base/java.util.concurrent.CompletableFuture.postComplete(CompletableFuture.java:510)
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at java.base/java.util.concurrent.CompletableFuture$AsyncSupply.run(CompletableFuture.java:1773)
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at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1136)
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at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:635)
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at java.base/java.lang.Thread.run(Thread.java:840)
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Caused by: java.nio.channels.UnresolvedAddressException
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:149)
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:157)
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at java.base/sun.nio.ch.SocketChannelImpl.checkRemote(SocketChannelImpl.java:816)
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at java.base/sun.nio.ch.SocketChannelImpl.connect(SocketChannelImpl.java:839)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.lambda$connectAsync$0(PlainHttpConnection.java:183)
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at java.base/java.security.AccessController.doPrivileged(AccessController.java:569)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:185)
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... 21 more
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!ENTRY org.eclipse.equinox.p2.transport.ecf 4 1002 2026-03-31 13:42:20.028
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!MESSAGE Unable to connect to repository https://download.eclipse.org/releases/2023-12/compositeContent.xml
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!STACK 0
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java.net.ConnectException
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at java.net.http/jdk.internal.net.http.common.Utils.toConnectException(Utils.java:1055)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:198)
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at java.net.http/jdk.internal.net.http.AsyncSSLConnection.connectAsync(AsyncSSLConnection.java:56)
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at java.net.http/jdk.internal.net.http.Http2Connection.createAsync(Http2Connection.java:378)
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at java.net.http/jdk.internal.net.http.Http2ClientImpl.getConnectionFor(Http2ClientImpl.java:126)
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at java.net.http/jdk.internal.net.http.ExchangeImpl.get(ExchangeImpl.java:93)
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at java.net.http/jdk.internal.net.http.Exchange.establishExchange(Exchange.java:343)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl0(Exchange.java:475)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsyncImpl(Exchange.java:380)
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at java.net.http/jdk.internal.net.http.Exchange.responseAsync(Exchange.java:372)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:408)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsyncImpl$7(MultiExchange.java:449)
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at java.base/java.util.concurrent.CompletableFuture.uniHandle(CompletableFuture.java:934)
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at java.base/java.util.concurrent.CompletableFuture.uniHandleStage(CompletableFuture.java:950)
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at java.base/java.util.concurrent.CompletableFuture.handle(CompletableFuture.java:2340)
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at java.net.http/jdk.internal.net.http.MultiExchange.responseAsyncImpl(MultiExchange.java:439)
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at java.net.http/jdk.internal.net.http.MultiExchange.lambda$responseAsync0$2(MultiExchange.java:341)
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at java.base/java.util.concurrent.CompletableFuture$UniCompose.tryFire(CompletableFuture.java:1150)
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at java.base/java.util.concurrent.CompletableFuture.postComplete(CompletableFuture.java:510)
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at java.base/java.util.concurrent.CompletableFuture$AsyncSupply.run(CompletableFuture.java:1773)
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at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1136)
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at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:635)
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at java.base/java.lang.Thread.run(Thread.java:840)
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Caused by: java.nio.channels.UnresolvedAddressException
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:149)
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at java.base/sun.nio.ch.Net.checkAddress(Net.java:157)
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at java.base/sun.nio.ch.SocketChannelImpl.checkRemote(SocketChannelImpl.java:816)
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at java.base/sun.nio.ch.SocketChannelImpl.connect(SocketChannelImpl.java:839)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.lambda$connectAsync$0(PlainHttpConnection.java:183)
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at java.base/java.security.AccessController.doPrivileged(AccessController.java:569)
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at java.net.http/jdk.internal.net.http.PlainHttpConnection.connectAsync(PlainHttpConnection.java:185)
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... 21 more
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!ENTRY org.eclipse.cdt.dsf.gdb 4 104 2026-03-31 13:56:39.797
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!MESSAGE Program file does not exist
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!STACK 0
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java.io.FileNotFoundException: /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/task1/Debug/task1.elf not found
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at org.eclipse.cdt.dsf.gdb.launching.LaunchUtils.verifyProgramPath(LaunchUtils.java:130)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.checkBinaryDetails(GdbLaunchDelegate.java:330)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launchDebugSession(GdbLaunchDelegate.java:152)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launchDebugger(GdbLaunchDelegate.java:109)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launch(GdbLaunchDelegate.java:97)
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at com.st.stm32cube.ide.mcu.debug.launch.DSFDelegate.launch(DSFDelegate.java:334)
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at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:805)
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at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:716)
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at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1040)
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at org.eclipse.debug.internal.ui.DebugUIPlugin$1.run(DebugUIPlugin.java:1243)
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at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63)
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!SUBENTRY 1 org.eclipse.cdt.dsf.gdb 4 104 2026-03-31 13:56:39.797
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!MESSAGE /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/task1/Debug/task1.elf not found
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!STACK 0
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java.io.FileNotFoundException: /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/task1/Debug/task1.elf not found
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at org.eclipse.cdt.dsf.gdb.launching.LaunchUtils.verifyProgramPath(LaunchUtils.java:130)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.checkBinaryDetails(GdbLaunchDelegate.java:330)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launchDebugSession(GdbLaunchDelegate.java:152)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launchDebugger(GdbLaunchDelegate.java:109)
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at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launch(GdbLaunchDelegate.java:97)
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at com.st.stm32cube.ide.mcu.debug.launch.DSFDelegate.launch(DSFDelegate.java:334)
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at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:805)
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at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:716)
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at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1040)
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at org.eclipse.debug.internal.ui.DebugUIPlugin$1.run(DebugUIPlugin.java:1243)
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at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63)
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@ -52,3 +52,5 @@
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*** SESSION März 13, 2026 10:49:11.272 -----------------------------------------
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*** SESSION März 16, 2026 12:55:55.445 -----------------------------------------
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*** SESSION März 24, 2026 14:01:49.132 -----------------------------------------
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*** SESSION März 24, 2026 14:11:29.704 -----------------------------------------
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*** SESSION März 24, 2026 14:21:04.465 -----------------------------------------
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Binary file not shown.
@ -553,3 +553,93 @@ Target all ready
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14:19:07 **** Incremental Build of configuration Debug for project task2 ****
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make -j12 all
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Target all ready
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14:56:35 **** Incremental Build of configuration Debug for project task2 ****
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make -j12 all
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Target all ready
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14:57:35 **** Clean-only build of configuration Debug for project task2 ****
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make -j12 clean
|
||||
14:57:51 **** Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
|
||||
arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
|
||||
arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
|
||||
arm-none-eabi-size task2.elf
|
||||
text data bss dec hex filename
|
||||
648 0 0 648 288 task2.elf
|
||||
Target all ready
|
||||
14:58:02 **** Incremental Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
Target all ready
|
||||
14:58:10 **** Incremental Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
Target all ready
|
||||
13:53:05 **** Incremental Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
|
||||
task2.s: Assembler messages:
|
||||
task2.s:346: Error: junk at end of line, first unrecognized character is `h'
|
||||
make: *** [makefile:74: task2.o] Error 1
|
||||
"make -j12 all" terminated with exit code 2. Build might be incomplete.
|
||||
13:53:51 **** Incremental Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
|
||||
arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
|
||||
arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
|
||||
arm-none-eabi-size task2.elf
|
||||
text data bss dec hex filename
|
||||
532 0 0 532 214 task2.elf
|
||||
Target all ready
|
||||
13:56:03 **** Build of configuration Debug for project task1 ****
|
||||
make -j12 all
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"Startup/startup_stm32g431kbtx.d" -MT"Startup/startup_stm32g431kbtx.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Startup/startup_stm32g431kbtx.o" "../Startup/startup_stm32g431kbtx.s"
|
||||
arm-none-eabi-gcc "../Startup/syscalls.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Startup/syscalls.d" -MT"Startup/syscalls.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Startup/syscalls.o"
|
||||
arm-none-eabi-gcc "../Startup/sysmem.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Startup/sysmem.d" -MT"Startup/sysmem.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Startup/sysmem.o"
|
||||
arm-none-eabi-gcc "../Src/sketch.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/sketch.d" -MT"Src/sketch.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/sketch.o"
|
||||
arm-none-eabi-gcc "../Src/task1.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/task1.d" -MT"Src/task1.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/task1.o"
|
||||
arm-none-eabi-gcc "../Src/task1_it.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/task1_it.d" -MT"Src/task1_it.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/task1_it.o"
|
||||
../Src/sketch.c: In function 'main':
|
||||
../Src/sketch.c:11:42: error: expected expression before ')' token
|
||||
11 | while(/*schalter nicht gedrückt*/){}
|
||||
| ^
|
||||
../Src/sketch.c:12:9: warning: implicit declaration of function 'delay' [-Wimplicit-function-declaration]
|
||||
12 | delay(10);
|
||||
| ^~~~~
|
||||
../Src/sketch.c:13:39: error: expected expression before ')' token
|
||||
13 | while(/*schalter losgelassen*/){}
|
||||
| ^
|
||||
../Src/sketch.c:18:39: error: request for member 'length' in something not a structure or union
|
||||
18 | for(int i; i < reihenfolge.length - 1 && aktiv = 1; i ++){
|
||||
| ^
|
||||
../Src/sketch.c:20:20: warning: suggest parentheses around assignment used as truth value [-Wparentheses]
|
||||
20 | if(i = 0){/*alles bis auf LED0 auschalten*/}
|
||||
| ^
|
||||
../Src/sketch.c:21:20: warning: suggest parentheses around assignment used as truth value [-Wparentheses]
|
||||
21 | if(i = 1){/*..*/}
|
||||
| ^
|
||||
../Src/sketch.c:24:44: error: expected expression before ')' token
|
||||
24 | if(/*schalter gerückt*/){
|
||||
| ^
|
||||
../Src/sketch.c:32:42: error: expected expression before ')' token
|
||||
32 | while(/*Taster gedrückt*/){}
|
||||
| ^
|
||||
make: *** [Src/subdir.mk:25: Src/sketch.o] Error 1
|
||||
make: *** Waiting for unfinished jobs....
|
||||
../Src/task1.c: In function 'GPIO_init':
|
||||
../Src/task1.c:169:22: error: expected expression before '<<' token
|
||||
169 | GPIOA->MODER &= ~(3 ^<< 2); // Versuch: LED 1 Mode löschen :klappt so
|
||||
| ^~
|
||||
make: *** [Src/subdir.mk:25: Src/task1.o] Error 1
|
||||
"make -j12 all" terminated with exit code 2. Build might be incomplete.
|
||||
13:56:35 **** Incremental Build of configuration Debug for project task1 ****
|
||||
make -j12 all
|
||||
arm-none-eabi-gcc "../Src/sketch.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/sketch.d" -MT"Src/sketch.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/sketch.o"
|
||||
arm-none-eabi-gcc "../Src/task1.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/task1.d" -MT"Src/task1.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/task1.o"
|
||||
../Src/task1.c: In function 'GPIO_init':
|
||||
../Src/task1.c:169:22: error: expected expression before '<<' token
|
||||
169 | GPIOA->MODER &= ~(3 ^<< 2); // Versuch: LED 1 Mode löschen :klappt so
|
||||
| ^~
|
||||
make: *** [Src/subdir.mk:25: Src/task1.o] Error 1
|
||||
"make -j12 all" terminated with exit code 2. Build might be incomplete.
|
||||
14:02:22 **** Incremental Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
Target all ready
|
||||
|
||||
@ -1,9 +1,13 @@
|
||||
14:13:43 **** Clean-only build of configuration Debug for project task1 ****
|
||||
make -j12 clean
|
||||
rm -rf ./Startup/startup_stm32g431kbtx.d ./Startup/startup_stm32g431kbtx.o ./Startup/syscalls.cyclo ./Startup/syscalls.d ./Startup/syscalls.o ./Startup/syscalls.su ./Startup/sysmem.cyclo ./Startup/sysmem.d ./Startup/sysmem.o ./Startup/sysmem.su
|
||||
rm -rf ./Src/task1.cyclo ./Src/task1.d ./Src/task1.o ./Src/task1.su ./Src/task1_it.cyclo ./Src/task1_it.d ./Src/task1_it.o ./Src/task1_it.su
|
||||
rm -rf default.size.stdout task1.elf task1.list task1.map
|
||||
13:56:35 **** Incremental Build of configuration Debug for project task1 ****
|
||||
make -j12 all
|
||||
arm-none-eabi-gcc "../Src/sketch.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/sketch.d" -MT"Src/sketch.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/sketch.o"
|
||||
arm-none-eabi-gcc "../Src/task1.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/task1.d" -MT"Src/task1.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/task1.o"
|
||||
../Src/task1.c: In function 'GPIO_init':
|
||||
../Src/task1.c:169:22: error: expected expression before '<<' token
|
||||
169 | GPIOA->MODER &= ~(3 ^<< 2); // Versuch: LED 1 Mode löschen :klappt so
|
||||
| ^~
|
||||
make: *** [Src/subdir.mk:25: Src/task1.o] Error 1
|
||||
"make -j12 all" terminated with exit code 2. Build might be incomplete.
|
||||
|
||||
|
||||
14:13:44 Build Finished. 0 errors, 0 warnings. (took 187ms)
|
||||
13:56:35 Build Failed. 2 errors, 0 warnings. (took 166ms)
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
14:19:07 **** Incremental Build of configuration Debug for project task2 ****
|
||||
14:02:22 **** Incremental Build of configuration Debug for project task2 ****
|
||||
make -j12 all
|
||||
Target all ready
|
||||
|
||||
14:19:07 Build Finished. 0 errors, 0 warnings. (took 182ms)
|
||||
14:02:22 Build Finished. 0 errors, 0 warnings. (took 121ms)
|
||||
|
||||
|
||||
@ -0,0 +1,328 @@
|
||||
#****************************************************************************************#
|
||||
# Project: task2 - ASM: Interrupts
|
||||
# File: task2.s
|
||||
# Hardware: STefi Light v1.1
|
||||
# Processor: STM32G431KBT6U
|
||||
#****************************************************************************************#
|
||||
|
||||
.include "G431_addr.s"
|
||||
|
||||
// Zusätzliche und benötigte Adressen
|
||||
.equ RCC_AHB2ENR, 0x4002104C
|
||||
.equ RCC_APB2ENR, 0x40021060
|
||||
|
||||
.equ GPIOA_MODER, 0x48000000
|
||||
.equ GPIOA_ODR, 0x48000014
|
||||
|
||||
.equ GPIOC_MODER, 0x48000800
|
||||
.equ GPIOC_PUPDR, 0x4800080C
|
||||
.equ GPIOC_IDR, 0x48000810
|
||||
|
||||
.equ SYSCFG_BASE, 0x40010000
|
||||
.equ SYSCFG_EXTICR4, (SYSCFG_BASE + 0x14)
|
||||
|
||||
.equ EXTI_BASE, 0x40010400
|
||||
.equ EXTI_IMR1, (EXTI_BASE + 0x00)
|
||||
.equ EXTI_FTSR1, (EXTI_BASE + 0x0C)
|
||||
.equ EXTI_PR1, (EXTI_BASE + 0x14)
|
||||
|
||||
.equ NVIC_ISER1, 0xE000E104
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.section .vectortable,"a" // vector table at begin of ROM
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
|
||||
.word 0x20004000 // initial Stack Pointer
|
||||
.word 0x08000401 // initial Program Counter
|
||||
.word _ISR_NMI // non-masking interrupt
|
||||
.word _ISR_HARDF // hard fault interrupt
|
||||
|
||||
.space 0xD0 // padding 208 Bytes bis Offset 0xE0 (EXTI15_10 IRQ 40)
|
||||
.word _ISR_S0_S1 // gemeinsamer Interrupt für PC13 (S0) und PC14 (S1)
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.text // section .text (default section for program code)
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global init
|
||||
.type init, %function
|
||||
init:
|
||||
CPSID i // disable interrupts globally
|
||||
|
||||
MOVS r0, #0 // safely initialize the GPRs
|
||||
MOVS r1, #0
|
||||
MOVS r2, #0
|
||||
MOVS r3, #0
|
||||
MOVS r4, #0
|
||||
MOVS r5, #0
|
||||
MOVS r6, #0
|
||||
MOVS r7, #0
|
||||
MOV r8, r0
|
||||
MOV r9, r0
|
||||
MOV r10, r0
|
||||
MOV r11, r0
|
||||
MOV r12, r0
|
||||
|
||||
#--- enable port clocking
|
||||
LDR r1, =RCC_AHB2ENR
|
||||
MOVS r2, #0x05 // Bit 0 (GPIOA) und Bit 2 (GPIOC)
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#--- port init
|
||||
#- LEDs (PA0-PA3)
|
||||
LDR r1, =GPIOA_MODER
|
||||
LDR r2, =0x000000FF // Maske PA0-PA3
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
LDR r2, =0x00000055 // Maske Output 0101 0101
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- switch LED off
|
||||
LDR r1, =GPIOA_ODR
|
||||
MOVS r2, #0x0F // Maske LED0-3
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- buttons (PC13, PC14 als Input)
|
||||
LDR r1, =GPIOC_MODER
|
||||
LDR r2, =0x3C000000 // Maske Bits 26-29
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- Pull-Up für PC13, PC14
|
||||
LDR r1, =GPIOC_PUPDR
|
||||
LDR r2, =0x3C000000
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
LDR r2, =0x14000000 // 01 = Pull-Up für PC13 (Bits 27:26) und PC14 (Bits 29:28)
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#--- button interrupt config
|
||||
|
||||
#- enable clock for SYSCFG module
|
||||
LDR r1, =RCC_APB2ENR
|
||||
MOVS r2, #0x01
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
|
||||
LDR r1, =SYSCFG_EXTICR4
|
||||
LDR r2, =0x00000FF0 // Maske für EXTI13 (Bits 7:4) und EXTI14 (Bits 11:8)
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
LDR r2, =0x00000220 // Port C (0010) für EXTI13 und EXTI14
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- configure lines in EXTI module (EXTI_* registers)
|
||||
LDR r1, =EXTI_FTSR1 // Fallende Flanke
|
||||
LDR r2, =0x00006000 // Bits 13 und 14
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =EXTI_IMR1 // Maskierung aufheben
|
||||
LDR r2, =0x00006000
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- NVIC: set interrupt priority, clear pending bits
|
||||
LDR r1, =NVIC_ISER1
|
||||
LDR r2, =0x00000100 // Bit 8 für IRQ 40 (EXTI15_10)
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
CPSIE i // enable interrupts globally
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global main
|
||||
.type main, %function
|
||||
main:
|
||||
WFI
|
||||
B main
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global delay
|
||||
.type delay, %function
|
||||
delay:
|
||||
LDR r0, =106000 // Entprell-Zeit ~20ms
|
||||
.L1:
|
||||
SUBS r0, r0, #1
|
||||
BNE .L1
|
||||
BX lr
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.global stop
|
||||
stop:
|
||||
NOP
|
||||
B stop
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.lp1:
|
||||
.ltorg
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.section .exhand,"ax" // section for exception handlers
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_NMI, %function
|
||||
_ISR_NMI:
|
||||
LDR r1, =RCC_AHB2ENR
|
||||
MOV r2, #0x01
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_MODER
|
||||
MOVS r2, #0xFF
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
MOVS r2, #0x44
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_ODR
|
||||
MOVS r2, #0x0A
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
B _ISR_NMI
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_HARDF, %function
|
||||
_ISR_HARDF:
|
||||
LDR r1, =RCC_AHB2ENR
|
||||
MOV r2, #0x01
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_MODER
|
||||
MOVS r2, #0xFF
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
MOVS r2, #0x11
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_ODR
|
||||
MOVS r2, #0x05
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
B _ISR_HARDF
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_S0_S1, %function
|
||||
_ISR_S0_S1:
|
||||
PUSH {r4, r5, lr} // Wichtig: Register sichern gemäß AAPCS
|
||||
|
||||
_check_S0:
|
||||
LDR r4, =EXTI_PR1
|
||||
LDR r5, [r4, #0]
|
||||
LDR r2, =0x2000 // Maske für S0 (PC13 / Bit 13)
|
||||
TST r5, r2
|
||||
BEQ _check_S1 // Wenn Bit 13 nicht gesetzt, überspringen
|
||||
|
||||
#--- do the work S0
|
||||
BL delay // Entprellen
|
||||
|
||||
LDR r0, =GPIOC_IDR
|
||||
LDR r1, [r0, #0]
|
||||
LDR r2, =0x2000
|
||||
TST r1, r2
|
||||
BNE _clear_S0 // Abbruch, wenn High (Taster prellt / schon losgelassen)
|
||||
|
||||
LDR r0, =GPIOA_ODR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x09 // LED0 & LED3 toggeln (1001)
|
||||
EORS r1, r2
|
||||
STR r1, [r0, #0]
|
||||
|
||||
_clear_S0:
|
||||
#--- clear interrupt flag S0
|
||||
LDR r4, =EXTI_PR1
|
||||
LDR r5, =0x2000
|
||||
STR r5, [r4, #0]
|
||||
|
||||
_check_S1:
|
||||
LDR r4, =EXTI_PR1
|
||||
LDR r5, [r4, #0]
|
||||
LDR r2, =0x4000 // Maske für S1 (PC14 / Bit 14)
|
||||
TST r5, r2
|
||||
BEQ _leave_ISR // Wenn Bit 14 nicht gesetzt, Ende
|
||||
|
||||
#--- do the work S1
|
||||
BL delay
|
||||
|
||||
LDR r0, =GPIOC_IDR
|
||||
LDR r1, [r0, #0]
|
||||
LDR r2, =0x4000
|
||||
TST r1, r2
|
||||
BNE _clear_S1 // Abbruch, wenn High
|
||||
|
||||
LDR r0, =GPIOA_ODR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x06 // LED1 & LED2 toggeln (0110)
|
||||
EORS r1, r2
|
||||
STR r1, [r0, #0]
|
||||
|
||||
_clear_S1:
|
||||
#--- clear interrupt flag S1
|
||||
LDR r4, =EXTI_PR1
|
||||
LDR r5, =0x4000
|
||||
STR r5, [r4, #0]
|
||||
|
||||
_leave_ISR:
|
||||
#--- leave ISR
|
||||
POP {r4, r5, pc} // Register wiederherstellen und zurückkehren
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.lp2:
|
||||
.ltorg
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.end
|
||||
|
||||
#************************************** E O F *******************************************#
|
||||
@ -0,0 +1,347 @@
|
||||
#****************************************************************************************#
|
||||
# Project: task2 - ASM: Interrupts
|
||||
# File: task2.s
|
||||
# Hardware: STefi Light v1.1
|
||||
# Processor: STM32G431KBT6U
|
||||
#****************************************************************************************#
|
||||
|
||||
.include "G431_addr.s"
|
||||
|
||||
// Falls in G431_addr.s vorhanden, diesen Block löschen um Fehler zu vermeiden:
|
||||
.equ RCC_AHB2ENR, 0x4002104C
|
||||
.equ RCC_APB2ENR, 0x40021060
|
||||
|
||||
.equ GPIOA_MODER, 0x48000000
|
||||
.equ GPIOA_ODR, 0x48000014
|
||||
|
||||
.equ GPIOB_MODER, 0x48000400
|
||||
.equ GPIOB_PUPDR, 0x4800040C
|
||||
.equ GPIOB_IDR, 0x48000410
|
||||
|
||||
.equ SYSCFG_BASE, 0x40010000
|
||||
.equ SYSCFG_EXTICR1, (SYSCFG_BASE + 0x08)
|
||||
.equ SYSCFG_EXTICR2, (SYSCFG_BASE + 0x0C)
|
||||
|
||||
.equ EXTI_BASE, 0x40010400
|
||||
.equ EXTI_IMR1, (EXTI_BASE + 0x00)
|
||||
.equ EXTI_FTSR1, (EXTI_BASE + 0x0C)
|
||||
.equ EXTI_PR1, (EXTI_BASE + 0x14)
|
||||
|
||||
.equ NVIC_ISER0, 0xE000E100
|
||||
|
||||
.equ DBGMCU_CR, 0xE0042004 // Adresse des Debug Configuration Registers
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.section .vectortable,"a"
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
|
||||
.word 0x20004000 // initial Stack Pointer
|
||||
.word init // initial Program Counter
|
||||
.word _ISR_NMI // non-masking interrupt
|
||||
.word _ISR_HARDF // hard fault interrupt
|
||||
|
||||
.space 0x48 // Padding 72 Bytes (Offset 0x10 -> 0x58)
|
||||
.word _ISR_EXTI0 // EXTI0_IRQHandler (PB0 / S0) - IRQ 6
|
||||
|
||||
.space 0x0C // Padding 12 Bytes (Offset 0x5C -> 0x68)
|
||||
.word _ISR_EXTI4 // EXTI4_IRQHandler (PB4 / S1) - IRQ 10
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.text
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global init
|
||||
.type init, %function
|
||||
init:
|
||||
CPSID i
|
||||
|
||||
MOVS r0, #0
|
||||
MOVS r1, #0
|
||||
MOVS r2, #0
|
||||
MOVS r3, #0
|
||||
MOVS r4, #0
|
||||
MOVS r5, #0
|
||||
MOVS r6, #0
|
||||
MOVS r7, #0
|
||||
MOV r8, r0
|
||||
MOV r9, r0
|
||||
MOV r10, r0
|
||||
MOV r11, r0
|
||||
MOV r12, r0
|
||||
|
||||
#--- enable port clocking (GPIOA, GPIOB)
|
||||
LDR r1, =RCC_AHB2ENR
|
||||
MOVS r2, #0x03 // Bit 0 (GPIOA) und Bit 1 (GPIOB)
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#--- port init
|
||||
#- LEDs (PA0 - PA3) als Output
|
||||
LDR r1, =GPIOA_MODER
|
||||
LDR r2, =0x000000FF
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
LDR r2, =0x00000055
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- switch LED off
|
||||
LDR r1, =GPIOA_ODR
|
||||
MOVS r2, #0x0F
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- buttons (PB0, PB4) als Input
|
||||
LDR r1, =GPIOB_MODER
|
||||
LDR r2, =0x00000303 // Maske Bits 0:1 (PB0) und 8:9 (PB4)
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- Pull-Up für PB0, PB4
|
||||
LDR r1, =GPIOB_PUPDR
|
||||
LDR r2, =0x00000303
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
LDR r2, =0x00000101 // 01 = Pull-Up für PB0 und PB4
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#--- button interrupt config
|
||||
|
||||
#- enable clock for SYSCFG module
|
||||
LDR r1, =RCC_APB2ENR
|
||||
MOVS r2, #0x01
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- connect GPIO pins to EXTI lines
|
||||
LDR r1, =SYSCFG_EXTICR1 // EXTI0 (PB0)
|
||||
LDR r2, =0x000F // Maske EXTI0 (Bits 3:0)
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
MOVS r2, #0x0001 // Port B (0001)
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =SYSCFG_EXTICR2 // EXTI4 (PB4)
|
||||
LDR r2, =0x000F // Maske EXTI4 (Bits 3:0)
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
MOVS r2, #0x0001 // Port B (0001)
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- configure EXTI lines (falling edge, unmask)
|
||||
LDR r1, =EXTI_FTSR1
|
||||
MOVS r2, #0x11 // Bit 0 (EXTI0) und Bit 4 (EXTI4)
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =EXTI_IMR1
|
||||
MOVS r2, #0x11 // Bit 0 und Bit 4
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- NVIC: enable interrupts EXTI0 (IRQ 6) & EXTI4 (IRQ 10)
|
||||
LDR r1, =NVIC_ISER0
|
||||
LDR r2, =0x00000440 // Bit 6 (EXTI0) und Bit 10 (EXTI4)
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#--- wachhalten während WFI
|
||||
LDR r1, =DBGMCU_CR
|
||||
LDR r0, [r1, #0]
|
||||
MOVS r2, #0x07 // Setzt DBG_SLEEP, DBG_STOP und DBG_STANDBY Bits
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
CPSIE i
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global main
|
||||
.type main, %function
|
||||
main:
|
||||
WFI
|
||||
B main
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global delay
|
||||
.type delay, %function
|
||||
delay:
|
||||
LDR r0, =106000
|
||||
.L1:
|
||||
SUBS r0, r0, #1
|
||||
BNE .L1
|
||||
BX lr
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.global stop
|
||||
stop:
|
||||
NOP
|
||||
B stop
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.lp1:
|
||||
.ltorg
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.section .exhand,"ax"
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_NMI, %function
|
||||
_ISR_NMI:
|
||||
LDR r1, =RCC_AHB2ENR
|
||||
MOV r2, #0x01
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_MODER
|
||||
MOVS r2, #0xFF
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
MOVS r2, #0x44
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_ODR
|
||||
MOVS r2, #0x0A
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
B _ISR_NMI
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_HARDF, %function
|
||||
_ISR_HARDF:
|
||||
LDR r1, =RCC_AHB2ENR
|
||||
MOV r2, #0x01
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_MODER
|
||||
MOVS r2, #0xFF
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
MOVS r2, #0x11
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =GPIOA_ODR
|
||||
MOVS r2, #0x05
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
B _ISR_HARDF
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_EXTI0, %function
|
||||
_ISR_EXTI0:
|
||||
PUSH {lr}
|
||||
|
||||
#--- Entprellen
|
||||
BL delay
|
||||
|
||||
#--- Überprüfen, ob Taster noch gedrückt ist (PB0)
|
||||
LDR r0, =GPIOB_IDR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x01
|
||||
TST r1, r2
|
||||
BNE _clear_exti0
|
||||
|
||||
#--- LED0 & LED3 toggeln (1001 = 0x09)
|
||||
LDR r0, =GPIOA_ODR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x09
|
||||
EORS r1, r2
|
||||
STR r1, [r0, #0]
|
||||
|
||||
_clear_exti0:
|
||||
#--- Interrupt Flag löschen
|
||||
LDR r0, =EXTI_PR1
|
||||
MOVS r1, #0x01
|
||||
STR r1, [r0, #0]
|
||||
|
||||
POP {pc}
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_EXTI4, %function
|
||||
_ISR_EXTI4:
|
||||
PUSH {lr}
|
||||
|
||||
#--- Entprellen
|
||||
BL delay
|
||||
|
||||
#--- Überprüfen, ob Taster noch gedrückt ist (PB4)
|
||||
LDR r0, =GPIOB_IDR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x10
|
||||
TST r1, r2
|
||||
BNE _clear_exti4
|
||||
|
||||
#--- LED1 & LED2 toggeln (0110 = 0x06)
|
||||
LDR r0, =GPIOA_ODR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x06
|
||||
EORS r1, r2
|
||||
STR r1, [r0, #0]
|
||||
|
||||
_clear_exti4:
|
||||
#--- Interrupt Flag löschen
|
||||
LDR r0, =EXTI_PR1
|
||||
MOVS r1, #0x10
|
||||
STR r1, [r0, #0]
|
||||
|
||||
POP {pc}
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.lp2:
|
||||
.ltorg
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.end
|
||||
hu
|
||||
@ -0,0 +1,764 @@
|
||||
#*****************************************************************************************
|
||||
# Project: task2 - switch triggered LEDs
|
||||
# File: G431_addr.s
|
||||
#
|
||||
# Language: ASM
|
||||
#
|
||||
# Hardware: STefi v1.1
|
||||
# Processor: STM32G431KBT6U
|
||||
#
|
||||
# Author: Manuel Lederhofer
|
||||
# Datum: 20.08.2015
|
||||
#
|
||||
# Version: 3.0
|
||||
# History:
|
||||
# 20.08.2015 ML create file
|
||||
# 07.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
|
||||
# 27.02.2019 ML change from absolute addresses to BASE + OFFSET notation and
|
||||
# add more timer modules
|
||||
# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
|
||||
#
|
||||
# Status: working
|
||||
#
|
||||
# Description:
|
||||
# Connects assembly addresses for STM32G431 MCU to symbolic register names
|
||||
# used in the datasheets.
|
||||
#
|
||||
# Notes:
|
||||
# - default MCU speed at startup is 16 MHz.
|
||||
#
|
||||
# ToDo:
|
||||
# - none -
|
||||
#*****************************************************************************************
|
||||
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# MCU Bus Base Addresses
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ APB1_BASE, 0x40000000
|
||||
.equ APB2_BASE, 0x40010000
|
||||
.equ AHB1_BASE, 0x40020000
|
||||
.equ AHB2_BASE, 0x48000000
|
||||
.equ AHB3_BASE, 0xA0000000 //!!! FSMC + QSPI registers = AHB3 ?
|
||||
.equ PPB_BASE, 0xE0000000 /* Cortex M4 with FPU Internal Peripherals */
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# System Configuration Controller
|
||||
#
|
||||
# address space: 0x4001_0000 .. 0x4001_0029
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ SYSCFG_BASE, APB2_BASE
|
||||
|
||||
.equ SYSCFG_MEMRMP, SYSCFG_BASE + 0x00
|
||||
.equ SYSCFG_CFGR1, SYSCFG_BASE + 0x04
|
||||
.equ SYSCFG_EXTICR1, SYSCFG_BASE + 0x08
|
||||
.equ SYSCFG_EXTICR2, SYSCFG_BASE + 0x0C
|
||||
.equ SYSCFG_EXTICR3, SYSCFG_BASE + 0x10
|
||||
.equ SYSCFG_EXTICR4, SYSCFG_BASE + 0x14
|
||||
.equ SYSCFG_SCSR, SYSCFG_BASE + 0x18
|
||||
.equ SYSCFG_CFGR2, SYSCFG_BASE + 0x1C
|
||||
.equ SYSCFG_SWPR, SYSCFG_BASE + 0x20
|
||||
.equ SYSCFG_SKR, SYSCFG_BASE + 0x24
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# Extended Interrupts And Events Controller
|
||||
#
|
||||
# address space: 0x4001_0400 .. 0x4001_07FF
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ EXTI_BASE, APB2_BASE + 0x400
|
||||
|
||||
.equ EXTI_IMR1, EXTI_BASE + 0x00
|
||||
.equ EXTI_EMR1, EXTI_BASE + 0x04
|
||||
.equ EXTI_RTSR1, EXTI_BASE + 0x08
|
||||
.equ EXTI_FTSR1, EXTI_BASE + 0x0C
|
||||
.equ EXTI_SWIER1, EXTI_BASE + 0x10
|
||||
.equ EXTI_PR1, EXTI_BASE + 0x14
|
||||
|
||||
.equ EXTI_IMR2, EXTI_BASE + 0x20
|
||||
.equ EXTI_EMR2, EXTI_BASE + 0x24
|
||||
.equ EXTI_RTSR2, EXTI_BASE + 0x28
|
||||
.equ EXTI_FTSR2, EXTI_BASE + 0x2C
|
||||
.equ EXTI_SWIER2, EXTI_BASE + 0x30
|
||||
.equ EXTI_PR2, EXTI_BASE + 0x34
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# TIM module common configuration
|
||||
#
|
||||
# Every timer has 1 KB address space:
|
||||
#
|
||||
# TIM2 .. TIM7: 0x4000_0000 .. 0x4000_17FF (APB1)
|
||||
# TIM1: 0x4001_2C00 .. 0x4001_2FFF (APB2)
|
||||
# TIM8: 0x4001_3400 .. 0x4001_37FF (APB2)
|
||||
# TIM15 .. TIM17: 0x4001_4000 .. 0x4001_4BFF (APB2)
|
||||
# TIM20: 0x4001_5000 .. 0x4001_53FF (APB2)
|
||||
#
|
||||
# note:
|
||||
# TIM2 + TIM5 are 32 bit timers. All others have a width of 16 bit.
|
||||
# Below, the timers on one line share a common register set description.
|
||||
#
|
||||
# TIM 1, 8, 20 advances control timers
|
||||
# TIM 2, 3, 4, 5 general purpose timers (TIM2/5 = 32 bit)
|
||||
# TIM 15 general purpose timers
|
||||
# TIM 16, 17 general purpose timers
|
||||
# TIM 6, 7 basic timers
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ TIM_CR1_OFFSET, 0x00
|
||||
.equ TIM_CR2_OFFSET, 0x04
|
||||
.equ TIM_SMCR_OFFSET, 0x08
|
||||
.equ TIM_DIER_OFFSET, 0x0C
|
||||
.equ TIM_SR_OFFSET, 0x10
|
||||
.equ TIM_EGR_OFFSET, 0x14
|
||||
.equ TIM_CCMR1_OFFSET, 0x18
|
||||
.equ TIM_CCMR2_OFFSET, 0x1C
|
||||
.equ TIM_CCER_OFFSET, 0x20
|
||||
.equ TIM_CNT_OFFSET, 0x24
|
||||
.equ TIM_PSC_OFFSET, 0x28
|
||||
.equ TIM_ARR_OFFSET, 0x2C
|
||||
.equ TIM_RCR_OFFSET, 0x30
|
||||
.equ TIM_CCR1_OFFSET, 0x34
|
||||
.equ TIM_CCR2_OFFSET, 0x38
|
||||
.equ TIM_CCR3_OFFSET, 0x3C
|
||||
.equ TIM_CCR4_OFFSET, 0x40
|
||||
.equ TIM_BDTR_OFFSET, 0x44
|
||||
.equ TIM_CCR5_OFFSET, 0x48
|
||||
.equ TIM_CCR6_OFFSET, 0x4C
|
||||
.equ TIM_CCMR3_OFFSET, 0x50
|
||||
.equ TIM_DTR2_OFFSET, 0x54
|
||||
.equ TIM_ECR_OFFSET, 0x58
|
||||
.equ TIM_TISEL_OFFSET, 0x5C
|
||||
.equ TIM_AF1_OFFSET, 0x60
|
||||
.equ TIM_AF2_OFFSET, 0x64
|
||||
.equ TIM_OR1_OFFSET, 0x68
|
||||
|
||||
.equ TIM_DCR_OFFSET, 0x3DC
|
||||
.equ TIM_DMAR_OFFSET, 0x3E0
|
||||
|
||||
#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
|
||||
|
||||
#--- Genral Purpose Timer - TIM2 / address space: 0x4000_0000 .. 0x4000_03FF
|
||||
|
||||
.equ TIM2_BASE, APB1_BASE
|
||||
|
||||
.equ TIM2_CR1, TIM2_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM2_CR2, TIM2_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM2_SMCR, TIM2_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM2_DIER, TIM2_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM2_SR, TIM2_BASE + TIM_SR_OFFSET
|
||||
.equ TIM2_EGR, TIM2_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM2_CCMR1, TIM2_BASE + TIM_CCMR1_OFFSET
|
||||
.equ TIM2_CCMR2, TIM2_BASE + TIM_CCMR2_OFFSET
|
||||
.equ TIM2_CCER, TIM2_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM2_CNT, TIM2_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM2_PSC, TIM2_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM2_ARR, TIM2_BASE + TIM_ARR_OFFSET
|
||||
|
||||
.equ TIM2_CCR1, TIM2_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM2_CCR2, TIM2_BASE + TIM_CCR2_OFFSET
|
||||
.equ TIM2_CCR3, TIM2_BASE + TIM_CCR3_OFFSET
|
||||
.equ TIM2_CCR4, TIM2_BASE + TIM_CCR4_OFFSET
|
||||
|
||||
.equ TIM2_ECR, TIM2_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM2_TISEL, TIM2_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM2_AF1, TIM2_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM2_AF2, TIM2_BASE + TIM_ECR_OFFSET
|
||||
|
||||
.equ TIM2_DCR, TIM2_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM2_DMAR, TIM2_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Genral Purpose Timer - TIM3 / address space: 0x4000_0400 .. 0x4000_07FF
|
||||
|
||||
.equ TIM3_BASE, APB1_BASE + 0x400
|
||||
|
||||
.equ TIM3_CR1, TIM3_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM3_CR2, TIM3_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM3_SMCR, TIM3_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM3_DIER, TIM3_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM3_SR, TIM3_BASE + TIM_SR_OFFSET
|
||||
.equ TIM3_EGR, TIM3_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM3_CCMR1, TIM3_BASE + TIM_CCMR1_OFFSET
|
||||
.equ TIM3_CCMR2, TIM3_BASE + TIM_CCMR2_OFFSET
|
||||
.equ TIM3_CCER, TIM3_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM3_CNT, TIM3_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM3_PSC, TIM3_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM3_ARR, TIM3_BASE + TIM_ARR_OFFSET
|
||||
|
||||
.equ TIM3_CCR1, TIM3_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM3_CCR2, TIM3_BASE + TIM_CCR2_OFFSET
|
||||
.equ TIM3_CCR3, TIM3_BASE + TIM_CCR3_OFFSET
|
||||
.equ TIM3_CCR4, TIM3_BASE + TIM_CCR4_OFFSET
|
||||
|
||||
.equ TIM3_ECR, TIM3_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM3_TISEL, TIM3_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM3_AF1, TIM3_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM3_AF2, TIM3_BASE + TIM_ECR_OFFSET
|
||||
|
||||
.equ TIM3_DCR, TIM3_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM3_DMAR, TIM3_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Genral Purpose Timer - TIM4 / address space: 0x4000_0800 .. 0x4000_0BFF
|
||||
|
||||
.equ TIM4_BASE, APB1_BASE + 0x800
|
||||
|
||||
.equ TIM4_CR1, TIM4_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM4_CR2, TIM4_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM4_SMCR, TIM4_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM4_DIER, TIM4_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM4_SR, TIM4_BASE + TIM_SR_OFFSET
|
||||
.equ TIM4_EGR, TIM4_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM4_CCMR1, TIM4_BASE + TIM_CCMR1_OFFSET
|
||||
.equ TIM4_CCMR2, TIM4_BASE + TIM_CCMR2_OFFSET
|
||||
.equ TIM4_CCER, TIM4_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM4_CNT, TIM4_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM4_PSC, TIM4_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM4_ARR, TIM4_BASE + TIM_ARR_OFFSET
|
||||
|
||||
.equ TIM4_CCR1, TIM4_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM4_CCR2, TIM4_BASE + TIM_CCR2_OFFSET
|
||||
.equ TIM4_CCR3, TIM4_BASE + TIM_CCR3_OFFSET
|
||||
.equ TIM4_CCR4, TIM4_BASE + TIM_CCR4_OFFSET
|
||||
|
||||
.equ TIM4_ECR, TIM4_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM4_TISEL, TIM4_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM4_AF1, TIM4_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM4_AF2, TIM4_BASE + TIM_ECR_OFFSET
|
||||
|
||||
.equ TIM4_DCR, TIM4_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM4_DMAR, TIM4_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Genral Purpose Timer - TIM5 / address space: 0x4000_0C00 .. 0x4000_0FFF
|
||||
|
||||
.equ TIM5_BASE, APB1_BASE + 0xC00
|
||||
|
||||
.equ TIM5_CR1, TIM5_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM5_CR2, TIM5_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM5_SMCR, TIM5_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM5_DIER, TIM5_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM5_SR, TIM5_BASE + TIM_SR_OFFSET
|
||||
.equ TIM5_EGR, TIM5_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM5_CCMR1, TIM5_BASE + TIM_CCMR1_OFFSET
|
||||
.equ TIM5_CCMR2, TIM5_BASE + TIM_CCMR2_OFFSET
|
||||
.equ TIM5_CCER, TIM5_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM5_CNT, TIM5_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM5_PSC, TIM5_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM5_ARR, TIM5_BASE + TIM_ARR_OFFSET
|
||||
|
||||
.equ TIM5_CCR1, TIM5_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM5_CCR2, TIM5_BASE + TIM_CCR2_OFFSET
|
||||
.equ TIM5_CCR3, TIM5_BASE + TIM_CCR3_OFFSET
|
||||
.equ TIM5_CCR4, TIM5_BASE + TIM_CCR4_OFFSET
|
||||
|
||||
.equ TIM5_ECR, TIM5_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM5_TISEL, TIM5_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM5_AF1, TIM5_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM5_AF2, TIM5_BASE + TIM_ECR_OFFSET
|
||||
|
||||
.equ TIM5_DCR, TIM5_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM5_DMAR, TIM5_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Basic Timer - TIM6 / address space: 0x4000_1000 .. 0x4000_13FF
|
||||
|
||||
.equ TIM6_BASE, APB1_BASE + 0x1000
|
||||
|
||||
.equ TIM6_CR1, TIM6_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM6_CR2, TIM6_BASE + TIM_CR2_OFFSET
|
||||
|
||||
.equ TIM6_DIER, TIM6_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM6_SR, TIM6_BASE + TIM_SR_OFFSET
|
||||
.equ TIM6_EGR, TIM6_BASE + TIM_EGR_OFFSET
|
||||
|
||||
.equ TIM6_CNT, TIM6_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM6_PSC, TIM6_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM6_ARR, TIM6_BASE + TIM_ARR_OFFSET
|
||||
|
||||
#--- Basic Timer - TIM7 / address space: 0x4000_1400 .. 0x4000_17FF
|
||||
|
||||
.equ TIM7_BASE, APB1_BASE + 0x1400
|
||||
|
||||
.equ TIM7_CR1, TIM7_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM7_CR2, TIM7_BASE + TIM_CR2_OFFSET
|
||||
|
||||
.equ TIM7_DIER, TIM7_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM7_SR, TIM7_BASE + TIM_SR_OFFSET
|
||||
.equ TIM7_EGR, TIM7_BASE + TIM_EGR_OFFSET
|
||||
|
||||
.equ TIM7_CNT, TIM7_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM7_PSC, TIM7_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM7_ARR, TIM7_BASE + TIM_ARR_OFFSET
|
||||
|
||||
#--- Advanced Control Timer - TIM1 / address space: 0x4001_2C00 .. 0x4001_2FFF
|
||||
|
||||
.equ TIM1_BASE, APB2_BASE + 0x2C00
|
||||
|
||||
.equ TIM1_CR1, TIM1_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM1_CR2, TIM1_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM1_SMCR, TIM1_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM1_DIER, TIM1_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM1_SR, TIM1_BASE + TIM_SR_OFFSET
|
||||
.equ TIM1_EGR, TIM1_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM1_CCMR1, TIM1_BASE + TIM_CCMR1_OFFSET
|
||||
.equ TIM1_CCMR2, TIM1_BASE + TIM_CCMR2_OFFSET
|
||||
.equ TIM1_CCER, TIM1_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM1_CNT, TIM1_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM1_PSC, TIM1_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM1_ARR, TIM1_BASE + TIM_ARR_OFFSET
|
||||
.equ TIM1_RCR, TIM1_BASE + TIM_RCR_OFFSET
|
||||
.equ TIM1_CCR1, TIM1_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM1_CCR2, TIM1_BASE + TIM_CCR2_OFFSET
|
||||
.equ TIM1_CCR3, TIM1_BASE + TIM_CCR3_OFFSET
|
||||
.equ TIM1_CCR4, TIM1_BASE + TIM_CCR4_OFFSET
|
||||
.equ TIM1_BDTR, TIM1_BASE + TIM_BDTR_OFFSET
|
||||
.equ TIM1_CCR5, TIM1_BASE + TIM_CCR5_OFFSET
|
||||
.equ TIM1_CCR6, TIM1_BASE + TIM_CCR6_OFFSET
|
||||
.equ TIM1_CCMR3, TIM1_BASE + TIM_CCMR3_OFFSET
|
||||
.equ TIM1_DTR2, TIM1_BASE + TIM_DTR2_OFFSET
|
||||
.equ TIM1_ECR, TIM1_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM1_TISEL, TIM1_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM1_AF1, TIM1_BASE + TIM_AF1_OFFSET
|
||||
.equ TIM1_AF2, TIM1_BASE + TIM_AF2_OFFSET
|
||||
|
||||
.equ TIM1_DCR, TIM1_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM1_DMAR, TIM1_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Advanced Control Timer - TIM8 / address space: 0x4001_3400 .. 0x4001_37FF
|
||||
|
||||
.equ TIM8_BASE, APB2_BASE + 0x3400
|
||||
|
||||
.equ TIM8_CR1, TIM8_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM8_CR2, TIM8_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM8_SMCR, TIM8_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM8_DIER, TIM8_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM8_SR, TIM8_BASE + TIM_SR_OFFSET
|
||||
.equ TIM8_EGR, TIM8_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM8_CCMR1, TIM8_BASE + TIM_CCMR1_OFFSET
|
||||
.equ TIM8_CCMR2, TIM8_BASE + TIM_CCMR2_OFFSET
|
||||
.equ TIM8_CCER, TIM8_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM8_CNT, TIM8_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM8_PSC, TIM8_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM8_ARR, TIM8_BASE + TIM_ARR_OFFSET
|
||||
.equ TIM8_RCR, TIM8_BASE + TIM_RCR_OFFSET
|
||||
.equ TIM8_CCR1, TIM8_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM8_CCR2, TIM8_BASE + TIM_CCR2_OFFSET
|
||||
.equ TIM8_CCR3, TIM8_BASE + TIM_CCR3_OFFSET
|
||||
.equ TIM8_CCR4, TIM8_BASE + TIM_CCR4_OFFSET
|
||||
.equ TIM8_BDTR, TIM8_BASE + TIM_BDTR_OFFSET
|
||||
.equ TIM8_CCR5, TIM8_BASE + TIM_CCR5_OFFSET
|
||||
.equ TIM8_CCR6, TIM8_BASE + TIM_CCR6_OFFSET
|
||||
.equ TIM8_CCMR3, TIM8_BASE + TIM_CCMR3_OFFSET
|
||||
.equ TIM8_DTR2, TIM8_BASE + TIM_DTR2_OFFSET
|
||||
.equ TIM8_ECR, TIM8_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM8_TISEL, TIM8_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM8_AF1, TIM8_BASE + TIM_AF1_OFFSET
|
||||
.equ TIM8_AF2, TIM8_BASE + TIM_AF2_OFFSET
|
||||
|
||||
.equ TIM8_DCR, TIM8_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM8_DMAR, TIM8_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Advanced Control Timer - TIM20 / address space: 0x4001_5000 .. 0x4001_53FF
|
||||
|
||||
.equ TIM20_BASE, APB2_BASE + 0x5000
|
||||
|
||||
.equ TIM20_CR1, TIM20_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM20_CR2, TIM20_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM20_SMCR, TIM20_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM20_DIER, TIM20_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM20_SR, TIM20_BASE + TIM_SR_OFFSET
|
||||
.equ TIM20_EGR, TIM20_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM20_CCMR1, TIM20_BASE + TIM_CCMR1_OFFSET
|
||||
.equ TIM20_CCMR2, TIM20_BASE + TIM_CCMR2_OFFSET
|
||||
.equ TIM20_CCER, TIM20_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM20_CNT, TIM20_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM20_PSC, TIM20_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM20_ARR, TIM20_BASE + TIM_ARR_OFFSET
|
||||
.equ TIM20_RCR, TIM20_BASE + TIM_RCR_OFFSET
|
||||
.equ TIM20_CCR1, TIM20_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM20_CCR2, TIM20_BASE + TIM_CCR2_OFFSET
|
||||
.equ TIM20_CCR3, TIM20_BASE + TIM_CCR3_OFFSET
|
||||
.equ TIM20_CCR4, TIM20_BASE + TIM_CCR4_OFFSET
|
||||
.equ TIM20_BDTR, TIM20_BASE + TIM_BDTR_OFFSET
|
||||
.equ TIM20_CCR5, TIM20_BASE + TIM_CCR5_OFFSET
|
||||
.equ TIM20_CCR6, TIM20_BASE + TIM_CCR6_OFFSET
|
||||
.equ TIM20_CCMR3, TIM20_BASE + TIM_CCMR3_OFFSET
|
||||
.equ TIM20_DTR2, TIM20_BASE + TIM_DTR2_OFFSET
|
||||
.equ TIM20_ECR, TIM20_BASE + TIM_ECR_OFFSET
|
||||
.equ TIM20_TISEL, TIM20_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM20_AF1, TIM20_BASE + TIM_AF1_OFFSET
|
||||
.equ TIM20_AF2, TIM20_BASE + TIM_AF2_OFFSET
|
||||
|
||||
.equ TIM20_DCR, TIM20_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM20_DMAR, TIM20_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Genral Purpose Timer - TIM15 / address space: 0x4001_4000 .. 0x4001_43FF
|
||||
|
||||
.equ TIM15_BASE, APB2_BASE + 0x4000
|
||||
|
||||
.equ TIM15_CR1, TIM15_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM15_CR2, TIM15_BASE + TIM_CR2_OFFSET
|
||||
.equ TIM15_SMCR, TIM15_BASE + TIM_SMCR_OFFSET
|
||||
.equ TIM15_DIER, TIM15_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM15_SR, TIM15_BASE + TIM_SR_OFFSET
|
||||
.equ TIM15_EGR, TIM15_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM15_CCMR1, TIM15_BASE + TIM_CCMR1_OFFSET
|
||||
|
||||
.equ TIM15_CCER, TIM15_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM15_CNT, TIM15_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM15_PSC, TIM15_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM15_ARR, TIM15_BASE + TIM_ARR_OFFSET
|
||||
.equ TIM15_RCR, TIM15_BASE + TIM_RCR_OFFSET
|
||||
.equ TIM15_CCR1, TIM15_BASE + TIM_CCR1_OFFSET
|
||||
.equ TIM15_CCR2, TIM15_BASE + TIM_CCR2_OFFSET
|
||||
|
||||
.equ TIM15_BDTR, TIM15_BASE + TIM_BDTR_OFFSET
|
||||
|
||||
.equ TIM15_DTR2, TIM15_BASE + TIM_DTR2_OFFSET
|
||||
|
||||
.equ TIM15_TISEL, TIM15_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM15_AF1, TIM15_BASE + TIM_AF1_OFFSET
|
||||
.equ TIM15_AF2, TIM15_BASE + TIM_AF2_OFFSET
|
||||
|
||||
.equ TIM15_DCR, TIM15_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM15_DMAR, TIM15_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Genral Purpose Timer - TIM16 / address space: 0x4001_4400 .. 0x4001_47FF
|
||||
|
||||
.equ TIM16_BASE, APB2_BASE + 0x4400
|
||||
|
||||
.equ TIM16_CR1, TIM16_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM16_CR2, TIM16_BASE + TIM_CR2_OFFSET
|
||||
|
||||
.equ TIM16_DIER, TIM16_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM16_SR, TIM16_BASE + TIM_SR_OFFSET
|
||||
.equ TIM16_EGR, TIM16_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM16_CCMR1, TIM16_BASE + TIM_CCMR1_OFFSET
|
||||
|
||||
.equ TIM16_CCER, TIM16_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM16_CNT, TIM16_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM16_PSC, TIM16_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM16_ARR, TIM16_BASE + TIM_ARR_OFFSET
|
||||
.equ TIM16_RCR, TIM16_BASE + TIM_RCR_OFFSET
|
||||
.equ TIM16_CCR1, TIM16_BASE + TIM_CCR1_OFFSET
|
||||
|
||||
.equ TIM16_BDTR, TIM16_BASE + TIM_BDTR_OFFSET
|
||||
|
||||
.equ TIM16_DTR2, TIM16_BASE + TIM_DTR2_OFFSET
|
||||
|
||||
.equ TIM16_TISEL, TIM16_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM16_AF1, TIM16_BASE + TIM_AF1_OFFSET
|
||||
.equ TIM16_AF2, TIM16_BASE + TIM_AF2_OFFSET
|
||||
.equ TIM16_OR1, TIM16_BASE + TIM_OR1_OFFSET
|
||||
|
||||
.equ TIM16_DCR, TIM16_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM16_DMAR, TIM16_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#--- Genral Purpose Timer - TIM17 / address space: 0x4001_4800 .. 0x4001_4BFF
|
||||
|
||||
.equ TIM17_BASE, APB2_BASE + 0x4800
|
||||
|
||||
.equ TIM17_CR1, TIM17_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM17_CR2, TIM17_BASE + TIM_CR2_OFFSET
|
||||
|
||||
.equ TIM17_DIER, TIM17_BASE + TIM_DIER_OFFSET
|
||||
.equ TIM17_SR, TIM17_BASE + TIM_SR_OFFSET
|
||||
.equ TIM17_EGR, TIM17_BASE + TIM_EGR_OFFSET
|
||||
.equ TIM17_CCMR1, TIM17_BASE + TIM_CCMR1_OFFSET
|
||||
|
||||
.equ TIM17_CCER, TIM17_BASE + TIM_CCER_OFFSET
|
||||
.equ TIM17_CNT, TIM17_BASE + TIM_CNT_OFFSET
|
||||
.equ TIM17_PSC, TIM17_BASE + TIM_PSC_OFFSET
|
||||
.equ TIM17_ARR, TIM17_BASE + TIM_ARR_OFFSET
|
||||
.equ TIM17_RCR, TIM17_BASE + TIM_RCR_OFFSET
|
||||
.equ TIM17_CCR1, TIM17_BASE + TIM_CCR1_OFFSET
|
||||
|
||||
.equ TIM17_BDTR, TIM17_BASE + TIM_BDTR_OFFSET
|
||||
|
||||
.equ TIM17_DTR2, TIM17_BASE + TIM_DTR2_OFFSET
|
||||
|
||||
.equ TIM17_TISEL, TIM17_BASE + TIM_TISEL_OFFSET
|
||||
.equ TIM17_AF1, TIM17_BASE + TIM_AF1_OFFSET
|
||||
.equ TIM17_AF2, TIM17_BASE + TIM_AF2_OFFSET
|
||||
.equ TIM17_OR1, TIM17_BASE + TIM_OR1_OFFSET
|
||||
|
||||
.equ TIM17_DCR, TIM17_BASE + TIM_DCR_OFFSET
|
||||
.equ TIM17_DMAR, TIM17_BASE + TIM_DMAR_OFFSET
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# Reset and Clock Control
|
||||
#
|
||||
# address space: 0x4002_1000 .. 0x4002_13FF
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ RCC_BASE, AHB1_BASE + 0x1000
|
||||
|
||||
.equ RCC_CR, RCC_BASE + 0x00
|
||||
.equ RCC_ICSCR, RCC_BASE + 0x04
|
||||
.equ RCC_CFGR, RCC_BASE + 0x08
|
||||
.equ RCC_PLLCFGR, RCC_BASE + 0x0C
|
||||
|
||||
.equ RCC_CIER, RCC_BASE + 0x18
|
||||
.equ RCC_CIFR, RCC_BASE + 0x1C
|
||||
.equ RCC_CICR, RCC_BASE + 0x20
|
||||
|
||||
.equ RCC_AHB1RSTR, RCC_BASE + 0x28
|
||||
.equ RCC_AHB2RSTR, RCC_BASE + 0x2C
|
||||
.equ RCC_AHB3RSTR, RCC_BASE + 0x30
|
||||
|
||||
.equ RCC_APB1RSTR1, RCC_BASE + 0x38
|
||||
.equ RCC_APB1RSTR2, RCC_BASE + 0x3C
|
||||
.equ RCC_APB2RSTR, RCC_BASE + 0x40
|
||||
|
||||
.equ RCC_AHB1ENR, RCC_BASE + 0x48
|
||||
.equ RCC_AHB2ENR, RCC_BASE + 0x4C
|
||||
.equ RCC_AHB3ENR, RCC_BASE + 0x50
|
||||
|
||||
.equ RCC_APB1ENR1, RCC_BASE + 0x58
|
||||
.equ RCC_APB1ENR2, RCC_BASE + 0x5C
|
||||
.equ RCC_APB2ENR, RCC_BASE + 0x60
|
||||
|
||||
.equ RCC_AHB1SMENR, RCC_BASE + 0x68
|
||||
.equ RCC_AHB2SMENR, RCC_BASE + 0x6C
|
||||
.equ RCC_AHB3SMENR, RCC_BASE + 0x70
|
||||
|
||||
.equ RCC_APB1SMENR1, RCC_BASE + 0x78
|
||||
.equ RCC_APB1SMENR2, RCC_BASE + 0x7C
|
||||
.equ RCC_APB2SMENR, RCC_BASE + 0x80
|
||||
|
||||
.equ RCC_CCIPR, RCC_BASE + 0x88
|
||||
|
||||
.equ RCC_BDCR, RCC_BASE + 0x90
|
||||
.equ RCC_CSR, RCC_BASE + 0x94
|
||||
.equ RCC_CRRCR, RCC_BASE + 0x98
|
||||
.equ RCC_CCIPR2, RCC_BASE + 0x9C
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# GPIO module common configuration
|
||||
#
|
||||
# address space: 0x4800_0000 .. 0x4800_1FFF
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ GPIO_BASE, AHB2_BASE
|
||||
|
||||
.equ GPIO_MODER_OFFSET, 0x00
|
||||
.equ GPIO_OTYPER_OFFSET, 0x04
|
||||
.equ GPIO_OSPEEDR_OFFSET, 0x08
|
||||
.equ GPIO_PUPDR_OFFSET, 0x0C
|
||||
.equ GPIO_IDR_OFFSET, 0x10
|
||||
.equ GPIO_ODR_OFFSET, 0x14
|
||||
.equ GPIO_BSRR_OFFSET, 0x18
|
||||
.equ GPIO_LCKR_OFFSET, 0x1C
|
||||
.equ GPIO_AFRL_OFFSET, 0x20
|
||||
.equ GPIO_AFRH_OFFSET, 0x24
|
||||
.equ GPIO_BRR_OFFSET, 0x28
|
||||
|
||||
#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
|
||||
|
||||
#--- Port A GPIO configuration / address space: 0x4800_0000 .. 0x4800_03FF
|
||||
|
||||
.equ GPIOA_BASE, GPIO_BASE
|
||||
|
||||
.equ GPIOA_MODER, GPIOA_BASE + GPIO_MODER_OFFSET
|
||||
.equ GPIOA_OTYPER, GPIOA_BASE + GPIO_OTYPER_OFFSET
|
||||
.equ GPIOA_OSPEEDR, GPIOA_BASE + GPIO_OSPEEDR_OFFSET
|
||||
.equ GPIOA_PUPDR, GPIOA_BASE + GPIO_PUPDR_OFFSET
|
||||
.equ GPIOA_IDR, GPIOA_BASE + GPIO_IDR_OFFSET
|
||||
.equ GPIOA_ODR, GPIOA_BASE + GPIO_ODR_OFFSET
|
||||
.equ GPIOA_BSRR, GPIOA_BASE + GPIO_BSRR_OFFSET
|
||||
.equ GPIOA_LCKR, GPIOA_BASE + GPIO_LCKR_OFFSET
|
||||
.equ GPIOA_AFRL, GPIOA_BASE + GPIO_AFRL_OFFSET
|
||||
.equ GPIOA_AFRH, GPIOA_BASE + GPIO_AFRH_OFFSET
|
||||
.equ GPIOA_BRR, GPIOA_BASE + GPIO_BRR_OFFSET
|
||||
|
||||
#--- Port B GPIO configuration / address space: 0x4800_0400 .. 0x4800_07FF
|
||||
|
||||
.equ GPIOB_BASE, GPIO_BASE + 0x400
|
||||
|
||||
.equ GPIOB_MODER, GPIOB_BASE + GPIO_MODER_OFFSET
|
||||
.equ GPIOB_OTYPER, GPIOB_BASE + GPIO_OTYPER_OFFSET
|
||||
.equ GPIOB_OSPEEDR, GPIOB_BASE + GPIO_OSPEEDR_OFFSET
|
||||
.equ GPIOB_PUPDR, GPIOB_BASE + GPIO_PUPDR_OFFSET
|
||||
.equ GPIOB_IDR, GPIOB_BASE + GPIO_IDR_OFFSET
|
||||
.equ GPIOB_ODR, GPIOB_BASE + GPIO_ODR_OFFSET
|
||||
.equ GPIOB_BSRR, GPIOB_BASE + GPIO_BSRR_OFFSET
|
||||
.equ GPIOB_LCKR, GPIOB_BASE + GPIO_LCKR_OFFSET
|
||||
.equ GPIOB_AFRL, GPIOB_BASE + GPIO_AFRL_OFFSET
|
||||
.equ GPIOB_AFRH, GPIOB_BASE + GPIO_AFRH_OFFSET
|
||||
.equ GPIOB_BRR, GPIOB_BASE + GPIO_BRR_OFFSET
|
||||
|
||||
#--- Port C GPIO configuration / address space: 0x4800_0800 .. 0x4800_0BFF
|
||||
|
||||
.equ GPIOC_BASE, GPIO_BASE + 0x800
|
||||
|
||||
.equ GPIOC_MODER, GPIOC_BASE + GPIO_MODER_OFFSET
|
||||
.equ GPIOC_OTYPER, GPIOC_BASE + GPIO_OTYPER_OFFSET
|
||||
.equ GPIOC_OSPEEDR, GPIOC_BASE + GPIO_OSPEEDR_OFFSET
|
||||
.equ GPIOC_PUPDR, GPIOC_BASE + GPIO_PUPDR_OFFSET
|
||||
.equ GPIOC_IDR, GPIOC_BASE + GPIO_IDR_OFFSET
|
||||
.equ GPIOC_ODR, GPIOC_BASE + GPIO_ODR_OFFSET
|
||||
.equ GPIOC_BSRR, GPIOC_BASE + GPIO_BSRR_OFFSET
|
||||
.equ GPIOC_LCKR, GPIOC_BASE + GPIO_LCKR_OFFSET
|
||||
.equ GPIOC_AFRL, GPIOC_BASE + GPIO_AFRL_OFFSET
|
||||
.equ GPIOC_AFRH, GPIOC_BASE + GPIO_AFRH_OFFSET
|
||||
.equ GPIOC_BRR, GPIOC_BASE + GPIO_BRR_OFFSET
|
||||
|
||||
#--- Port D GPIO configuration / address space: 0x4800_0C00 .. 0x4800_0FFF
|
||||
|
||||
.equ GPIOD_BASE, GPIO_BASE + 0xC00
|
||||
|
||||
.equ GPIOD_MODER, GPIOD_BASE + GPIO_MODER_OFFSET
|
||||
.equ GPIOD_OTYPER, GPIOD_BASE + GPIO_OTYPER_OFFSET
|
||||
.equ GPIOD_OSPEEDR, GPIOD_BASE + GPIO_OSPEEDR_OFFSET
|
||||
.equ GPIOD_PUPDR, GPIOD_BASE + GPIO_PUPDR_OFFSET
|
||||
.equ GPIOD_IDR, GPIOD_BASE + GPIO_IDR_OFFSET
|
||||
.equ GPIOD_ODR, GPIOD_BASE + GPIO_ODR_OFFSET
|
||||
.equ GPIOD_BSRR, GPIOD_BASE + GPIO_BSRR_OFFSET
|
||||
.equ GPIOD_LCKR, GPIOD_BASE + GPIO_LCKR_OFFSET
|
||||
.equ GPIOD_AFRL, GPIOD_BASE + GPIO_AFRL_OFFSET
|
||||
.equ GPIOD_AFRH, GPIOD_BASE + GPIO_AFRH_OFFSET
|
||||
.equ GPIOD_BRR, GPIOD_BASE + GPIO_BRR_OFFSET
|
||||
|
||||
#--- Port E GPIO configuration / address space: 0x4800_1000 .. 0x4800_13FF
|
||||
|
||||
.equ GPIOE_BASE, GPIO_BASE + 0x1000
|
||||
|
||||
.equ GPIOE_MODER, GPIOE_BASE + GPIO_MODER_OFFSET
|
||||
.equ GPIOE_OTYPER, GPIOE_BASE + GPIO_OTYPER_OFFSET
|
||||
.equ GPIOE_OSPEEDR, GPIOE_BASE + GPIO_OSPEEDR_OFFSET
|
||||
.equ GPIOE_PUPDR, GPIOE_BASE + GPIO_PUPDR_OFFSET
|
||||
.equ GPIOE_IDR, GPIOE_BASE + GPIO_IDR_OFFSET
|
||||
.equ GPIOE_ODR, GPIOE_BASE + GPIO_ODR_OFFSET
|
||||
.equ GPIOE_BSRR, GPIOE_BASE + GPIO_BSRR_OFFSET
|
||||
.equ GPIOE_LCKR, GPIOE_BASE + GPIO_LCKR_OFFSET
|
||||
.equ GPIOE_AFRL, GPIOE_BASE + GPIO_AFRL_OFFSET
|
||||
.equ GPIOE_AFRH, GPIOE_BASE + GPIO_AFRH_OFFSET
|
||||
.equ GPIOE_BRR, GPIOE_BASE + GPIO_BRR_OFFSET
|
||||
|
||||
#--- Port F GPIO configuration / address space: 0x4800_1400 .. 0x4800_17FF
|
||||
|
||||
.equ GPIOF_BASE, GPIO_BASE + 0x1400
|
||||
|
||||
.equ GPIOF_MODER, GPIOF_BASE + GPIO_MODER_OFFSET
|
||||
.equ GPIOF_OTYPER, GPIOF_BASE + GPIO_OTYPER_OFFSET
|
||||
.equ GPIOF_OSPEEDR, GPIOF_BASE + GPIO_OSPEEDR_OFFSET
|
||||
.equ GPIOF_PUPDR, GPIOF_BASE + GPIO_PUPDR_OFFSET
|
||||
.equ GPIOF_IDR, GPIOF_BASE + GPIO_IDR_OFFSET
|
||||
.equ GPIOF_ODR, GPIOF_BASE + GPIO_ODR_OFFSET
|
||||
.equ GPIOF_BSRR, GPIOF_BASE + GPIO_BSRR_OFFSET
|
||||
.equ GPIOF_LCKR, GPIOF_BASE + GPIO_LCKR_OFFSET
|
||||
.equ GPIOF_AFRL, GPIOF_BASE + GPIO_AFRL_OFFSET
|
||||
.equ GPIOF_AFRH, GPIOF_BASE + GPIO_AFRH_OFFSET
|
||||
.equ GPIOF_BRR, GPIOF_BASE + GPIO_BRR_OFFSET
|
||||
|
||||
#--- Port G GPIO configuration / address space: 0x4800_1800 .. 0x4800_1BFF
|
||||
|
||||
.equ GPIOG_BASE, GPIO_BASE + 0x1800
|
||||
|
||||
.equ GPIOG_MODER, GPIOG_BASE + GPIO_MODER_OFFSET
|
||||
.equ GPIOG_OTYPER, GPIOG_BASE + GPIO_OTYPER_OFFSET
|
||||
.equ GPIOG_OSPEEDR, GPIOG_BASE + GPIO_OSPEEDR_OFFSET
|
||||
.equ GPIOG_PUPDR, GPIOG_BASE + GPIO_PUPDR_OFFSET
|
||||
.equ GPIOG_IDR, GPIOG_BASE + GPIO_IDR_OFFSET
|
||||
.equ GPIOG_ODR, GPIOG_BASE + GPIO_ODR_OFFSET
|
||||
.equ GPIOG_BSRR, GPIOG_BASE + GPIO_BSRR_OFFSET
|
||||
.equ GPIOG_LCKR, GPIOG_BASE + GPIO_LCKR_OFFSET
|
||||
.equ GPIOG_AFRL, GPIOG_BASE + GPIO_AFRL_OFFSET
|
||||
.equ GPIOG_AFRH, GPIOG_BASE + GPIO_AFRH_OFFSET
|
||||
.equ GPIOG_BRR, GPIOG_BASE + GPIO_BRR_OFFSET
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# System Control Space
|
||||
#
|
||||
# address space: 0xE000_E000 .. 0xE000_EFFF
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ SCS_BASE, PPB_BASE + 0xE000
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# System Timer (SysTick)
|
||||
#
|
||||
# address space: 0xE000_E010 .. 0xE000_E01F
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ STK_BASE, SCS_BASE + 10 // 0xE000_E010
|
||||
|
||||
.equ STK_CTRL, SCS_BASE + 0x00
|
||||
.equ STK_LOAD, SCS_BASE + 0x04
|
||||
.equ STK_VAL, SCS_BASE + 0x08
|
||||
.equ STK_CALIB, SCS_BASE + 0x0C
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# Nested Vector Interrupt Controller
|
||||
#
|
||||
# address space: 0xE000_E100 .. 0xE000_E4EF
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ NVIC_BASE, SCS_BASE + 0x100 // 0xE000_E100
|
||||
|
||||
.equ NVIC_ISER0, NVIC_BASE + 0x00
|
||||
.equ NVIC_ISER1, NVIC_BASE + 0x04
|
||||
.equ NVIC_ISER2, NVIC_BASE + 0x08
|
||||
.equ NVIC_ISER3, NVIC_BASE + 0x0C
|
||||
|
||||
.equ NVIC_ICER0, NVIC_BASE + 0x80
|
||||
.equ NVIC_ICER1, NVIC_BASE + 0x84
|
||||
.equ NVIC_ICER2, NVIC_BASE + 0x88
|
||||
.equ NVIC_ICER3, NVIC_BASE + 0x8C
|
||||
|
||||
.equ NVIC_ISPR0, NVIC_BASE + 0x100
|
||||
.equ NVIC_ISPR1, NVIC_BASE + 0x104
|
||||
.equ NVIC_ISPR2, NVIC_BASE + 0x108
|
||||
.equ NVIC_ISPR3, NVIC_BASE + 0x10C
|
||||
|
||||
.equ NVIC_ICPR0, NVIC_BASE + 0x180
|
||||
.equ NVIC_ICPR1, NVIC_BASE + 0x184
|
||||
.equ NVIC_ICPR2, NVIC_BASE + 0x188
|
||||
.equ NVIC_ICPR3, NVIC_BASE + 0x18C
|
||||
|
||||
.equ NVIC_IABR0, NVIC_BASE + 0x200
|
||||
.equ NVIC_IABR1, NVIC_BASE + 0x204
|
||||
.equ NVIC_IABR2, NVIC_BASE + 0x208
|
||||
.equ NVIC_IABR3, NVIC_BASE + 0x20C
|
||||
|
||||
.equ NVIC_IPR0, NVIC_BASE + 0x300
|
||||
.equ NVIC_IPR1, NVIC_BASE + 0x304
|
||||
.equ NVIC_IPR2, NVIC_BASE + 0x308
|
||||
.equ NVIC_IPR3, NVIC_BASE + 0x30C
|
||||
.equ NVIC_IPR4, NVIC_BASE + 0x310
|
||||
.equ NVIC_IPR5, NVIC_BASE + 0x314
|
||||
.equ NVIC_IPR6, NVIC_BASE + 0x318
|
||||
.equ NVIC_IPR7, NVIC_BASE + 0x31C
|
||||
.equ NVIC_IPR8, NVIC_BASE + 0x320
|
||||
.equ NVIC_IPR9, NVIC_BASE + 0x324
|
||||
.equ NVIC_IPR10, NVIC_BASE + 0x328
|
||||
.equ NVIC_IPR11, NVIC_BASE + 0x32C
|
||||
.equ NVIC_IPR12, NVIC_BASE + 0x330
|
||||
.equ NVIC_IPR13, NVIC_BASE + 0x334
|
||||
.equ NVIC_IPR14, NVIC_BASE + 0x338
|
||||
.equ NVIC_IPR15, NVIC_BASE + 0x33C
|
||||
.equ NVIC_IPR16, NVIC_BASE + 0x340
|
||||
.equ NVIC_IPR17, NVIC_BASE + 0x344
|
||||
.equ NVIC_IPR18, NVIC_BASE + 0x348
|
||||
.equ NVIC_IPR19, NVIC_BASE + 0x34C
|
||||
.equ NVIC_IPR20, NVIC_BASE + 0x350
|
||||
.equ NVIC_IPR21, NVIC_BASE + 0x354
|
||||
.equ NVIC_IPR22, NVIC_BASE + 0x358
|
||||
.equ NVIC_IPR23, NVIC_BASE + 0x35C
|
||||
.equ NVIC_IPR24, NVIC_BASE + 0x360
|
||||
.equ NVIC_IPR25, NVIC_BASE + 0x364
|
||||
|
||||
.equ STIR, NVIC_BASE + 0xE00
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
# MCU Debug Component
|
||||
#
|
||||
# address space: 0xE004_2000 .. 0xE004_2013
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.equ DBGMCU_BASE, PPB_BASE + 0x42000
|
||||
|
||||
.equ DBGMCU_IDCODE, DBGMCU_BASE + 0x00
|
||||
.equ DBGMCU_CR, DBGMCU_BASE + 0x04
|
||||
.equ DBGMCU_APB1FZR1, DBGMCU_BASE + 0x08
|
||||
.equ DBGMCU_APB1FZR2, DBGMCU_BASE + 0x0C
|
||||
.equ DBGMCU_APB2DZR, DBGMCU_BASE + 0x10
|
||||
@ -0,0 +1,36 @@
|
||||
/*
|
||||
* sketch.c
|
||||
*
|
||||
* Created on: Mar 18, 2026
|
||||
* Author: tobii
|
||||
*/
|
||||
int reihenfolge[6] = {0, 1, 2, 3, 2, 1};
|
||||
|
||||
int main(){
|
||||
while(1){
|
||||
while(/*schalter nicht gedrückt*/){}
|
||||
delay(10);
|
||||
while(/*schalter losgelassen*/){}
|
||||
delay(150);
|
||||
|
||||
int aktiv = 1;
|
||||
while(aktiv){
|
||||
for(int i; i < reihenfolge.length - 1 && aktiv = 1; i ++){
|
||||
//alle LED einschalten
|
||||
if(i = 0){/*alles bis auf LED0 auschalten*/}
|
||||
if(i = 1){/*..*/}
|
||||
//...
|
||||
for(int zähler = 0; zähler < 333 && aktiv == 1; zähler++){
|
||||
if(/*schalter gerückt*/){
|
||||
aktiv = 0;
|
||||
break;
|
||||
}
|
||||
else{
|
||||
delay(1);
|
||||
}
|
||||
}
|
||||
while(/*Taster gedrückt*/){}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
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Binary file not shown.
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Binary file not shown.
Binary file not shown.
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Binary file not shown.
BIN
.metadata/.plugins/org.eclipse.core.resources/69.snap
Normal file
BIN
.metadata/.plugins/org.eclipse.core.resources/69.snap
Normal file
Binary file not shown.
File diff suppressed because one or more lines are too long
@ -0,0 +1,4 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<session version="1.0">
|
||||
<refactoring comment="Delete resource 'task2/task2_tobi.s'" deleteContents="false" description="Delete resource 'task2/task2_tobi.s'" element1="/task2/task2_tobi.s" flags="7" id="org.eclipse.ltk.core.refactoring.delete.resources" resources="1" stamp="1774360637158"/>
|
||||
</session>
|
||||
@ -0,0 +1 @@
|
||||
1774360637158 Delete resource 'task2/task2_tobi.s'
|
||||
@ -17,7 +17,7 @@
|
||||
<section name="CleanDialogSettings">
|
||||
<item key="BUILD_NOW" value="false"/>
|
||||
<item key="BUILD_ALL" value="true"/>
|
||||
<item key="TOGGLE_SELECTED" value="false"/>
|
||||
<item key="TOGGLE_SELECTED" value="true"/>
|
||||
<item key="DIALOG_WIDTH" value="731"/>
|
||||
<item key="DIALOG_HEIGHT" value="569"/>
|
||||
<item key="DIALOG_FONT_NAME" value="1|Noto Sans|10.0|0|GTK|1|"/>
|
||||
|
||||
@ -1,3 +1,3 @@
|
||||
#Tue Mar 24 14:11:27 CET 2026
|
||||
#Tue Mar 31 13:41:52 CEST 2026
|
||||
org.eclipse.core.runtime=2
|
||||
org.eclipse.platform=4.30.0.v20231201-0110
|
||||
|
||||
0
task1/Debug/Src/sketch.cyclo
Normal file
0
task1/Debug/Src/sketch.cyclo
Normal file
1
task1/Debug/Src/sketch.d
Normal file
1
task1/Debug/Src/sketch.d
Normal file
@ -0,0 +1 @@
|
||||
Src/sketch.o: ../Src/sketch.c
|
||||
BIN
task1/Debug/Src/sketch.o
Normal file
BIN
task1/Debug/Src/sketch.o
Normal file
Binary file not shown.
0
task1/Debug/Src/sketch.su
Normal file
0
task1/Debug/Src/sketch.su
Normal file
@ -5,14 +5,17 @@
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
C_SRCS += \
|
||||
../Src/sketch.c \
|
||||
../Src/task1.c \
|
||||
../Src/task1_it.c
|
||||
|
||||
OBJS += \
|
||||
./Src/sketch.o \
|
||||
./Src/task1.o \
|
||||
./Src/task1_it.o
|
||||
|
||||
C_DEPS += \
|
||||
./Src/sketch.d \
|
||||
./Src/task1.d \
|
||||
./Src/task1_it.d
|
||||
|
||||
@ -24,7 +27,7 @@ Src/%.o Src/%.su Src/%.cyclo: ../Src/%.c Src/subdir.mk
|
||||
clean: clean-Src
|
||||
|
||||
clean-Src:
|
||||
-$(RM) ./Src/task1.cyclo ./Src/task1.d ./Src/task1.o ./Src/task1.su ./Src/task1_it.cyclo ./Src/task1_it.d ./Src/task1_it.o ./Src/task1_it.su
|
||||
-$(RM) ./Src/sketch.cyclo ./Src/sketch.d ./Src/sketch.o ./Src/sketch.su ./Src/task1.cyclo ./Src/task1.d ./Src/task1.o ./Src/task1.su ./Src/task1_it.cyclo ./Src/task1_it.d ./Src/task1_it.o ./Src/task1_it.su
|
||||
|
||||
.PHONY: clean-Src
|
||||
|
||||
|
||||
0
task1/Debug/Src/task1.cyclo
Normal file
0
task1/Debug/Src/task1.cyclo
Normal file
11
task1/Debug/Src/task1.d
Normal file
11
task1/Debug/Src/task1.d
Normal file
@ -0,0 +1,11 @@
|
||||
Src/task1.o: ../Src/task1.c ../Inc/stm32g431xx.h ../Inc/core_cm4.h \
|
||||
../Inc/cmsis_version.h ../Inc/cmsis_compiler.h ../Inc/cmsis_gcc.h \
|
||||
../Inc/mpu_armv7.h ../Inc/system_stm32g4xx.h ../Inc/STefi-Light.h
|
||||
../Inc/stm32g431xx.h:
|
||||
../Inc/core_cm4.h:
|
||||
../Inc/cmsis_version.h:
|
||||
../Inc/cmsis_compiler.h:
|
||||
../Inc/cmsis_gcc.h:
|
||||
../Inc/mpu_armv7.h:
|
||||
../Inc/system_stm32g4xx.h:
|
||||
../Inc/STefi-Light.h:
|
||||
0
task1/Debug/Src/task1.su
Normal file
0
task1/Debug/Src/task1.su
Normal file
2
task1/Debug/Src/task1_it.cyclo
Normal file
2
task1/Debug/Src/task1_it.cyclo
Normal file
@ -0,0 +1,2 @@
|
||||
../Src/task1_it.c:56:6:ISR_error 1
|
||||
../Src/task1_it.c:76:6:ISR_default 1
|
||||
11
task1/Debug/Src/task1_it.d
Normal file
11
task1/Debug/Src/task1_it.d
Normal file
@ -0,0 +1,11 @@
|
||||
Src/task1_it.o: ../Src/task1_it.c ../Inc/stm32g431xx.h ../Inc/core_cm4.h \
|
||||
../Inc/cmsis_version.h ../Inc/cmsis_compiler.h ../Inc/cmsis_gcc.h \
|
||||
../Inc/mpu_armv7.h ../Inc/system_stm32g4xx.h ../Inc/STefi-Light.h
|
||||
../Inc/stm32g431xx.h:
|
||||
../Inc/core_cm4.h:
|
||||
../Inc/cmsis_version.h:
|
||||
../Inc/cmsis_compiler.h:
|
||||
../Inc/cmsis_gcc.h:
|
||||
../Inc/mpu_armv7.h:
|
||||
../Inc/system_stm32g4xx.h:
|
||||
../Inc/STefi-Light.h:
|
||||
BIN
task1/Debug/Src/task1_it.o
Normal file
BIN
task1/Debug/Src/task1_it.o
Normal file
Binary file not shown.
2
task1/Debug/Src/task1_it.su
Normal file
2
task1/Debug/Src/task1_it.su
Normal file
@ -0,0 +1,2 @@
|
||||
../Src/task1_it.c:56:6:ISR_error 4 static
|
||||
../Src/task1_it.c:76:6:ISR_default 4 static
|
||||
1
task1/Debug/Startup/startup_stm32g431kbtx.d
Normal file
1
task1/Debug/Startup/startup_stm32g431kbtx.d
Normal file
@ -0,0 +1 @@
|
||||
Startup/startup_stm32g431kbtx.o: ../Startup/startup_stm32g431kbtx.s
|
||||
BIN
task1/Debug/Startup/startup_stm32g431kbtx.o
Normal file
BIN
task1/Debug/Startup/startup_stm32g431kbtx.o
Normal file
Binary file not shown.
18
task1/Debug/Startup/syscalls.cyclo
Normal file
18
task1/Debug/Startup/syscalls.cyclo
Normal file
@ -0,0 +1,18 @@
|
||||
../Startup/syscalls.c:44:6:initialise_monitor_handles 1
|
||||
../Startup/syscalls.c:48:5:_getpid 1
|
||||
../Startup/syscalls.c:53:5:_kill 1
|
||||
../Startup/syscalls.c:61:6:_exit 1
|
||||
../Startup/syscalls.c:67:27:_read 2
|
||||
../Startup/syscalls.c:80:27:_write 2
|
||||
../Startup/syscalls.c:92:5:_close 1
|
||||
../Startup/syscalls.c:99:5:_fstat 1
|
||||
../Startup/syscalls.c:106:5:_isatty 1
|
||||
../Startup/syscalls.c:112:5:_lseek 1
|
||||
../Startup/syscalls.c:120:5:_open 1
|
||||
../Startup/syscalls.c:128:5:_wait 1
|
||||
../Startup/syscalls.c:135:5:_unlink 1
|
||||
../Startup/syscalls.c:142:5:_times 1
|
||||
../Startup/syscalls.c:148:5:_stat 1
|
||||
../Startup/syscalls.c:155:5:_link 1
|
||||
../Startup/syscalls.c:163:5:_fork 1
|
||||
../Startup/syscalls.c:169:5:_execve 1
|
||||
1
task1/Debug/Startup/syscalls.d
Normal file
1
task1/Debug/Startup/syscalls.d
Normal file
@ -0,0 +1 @@
|
||||
Startup/syscalls.o: ../Startup/syscalls.c
|
||||
BIN
task1/Debug/Startup/syscalls.o
Normal file
BIN
task1/Debug/Startup/syscalls.o
Normal file
Binary file not shown.
18
task1/Debug/Startup/syscalls.su
Normal file
18
task1/Debug/Startup/syscalls.su
Normal file
@ -0,0 +1,18 @@
|
||||
../Startup/syscalls.c:44:6:initialise_monitor_handles 4 static
|
||||
../Startup/syscalls.c:48:5:_getpid 4 static
|
||||
../Startup/syscalls.c:53:5:_kill 16 static
|
||||
../Startup/syscalls.c:61:6:_exit 16 static
|
||||
../Startup/syscalls.c:67:27:_read 32 static
|
||||
../Startup/syscalls.c:80:27:_write 32 static
|
||||
../Startup/syscalls.c:92:5:_close 16 static
|
||||
../Startup/syscalls.c:99:5:_fstat 16 static
|
||||
../Startup/syscalls.c:106:5:_isatty 16 static
|
||||
../Startup/syscalls.c:112:5:_lseek 24 static
|
||||
../Startup/syscalls.c:120:5:_open 12 static
|
||||
../Startup/syscalls.c:128:5:_wait 16 static
|
||||
../Startup/syscalls.c:135:5:_unlink 16 static
|
||||
../Startup/syscalls.c:142:5:_times 16 static
|
||||
../Startup/syscalls.c:148:5:_stat 16 static
|
||||
../Startup/syscalls.c:155:5:_link 16 static
|
||||
../Startup/syscalls.c:163:5:_fork 8 static
|
||||
../Startup/syscalls.c:169:5:_execve 24 static
|
||||
1
task1/Debug/Startup/sysmem.cyclo
Normal file
1
task1/Debug/Startup/sysmem.cyclo
Normal file
@ -0,0 +1 @@
|
||||
../Startup/sysmem.c:53:7:_sbrk 3
|
||||
1
task1/Debug/Startup/sysmem.d
Normal file
1
task1/Debug/Startup/sysmem.d
Normal file
@ -0,0 +1 @@
|
||||
Startup/sysmem.o: ../Startup/sysmem.c
|
||||
BIN
task1/Debug/Startup/sysmem.o
Normal file
BIN
task1/Debug/Startup/sysmem.o
Normal file
Binary file not shown.
1
task1/Debug/Startup/sysmem.su
Normal file
1
task1/Debug/Startup/sysmem.su
Normal file
@ -0,0 +1 @@
|
||||
../Startup/sysmem.c:53:7:_sbrk 32 static
|
||||
@ -1,3 +1,4 @@
|
||||
"./Src/sketch.o"
|
||||
"./Src/task1.o"
|
||||
"./Src/task1_it.o"
|
||||
"./Startup/startup_stm32g431kbtx.o"
|
||||
|
||||
@ -172,6 +172,23 @@
|
||||
#--- Genral Purpose Timer - TIM3 / address space: 0x4000_0400 .. 0x4000_07FF
|
||||
|
||||
.equ TIM3_BASE, APB1_BASE + 0x400
|
||||
sketch.c
|
||||
*
|
||||
* Created on: Mar 18, 2026
|
||||
* Author: tobii
|
||||
*/
|
||||
int reihenfolge[6] = {0, 1, 2, 3, 2, 1};
|
||||
|
||||
int main(){
|
||||
while(1){
|
||||
while(/*schalter nicht gedrückt*/){}
|
||||
delay(10);
|
||||
while(/*schalter losgelassen*/){}
|
||||
delay(150);
|
||||
|
||||
int aktiv = 1;
|
||||
while(aktiv){
|
||||
for(int i; i < reihenfolge.length - 1 && aktiv = 1; i ++){
|
||||
|
||||
.equ TIM3_CR1, TIM3_BASE + TIM_CR1_OFFSET
|
||||
.equ TIM3_CR2, TIM3_BASE + TIM_CR2_OFFSET
|
||||
|
||||
672
task2/task2.als
672
task2/task2.als
@ -4,49 +4,16 @@
|
||||
input file : task2.s
|
||||
output file : task2.o
|
||||
target : arm-none-eabi
|
||||
time stamp : 2026-03-24T14:14:11.000+0100
|
||||
time stamp : 2026-03-31T13:53:51.000+0200
|
||||
|
||||
1 #****************************************************************************************#
|
||||
2 # Project: task2 - ASM: Interrupts
|
||||
3 # File: task2.s
|
||||
4 #
|
||||
5 # Language: ASM
|
||||
6 #
|
||||
7 # Hardware: STefi Light v1.1
|
||||
8 # Processor: STM32G431KBT6U
|
||||
9 #
|
||||
10 # Author: Manuel Lederhofer
|
||||
11 # Datum: 31.10.2014
|
||||
12 #
|
||||
13 # Version: 6.0
|
||||
14 # History:
|
||||
15 # 31.10.2014 ML create file
|
||||
16 # 27.09.2018 ML edit comments, extend vector table
|
||||
17 # 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
|
||||
18 # 27.02.2019 ML move section of exception handlers to bottom of file
|
||||
19 # 25.09.2019 ML minor changes for a better code and comment understanding
|
||||
20 # 04.09.2020 HL port from STM32L476RG to STM32F411xE
|
||||
21 # 21.09.2020 ML tidy up, comments and formatting
|
||||
22 # 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
|
||||
23 # 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
|
||||
24 # 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
|
||||
25 # 24.06.2025 TK remove /* ... place your code here ... */
|
||||
26 #
|
||||
27 # Status: working
|
||||
28 #
|
||||
29 # Description:
|
||||
30 # See the description and requirements of the requested application
|
||||
31 # in the lab exercise guide.
|
||||
32 #
|
||||
33 # Notes:
|
||||
34 # - MCU speed at startup is 16 MHz
|
||||
35 #
|
||||
36 # ToDo:
|
||||
37 # - Change the example code to match the description and requirements
|
||||
38 # of the requested application in the lab exercise guide.
|
||||
39 #****************************************************************************************#
|
||||
40
|
||||
41 .include "G431_addr.s"
|
||||
4 # Hardware: STefi Light v1.1
|
||||
5 # Processor: STM32G431KBT6U
|
||||
6 #****************************************************************************************#
|
||||
7
|
||||
8 .include "G431_addr.s"
|
||||
1 #*****************************************************************************************
|
||||
2 # Project: task2 - switch triggered LEDs
|
||||
3 # File: G431_addr.s
|
||||
@ -811,286 +778,351 @@
|
||||
762 .equ DBGMCU_APB1FZR1, DBGMCU_BASE + 0x08
|
||||
763 .equ DBGMCU_APB1FZR2, DBGMCU_BASE + 0x0C
|
||||
764 .equ DBGMCU_APB2DZR, DBGMCU_BASE + 0x10
|
||||
42
|
||||
43
|
||||
44 #----------------------------------------------------------------------------------------#
|
||||
45 .section .vectortable,"a" // vector table at begin of ROM
|
||||
46 #----------------------------------------------------------------------------------------#
|
||||
9
|
||||
10 // Falls in G431_addr.s vorhanden, diesen Block löschen um Fehler zu vermeiden:
|
||||
11 .equ RCC_AHB2ENR, 0x4002104C
|
||||
12 .equ RCC_APB2ENR, 0x40021060
|
||||
13
|
||||
14 .equ GPIOA_MODER, 0x48000000
|
||||
15 .equ GPIOA_ODR, 0x48000014
|
||||
16
|
||||
17 .equ GPIOB_MODER, 0x48000400
|
||||
18 .equ GPIOB_PUPDR, 0x4800040C
|
||||
19 .equ GPIOB_IDR, 0x48000410
|
||||
20
|
||||
21 .equ SYSCFG_BASE, 0x40010000
|
||||
22 .equ SYSCFG_EXTICR1, (SYSCFG_BASE + 0x08)
|
||||
23 .equ SYSCFG_EXTICR2, (SYSCFG_BASE + 0x0C)
|
||||
24
|
||||
25 .equ EXTI_BASE, 0x40010400
|
||||
26 .equ EXTI_IMR1, (EXTI_BASE + 0x00)
|
||||
27 .equ EXTI_FTSR1, (EXTI_BASE + 0x0C)
|
||||
28 .equ EXTI_PR1, (EXTI_BASE + 0x14)
|
||||
29
|
||||
30 .equ NVIC_ISER0, 0xE000E100
|
||||
31
|
||||
32 .equ DBGMCU_CR, 0xE0042004 // Adresse des Debug Configuration Registers
|
||||
33
|
||||
34 #----------------------------------------------------------------------------------------#
|
||||
35 .section .vectortable,"a"
|
||||
36 #----------------------------------------------------------------------------------------#
|
||||
37
|
||||
38 .align 2
|
||||
39
|
||||
40 0000 00400020 .word 0x20004000 // initial Stack Pointer
|
||||
41 0004 00000000 .word init // initial Program Counter
|
||||
42 0008 00000000 .word _ISR_NMI // non-masking interrupt
|
||||
43 000c 00000000 .word _ISR_HARDF // hard fault interrupt
|
||||
44
|
||||
45 0010 00000000 .space 0x48 // Padding 72 Bytes (Offset 0x10 -> 0x58)
|
||||
45 00000000
|
||||
45 00000000
|
||||
45 00000000
|
||||
45 00000000
|
||||
46 0058 00000000 .word _ISR_EXTI0 // EXTI0_IRQHandler (PB0 / S0) - IRQ 6
|
||||
47
|
||||
48 .align 2
|
||||
49
|
||||
50 0000 00400020 .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRA
|
||||
51 0004 01040008 .word 0x08000401 // initial Program Counter
|
||||
52 0008 00000000 .word _ISR_NMI // non-masking interrupt
|
||||
53 000c 00000000 .word _ISR_HARDF // hard fault interrupt
|
||||
48 005c 00000000 .space 0x0C // Padding 12 Bytes (Offset 0x5C -> 0x68)
|
||||
48 00000000
|
||||
48 00000000
|
||||
49 0068 00000000 .word _ISR_EXTI4 // EXTI4_IRQHandler (PB4 / S1) - IRQ 10
|
||||
50
|
||||
51 #----------------------------------------------------------------------------------------#
|
||||
52 .text
|
||||
53 #----------------------------------------------------------------------------------------#
|
||||
54
|
||||
55
|
||||
56
|
||||
57 /* N.B.
|
||||
58 Look at the .space or the .org assembler directive to insert the address of the
|
||||
59 ISRs at the right place in the vector table. Verify your settings by the help of
|
||||
60 the list file. */
|
||||
61
|
||||
62 0010 00000000 .word _ISR_S0
|
||||
55 .align 2
|
||||
56 .syntax unified
|
||||
57 .thumb
|
||||
58 .thumb_func
|
||||
59 .global init
|
||||
61 init:
|
||||
62 0000 72B6 CPSID i
|
||||
63
|
||||
64
|
||||
65 #----------------------------------------------------------------------------------------#
|
||||
66 .text // section .text (default section for program code)
|
||||
67 #----------------------------------------------------------------------------------------#
|
||||
68
|
||||
69 .align 2
|
||||
70 .syntax unified
|
||||
71 .thumb
|
||||
72 .thumb_func
|
||||
73 .global init
|
||||
75 init:
|
||||
76 0000 72B6 CPSID i // disable interrupts globally
|
||||
64 0002 0020 MOVS r0, #0
|
||||
65 0004 0021 MOVS r1, #0
|
||||
66 0006 0022 MOVS r2, #0
|
||||
67 0008 0023 MOVS r3, #0
|
||||
68 000a 0024 MOVS r4, #0
|
||||
69 000c 0025 MOVS r5, #0
|
||||
70 000e 0026 MOVS r6, #0
|
||||
71 0010 0027 MOVS r7, #0
|
||||
72 0012 8046 MOV r8, r0
|
||||
73 0014 8146 MOV r9, r0
|
||||
74 0016 8246 MOV r10, r0
|
||||
75 0018 8346 MOV r11, r0
|
||||
76 001a 8446 MOV r12, r0
|
||||
77
|
||||
78 0002 0020 MOVS r0, #0 // safely initialize the GPRs
|
||||
79 0004 0021 MOVS r1, #0
|
||||
80 0006 0022 MOVS r2, #0
|
||||
81 0008 0023 MOVS r3, #0
|
||||
82 000a 0024 MOVS r4, #0
|
||||
83 000c 0025 MOVS r5, #0
|
||||
84 000e 0026 MOVS r6, #0
|
||||
85 0010 0027 MOVS r7, #0
|
||||
86 0012 8046 MOV r8, r0
|
||||
87 0014 8146 MOV r9, r0
|
||||
88 0016 8246 MOV r10, r0
|
||||
89 0018 8346 MOV r11, r0
|
||||
90 001a 8446 MOV r12, r0
|
||||
91
|
||||
92 #--- enable port clocking
|
||||
93 001c 1249 LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
|
||||
94 001e 4FF00102 MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
|
||||
95 0022 0868 LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
|
||||
96 0024 1043 ORRS r0, r0, r2 // configure clock gating for ports
|
||||
97 0026 0860 STR r0, [r1, #0] // apply settings
|
||||
98
|
||||
99 #--- port init
|
||||
100 #- LEDs
|
||||
101 0028 4FF09041 LDR r1, =GPIOA_MODER // load port A mode register address
|
||||
102 002c 0322 MOVS r2, #0x03 // prepare mask
|
||||
103 002e 0868 LDR r0, [r1, #0] // get current value of port A mode register
|
||||
104 0030 9043 BICS r0, r2 // delete bits
|
||||
105 0032 0122 MOVS r2, #0x01 // load configuration mask
|
||||
106 0034 1043 ORRS r0, r0, r2 // apply mask
|
||||
107 0036 0860 STR r0, [r1, #0] // apply result to port A mode register
|
||||
78 #--- enable port clocking (GPIOA, GPIOB)
|
||||
79 001c 2C49 LDR r1, =RCC_AHB2ENR
|
||||
80 001e 0322 MOVS r2, #0x03 // Bit 0 (GPIOA) und Bit 1 (GPIOB)
|
||||
81 0020 0868 LDR r0, [r1, #0]
|
||||
82 0022 1043 ORRS r0, r2
|
||||
83 0024 0860 STR r0, [r1, #0]
|
||||
84
|
||||
85 #--- port init
|
||||
86 #- LEDs (PA0 - PA3) als Output
|
||||
87 0026 4FF09041 LDR r1, =GPIOA_MODER
|
||||
88 002a 4FF0FF02 LDR r2, =0x000000FF
|
||||
89 002e 0868 LDR r0, [r1, #0]
|
||||
90 0030 9043 BICS r0, r2
|
||||
91 0032 4FF05502 LDR r2, =0x00000055
|
||||
92 0036 1043 ORRS r0, r2
|
||||
93 0038 0860 STR r0, [r1, #0]
|
||||
94
|
||||
95 #- switch LED off
|
||||
96 003a 2649 LDR r1, =GPIOA_ODR
|
||||
97 003c 0F22 MOVS r2, #0x0F
|
||||
98 003e 0868 LDR r0, [r1, #0]
|
||||
99 0040 1043 ORRS r0, r2
|
||||
100 0042 0860 STR r0, [r1, #0]
|
||||
101
|
||||
102 #- buttons (PB0, PB4) als Input
|
||||
103 0044 2449 LDR r1, =GPIOB_MODER
|
||||
104 0046 40F20332 LDR r2, =0x00000303 // Maske Bits 0:1 (PB0) und 8:9 (PB4)
|
||||
105 004a 0868 LDR r0, [r1, #0]
|
||||
106 004c 9043 BICS r0, r2
|
||||
107 004e 0860 STR r0, [r1, #0]
|
||||
108
|
||||
109 # LDR r1, =GPIOB_MODER
|
||||
110 # MOVS r3, #0x03
|
||||
111 # LDR r0, [r1, #1]
|
||||
112 # BICS r0, r3
|
||||
113 # MOVS r3, #0x01
|
||||
114 # ORRS r0, r0, r3
|
||||
115 # STR r0, [r1, #1]
|
||||
116
|
||||
117 #- switch LED off
|
||||
118 0038 0C49 LDR r1, =GPIOA_ODR // load port A output data register
|
||||
119 003a 0122 MOVS r2, #0x01 // load mask for LED
|
||||
120 003c 0868 LDR r0, [r1, #0] // get current value of GPIOA
|
||||
121 003e 1043 ORRS r0, r0, r2 // configure pin state
|
||||
122 0040 0860 STR r0, [r1, #0] // apply settings
|
||||
123
|
||||
124 #- buttons
|
||||
125
|
||||
126 /* ... place your code here ... */
|
||||
127
|
||||
128
|
||||
129 #--- button interrupt config
|
||||
130
|
||||
131 #- enable clock for SYSCFG module
|
||||
132
|
||||
133
|
||||
134 #- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
|
||||
135 # in SYSCFG module (SYSCFG_* registers)
|
||||
136
|
||||
137
|
||||
138
|
||||
139
|
||||
140 #- configure lines in EXTI module (EXTI_* registers)
|
||||
141
|
||||
142
|
||||
109 #- Pull-Up für PB0, PB4
|
||||
110 0050 2249 LDR r1, =GPIOB_PUPDR
|
||||
111 0052 40F20332 LDR r2, =0x00000303
|
||||
112 0056 0868 LDR r0, [r1, #0]
|
||||
113 0058 9043 BICS r0, r2
|
||||
114 005a 40F20112 LDR r2, =0x00000101 // 01 = Pull-Up für PB0 und PB4
|
||||
115 005e 1043 ORRS r0, r2
|
||||
116 0060 0860 STR r0, [r1, #0]
|
||||
117
|
||||
118 #--- button interrupt config
|
||||
119
|
||||
120 #- enable clock for SYSCFG module
|
||||
121 0062 1F49 LDR r1, =RCC_APB2ENR
|
||||
122 0064 0122 MOVS r2, #0x01
|
||||
123 0066 0868 LDR r0, [r1, #0]
|
||||
124 0068 1043 ORRS r0, r2
|
||||
125 006a 0860 STR r0, [r1, #0]
|
||||
126
|
||||
127 #- connect GPIO pins to EXTI lines
|
||||
128 006c 1D49 LDR r1, =SYSCFG_EXTICR1 // EXTI0 (PB0)
|
||||
129 006e 4FF00F02 LDR r2, =0x000F // Maske EXTI0 (Bits 3:0)
|
||||
130 0072 0868 LDR r0, [r1, #0]
|
||||
131 0074 9043 BICS r0, r2
|
||||
132 0076 0122 MOVS r2, #0x0001 // Port B (0001)
|
||||
133 0078 1043 ORRS r0, r2
|
||||
134 007a 0860 STR r0, [r1, #0]
|
||||
135
|
||||
136 007c 1A49 LDR r1, =SYSCFG_EXTICR2 // EXTI4 (PB4)
|
||||
137 007e 4FF00F02 LDR r2, =0x000F // Maske EXTI4 (Bits 3:0)
|
||||
138 0082 0868 LDR r0, [r1, #0]
|
||||
139 0084 9043 BICS r0, r2
|
||||
140 0086 0122 MOVS r2, #0x0001 // Port B (0001)
|
||||
141 0088 1043 ORRS r0, r2
|
||||
142 008a 0860 STR r0, [r1, #0]
|
||||
143
|
||||
144 #- NVIC: set interrupt priority, clear pending bits
|
||||
145 # and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
|
||||
146
|
||||
147
|
||||
148
|
||||
149 0042 62B6 CPSIE i // enable interrupts globally
|
||||
144 #- configure EXTI lines (falling edge, unmask)
|
||||
145 008c 1749 LDR r1, =EXTI_FTSR1
|
||||
146 008e 1122 MOVS r2, #0x11 // Bit 0 (EXTI0) und Bit 4 (EXTI4)
|
||||
147 0090 0868 LDR r0, [r1, #0]
|
||||
148 0092 1043 ORRS r0, r2
|
||||
149 0094 0860 STR r0, [r1, #0]
|
||||
150
|
||||
151
|
||||
152 #----------------------------------------------------------------------------------------#
|
||||
153
|
||||
154 .align 2
|
||||
155 .syntax unified
|
||||
156 .thumb
|
||||
157 .thumb_func
|
||||
158 .global main
|
||||
160 main:
|
||||
161 0044 0949 LDR r1, =GPIOA_ODR
|
||||
162 0046 5040 EORS r0, r0, r2
|
||||
151 0096 1649 LDR r1, =EXTI_IMR1
|
||||
152 0098 1122 MOVS r2, #0x11 // Bit 0 und Bit 4
|
||||
153 009a 0868 LDR r0, [r1, #0]
|
||||
154 009c 1043 ORRS r0, r2
|
||||
155 009e 0860 STR r0, [r1, #0]
|
||||
156
|
||||
157 #- NVIC: enable interrupts EXTI0 (IRQ 6) & EXTI4 (IRQ 10)
|
||||
158 00a0 1449 LDR r1, =NVIC_ISER0
|
||||
159 00a2 4FF48862 LDR r2, =0x00000440 // Bit 6 (EXTI0) und Bit 10 (EXTI4)
|
||||
160 00a6 0868 LDR r0, [r1, #0]
|
||||
161 00a8 1043 ORRS r0, r2
|
||||
162 00aa 0860 STR r0, [r1, #0]
|
||||
163
|
||||
164 0048 0860 STR r0, [r1, #0]
|
||||
165
|
||||
166
|
||||
167
|
||||
168 004a FFF7FEFF BL delay
|
||||
169
|
||||
164 #--- wachhalten während WFI
|
||||
165 00ac 1249 LDR r1, =DBGMCU_CR
|
||||
166 00ae 0868 LDR r0, [r1, #0]
|
||||
167 00b0 0722 MOVS r2, #0x07 // Setzt DBG_SLEEP, DBG_STOP und DBG_STANDBY Bits
|
||||
168 00b2 1043 ORRS r0, r2
|
||||
169 00b4 0860 STR r0, [r1, #0]
|
||||
170
|
||||
171 004e FFF7FEBF B main
|
||||
171 00b6 62B6 CPSIE i
|
||||
172
|
||||
173
|
||||
174 #----------------------------------------------------------------------------------------#
|
||||
175
|
||||
176 0052 00BF .align 2
|
||||
177 .syntax unified
|
||||
178 .thumb
|
||||
179 .thumb_func
|
||||
180 .global delay
|
||||
182 delay:
|
||||
183 0054 0026 MOVS r6, #0 // ...
|
||||
184 0056 064F LDR r7, =2000000 // ...
|
||||
185 .L1:
|
||||
186 0058 0136 ADDS r6, r6, #1 // ...
|
||||
187 005a BE42 CMP r6, r7 // ...
|
||||
188 005c FCD1 BNE .L1 // ...
|
||||
189 005e 7047 BX lr // ...
|
||||
190
|
||||
191
|
||||
192 #----------------------------------------------------------------------------------------#
|
||||
193
|
||||
194 .align 2
|
||||
195 .global stop
|
||||
196 stop:
|
||||
197 0060 00BF NOP // do nothing (NOP is here to avoid a debugger crash, only)
|
||||
198 0062 FFF7FEBF B stop // if this line is reached, something went wrong
|
||||
173 #----------------------------------------------------------------------------------------#
|
||||
174
|
||||
175 .align 2
|
||||
176 .syntax unified
|
||||
177 .thumb
|
||||
178 .thumb_func
|
||||
179 .global main
|
||||
181 main:
|
||||
182 00b8 30BF WFI
|
||||
183 00ba FFF7FEBF B main
|
||||
184
|
||||
185 #----------------------------------------------------------------------------------------#
|
||||
186
|
||||
187 00be 00BF .align 2
|
||||
188 .syntax unified
|
||||
189 .thumb
|
||||
190 .thumb_func
|
||||
191 .global delay
|
||||
193 delay:
|
||||
194 00c0 0E48 LDR r0, =106000
|
||||
195 .L1:
|
||||
196 00c2 0138 SUBS r0, r0, #1
|
||||
197 00c4 FDD1 BNE .L1
|
||||
198 00c6 7047 BX lr
|
||||
199
|
||||
200
|
||||
201 #----------------------------------------------------------------------------------------#
|
||||
202 .lp1: // this label is only to nicify the line up in the .lst file
|
||||
203 0066 00004C10 .ltorg
|
||||
203 02401400
|
||||
203 00488084
|
||||
203 1E00
|
||||
204 #----------------------------------------------------------------------------------------#
|
||||
205
|
||||
206
|
||||
207 #----------------------------------------------------------------------------------------#
|
||||
208 .section .exhand,"ax" // section for exception handlers
|
||||
209 #----------------------------------------------------------------------------------------#
|
||||
210
|
||||
211 .align 2
|
||||
212 .syntax unified
|
||||
213 .thumb
|
||||
215 _ISR_NMI:
|
||||
216 #--- enable clock
|
||||
217 0000 1749 LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
|
||||
218 0002 4FF00102 MOV r2, #0x01 // load mask
|
||||
219 0006 0868 LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
|
||||
220 0008 1043 ORRS r0, r0, r2 // configure clock gating for port
|
||||
221 000a 0860 STR r0, [r1, #0] // apply settings
|
||||
222
|
||||
223 #--- init pins
|
||||
224 000c 4FF09041 LDR r1, =GPIOA_MODER // load port A mode register address
|
||||
225 0010 FF22 MOVS r2, #0xFF // prepare mask
|
||||
226 0012 0868 LDR r0, [r1, #0] // get current value of port A mode register
|
||||
227 0014 9043 BICS r0, r0, r2 // delete bits
|
||||
228 0016 4422 MOVS r2, #0x44 // load configuration mask
|
||||
229 0018 1043 ORRS r0, r0, r2 // configure pins
|
||||
230 001a 0860 STR r0, [r1, #0] // apply settings to port A mode register
|
||||
231
|
||||
232 #--- switch some LEDs on
|
||||
233 001c 1149 LDR r1, =GPIOA_ODR // load port A data output register address
|
||||
234 001e 0A22 MOVS r2, #0x0A // load mask for blue and yellow LED
|
||||
235 0020 0868 LDR r0, [r1, #0]
|
||||
236 0022 9043 BICS r0, r0, r2
|
||||
237 0024 0860 STR r0, [r1, #0] // switch LEDs on
|
||||
238
|
||||
239 0026 EBE7 B _ISR_NMI
|
||||
240
|
||||
200 #----------------------------------------------------------------------------------------#
|
||||
201
|
||||
202 .align 2
|
||||
203 .global stop
|
||||
204 stop:
|
||||
205 00c8 00BF NOP
|
||||
206 00ca FFF7FEBF B stop
|
||||
207
|
||||
208 #----------------------------------------------------------------------------------------#
|
||||
209 .lp1:
|
||||
210 00ce 00004C10 .ltorg
|
||||
210 02401400
|
||||
210 00480004
|
||||
210 00480C04
|
||||
210 00486010
|
||||
211 #----------------------------------------------------------------------------------------#
|
||||
212
|
||||
213 #----------------------------------------------------------------------------------------#
|
||||
214 .section .exhand,"ax"
|
||||
215 #----------------------------------------------------------------------------------------#
|
||||
216
|
||||
217 .align 2
|
||||
218 .syntax unified
|
||||
219 .thumb
|
||||
221 _ISR_NMI:
|
||||
222 0000 2549 LDR r1, =RCC_AHB2ENR
|
||||
223 0002 4FF00102 MOV r2, #0x01
|
||||
224 0006 0868 LDR r0, [r1, #0]
|
||||
225 0008 1043 ORRS r0, r2
|
||||
226 000a 0860 STR r0, [r1, #0]
|
||||
227
|
||||
228 000c 4FF09041 LDR r1, =GPIOA_MODER
|
||||
229 0010 FF22 MOVS r2, #0xFF
|
||||
230 0012 0868 LDR r0, [r1, #0]
|
||||
231 0014 9043 BICS r0, r2
|
||||
232 0016 4422 MOVS r2, #0x44
|
||||
233 0018 1043 ORRS r0, r2
|
||||
234 001a 0860 STR r0, [r1, #0]
|
||||
235
|
||||
236 001c 1F49 LDR r1, =GPIOA_ODR
|
||||
237 001e 0A22 MOVS r2, #0x0A
|
||||
238 0020 0868 LDR r0, [r1, #0]
|
||||
239 0022 9043 BICS r0, r2
|
||||
240 0024 0860 STR r0, [r1, #0]
|
||||
241
|
||||
242 #----------------------------------------------------------------------------------------#
|
||||
242 0026 EBE7 B _ISR_NMI
|
||||
243
|
||||
244 .align 2
|
||||
245 .syntax unified
|
||||
246 .thumb
|
||||
248 _ISR_HARDF:
|
||||
249 #--- enable clock
|
||||
250 0028 0D49 LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
|
||||
251 002a 4FF00102 MOV r2, #0x01 // load mask
|
||||
252 002e 0868 LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
|
||||
253 0030 1043 ORRS r0, r0, r2 // configure clock gating for port
|
||||
254 0032 0860 STR r0, [r1, #0] // apply settings
|
||||
255
|
||||
256 #--- init pins
|
||||
257 0034 4FF09041 LDR r1, =GPIOA_MODER // load port A mode register address
|
||||
258 0038 FF22 MOVS r2, #0xFF // prepare mask
|
||||
259 003a 0868 LDR r0, [r1, #0] // get current value of port A mode register
|
||||
260 003c 9043 BICS r0, r0, r2 // delete bits
|
||||
261 003e 1122 MOVS r2, #0x11 // load configuration mask
|
||||
262 0040 1043 ORRS r0, r0, r2 // configure pins
|
||||
263 0042 0860 STR r0, [r1, #0] // apply settings to port A mode register
|
||||
244 #----------------------------------------------------------------------------------------#
|
||||
245
|
||||
246 .align 2
|
||||
247 .syntax unified
|
||||
248 .thumb
|
||||
250 _ISR_HARDF:
|
||||
251 0028 1B49 LDR r1, =RCC_AHB2ENR
|
||||
252 002a 4FF00102 MOV r2, #0x01
|
||||
253 002e 0868 LDR r0, [r1, #0]
|
||||
254 0030 1043 ORRS r0, r2
|
||||
255 0032 0860 STR r0, [r1, #0]
|
||||
256
|
||||
257 0034 4FF09041 LDR r1, =GPIOA_MODER
|
||||
258 0038 FF22 MOVS r2, #0xFF
|
||||
259 003a 0868 LDR r0, [r1, #0]
|
||||
260 003c 9043 BICS r0, r2
|
||||
261 003e 1122 MOVS r2, #0x11
|
||||
262 0040 1043 ORRS r0, r2
|
||||
263 0042 0860 STR r0, [r1, #0]
|
||||
264
|
||||
265 #--- switch some LEDs on
|
||||
266 0044 0749 LDR r1, =GPIOA_ODR // load port A data output register address
|
||||
267 0046 0522 MOVS r2, #0x05 // load mask for red and green LED
|
||||
268 0048 0868 LDR r0, [r1, #0]
|
||||
269 004a 9043 BICS r0, r0, r2
|
||||
270 004c 0860 STR r0, [r1, #0] // switch LEDs on
|
||||
271
|
||||
272 004e EBE7 B _ISR_HARDF
|
||||
273
|
||||
265 0044 1549 LDR r1, =GPIOA_ODR
|
||||
266 0046 0522 MOVS r2, #0x05
|
||||
267 0048 0868 LDR r0, [r1, #0]
|
||||
268 004a 9043 BICS r0, r2
|
||||
269 004c 0860 STR r0, [r1, #0]
|
||||
270
|
||||
271 004e EBE7 B _ISR_HARDF
|
||||
272
|
||||
273 #----------------------------------------------------------------------------------------#
|
||||
274
|
||||
275 #----------------------------------------------------------------------------------------#
|
||||
276
|
||||
277 .align 2
|
||||
278 .syntax unified
|
||||
279 .thumb
|
||||
281 _ISR_S0:
|
||||
282 0050 00B5 PUSH {lr} // save special content
|
||||
283
|
||||
284 #--- do the work
|
||||
285
|
||||
286
|
||||
287 #--- clear interrupt flag
|
||||
288
|
||||
289
|
||||
290 #--- leave ISR
|
||||
291 0052 02BC POP {r1} // get special content back
|
||||
292 0054 0847 BX r1 // go back to where we came from
|
||||
293
|
||||
294
|
||||
295 #----------------------------------------------------------------------------------------#
|
||||
296
|
||||
297 0056 00BF .align 2
|
||||
298 .syntax unified
|
||||
299 .thumb
|
||||
301 _ISR_S1:
|
||||
302 0058 00B5 PUSH {lr} // save special content
|
||||
303
|
||||
304 #--- do the work
|
||||
305
|
||||
275 .align 2
|
||||
276 .syntax unified
|
||||
277 .thumb
|
||||
279 _ISR_EXTI0:
|
||||
280 0050 00B5 PUSH {lr}
|
||||
281
|
||||
282 #--- Entprellen
|
||||
283 0052 FFF7FEFF BL delay
|
||||
284
|
||||
285 #--- Überprüfen, ob Taster noch gedrückt ist (PB0)
|
||||
286 0056 1248 LDR r0, =GPIOB_IDR
|
||||
287 0058 0168 LDR r1, [r0, #0]
|
||||
288 005a 0122 MOVS r2, #0x01
|
||||
289 005c 1142 TST r1, r2
|
||||
290 005e 04D1 BNE _clear_exti0
|
||||
291
|
||||
292 #--- LED0 & LED3 toggeln (1001 = 0x09)
|
||||
293 0060 0E48 LDR r0, =GPIOA_ODR
|
||||
294 0062 0168 LDR r1, [r0, #0]
|
||||
295 0064 0922 MOVS r2, #0x09
|
||||
296 0066 5140 EORS r1, r2
|
||||
297 0068 0160 STR r1, [r0, #0]
|
||||
298
|
||||
299 _clear_exti0:
|
||||
300 #--- Interrupt Flag löschen
|
||||
301 006a 0E48 LDR r0, =EXTI_PR1
|
||||
302 006c 0121 MOVS r1, #0x01
|
||||
303 006e 0160 STR r1, [r0, #0]
|
||||
304
|
||||
305 0070 00BD POP {pc}
|
||||
306
|
||||
307
|
||||
307 #----------------------------------------------------------------------------------------#
|
||||
308
|
||||
309 #--- clear interrupt flag
|
||||
310
|
||||
311
|
||||
312
|
||||
313 #--- leave ISR
|
||||
314 005a 02BC POP {r1} // get special content back
|
||||
315 005c 0847 BX r1 // go back to where we came from
|
||||
316
|
||||
317
|
||||
318 #----------------------------------------------------------------------------------------#
|
||||
319 .lp2: // this label is only to nicify the line up in the .lst file
|
||||
320 005e 00004C10 .ltorg
|
||||
320 02401400
|
||||
320 0048
|
||||
321 #----------------------------------------------------------------------------------------#
|
||||
322
|
||||
323 .end
|
||||
309 0072 00BF .align 2
|
||||
310 .syntax unified
|
||||
311 .thumb
|
||||
313 _ISR_EXTI4:
|
||||
314 0074 00B5 PUSH {lr}
|
||||
315
|
||||
316 #--- Entprellen
|
||||
317 0076 FFF7FEFF BL delay
|
||||
318
|
||||
319 #--- Überprüfen, ob Taster noch gedrückt ist (PB4)
|
||||
320 007a 0948 LDR r0, =GPIOB_IDR
|
||||
321 007c 0168 LDR r1, [r0, #0]
|
||||
322 007e 1022 MOVS r2, #0x10
|
||||
323 0080 1142 TST r1, r2
|
||||
324 0082 04D1 BNE _clear_exti4
|
||||
325
|
||||
326 #--- LED1 & LED2 toggeln (0110 = 0x06)
|
||||
327 0084 0548 LDR r0, =GPIOA_ODR
|
||||
328 0086 0168 LDR r1, [r0, #0]
|
||||
329 0088 0622 MOVS r2, #0x06
|
||||
330 008a 5140 EORS r1, r2
|
||||
331 008c 0160 STR r1, [r0, #0]
|
||||
332
|
||||
333 _clear_exti4:
|
||||
334 #--- Interrupt Flag löschen
|
||||
335 008e 0548 LDR r0, =EXTI_PR1
|
||||
336 0090 1021 MOVS r1, #0x10
|
||||
337 0092 0160 STR r1, [r0, #0]
|
||||
338
|
||||
339 0094 00BD POP {pc}
|
||||
340
|
||||
341 #----------------------------------------------------------------------------------------#
|
||||
342 .lp2:
|
||||
343 0096 00004C10 .ltorg
|
||||
343 02401400
|
||||
343 00481004
|
||||
343 00481404
|
||||
343 0140
|
||||
344 #----------------------------------------------------------------------------------------#
|
||||
345
|
||||
346 .end
|
||||
DEFINED SYMBOLS
|
||||
G431_addr.s:39 *ABS*:40000000 APB1_BASE
|
||||
G431_addr.s:40 *ABS*:40010000 APB2_BASE
|
||||
@ -1599,22 +1631,24 @@ DEFINED SYMBOLS
|
||||
G431_addr.s:762 *ABS*:e0042008 DBGMCU_APB1FZR1
|
||||
G431_addr.s:763 *ABS*:e004200c DBGMCU_APB1FZR2
|
||||
G431_addr.s:764 *ABS*:e0042010 DBGMCU_APB2DZR
|
||||
task2.s:48 .vectortable:00000000 $d
|
||||
task2.s:215 .exhand:00000000 _ISR_NMI
|
||||
task2.s:248 .exhand:00000028 _ISR_HARDF
|
||||
task2.s:281 .exhand:00000050 _ISR_S0
|
||||
task2.s:69 .text:00000000 $t
|
||||
task2.s:75 .text:00000000 init
|
||||
task2.s:160 .text:00000044 main
|
||||
task2.s:182 .text:00000054 delay
|
||||
task2.s:196 .text:00000060 stop
|
||||
task2.s:202 .text:00000066 .lp1
|
||||
task2.s:203 .text:00000066 $d
|
||||
task2.s:203 .text:00000068 $d
|
||||
task2.s:211 .exhand:00000000 $t
|
||||
task2.s:301 .exhand:00000058 _ISR_S1
|
||||
task2.s:319 .exhand:0000005e .lp2
|
||||
task2.s:320 .exhand:0000005e $d
|
||||
task2.s:320 .exhand:00000060 $d
|
||||
task2.s:38 .vectortable:00000000 $d
|
||||
task2.s:61 .text:00000000 init
|
||||
task2.s:221 .exhand:00000000 _ISR_NMI
|
||||
task2.s:250 .exhand:00000028 _ISR_HARDF
|
||||
task2.s:279 .exhand:00000050 _ISR_EXTI0
|
||||
task2.s:313 .exhand:00000074 _ISR_EXTI4
|
||||
task2.s:55 .text:00000000 $t
|
||||
task2.s:181 .text:000000b8 main
|
||||
task2.s:193 .text:000000c0 delay
|
||||
task2.s:204 .text:000000c8 stop
|
||||
task2.s:209 .text:000000ce .lp1
|
||||
task2.s:210 .text:000000ce $d
|
||||
task2.s:210 .text:000000d0 $d
|
||||
task2.s:217 .exhand:00000000 $t
|
||||
task2.s:299 .exhand:0000006a _clear_exti0
|
||||
task2.s:333 .exhand:0000008e _clear_exti4
|
||||
task2.s:342 .exhand:00000096 .lp2
|
||||
task2.s:343 .exhand:00000096 $d
|
||||
task2.s:343 .exhand:00000098 $d
|
||||
|
||||
NO UNDEFINED SYMBOLS
|
||||
|
||||
BIN
task2/task2.elf
BIN
task2/task2.elf
Binary file not shown.
222
task2/task2.lst
222
task2/task2.lst
@ -3,11 +3,11 @@ task2.elf: file format elf32-littlearm
|
||||
|
||||
Sections:
|
||||
Idx Name Size VMA LMA File off Algn
|
||||
0 .vectortable 00000014 08000000 08000000 00001000 2**2
|
||||
0 .vectortable 0000006c 08000000 08000000 00001000 2**2
|
||||
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
||||
1 .text 00000074 08000400 08000400 00001400 2**2
|
||||
1 .text 00000100 08000400 08000400 00001400 2**2
|
||||
CONTENTS, ALLOC, LOAD, READONLY, CODE
|
||||
2 .exhand 00000068 08001000 08001000 00002000 2**2
|
||||
2 .exhand 000000a8 08001000 08001000 00002000 2**2
|
||||
CONTENTS, ALLOC, LOAD, READONLY, CODE
|
||||
SYMBOL TABLE:
|
||||
08000000 l d .vectortable 00000000 .vectortable
|
||||
@ -15,14 +15,16 @@ SYMBOL TABLE:
|
||||
08001000 l d .exhand 00000000 .exhand
|
||||
08001000 l F .exhand 00000000 _ISR_NMI
|
||||
08001028 l F .exhand 00000000 _ISR_HARDF
|
||||
08001050 l F .exhand 00000000 _ISR_S0
|
||||
08000466 l .text 00000000 .lp1
|
||||
08001058 l F .exhand 00000000 _ISR_S1
|
||||
0800105e l .exhand 00000000 .lp2
|
||||
08001050 l F .exhand 00000000 _ISR_EXTI0
|
||||
08001074 l F .exhand 00000000 _ISR_EXTI4
|
||||
080004ce l .text 00000000 .lp1
|
||||
0800106a l .exhand 00000000 _clear_exti0
|
||||
0800108e l .exhand 00000000 _clear_exti4
|
||||
08001096 l .exhand 00000000 .lp2
|
||||
08000400 g F .text 00000000 init
|
||||
08000444 g F .text 00000000 main
|
||||
08000454 g F .text 00000000 delay
|
||||
08000460 g .text 00000000 stop
|
||||
080004b8 g F .text 00000000 main
|
||||
080004c0 g F .text 00000000 delay
|
||||
080004c8 g .text 00000000 stop
|
||||
|
||||
|
||||
|
||||
@ -33,7 +35,10 @@ Disassembly of section .vectortable:
|
||||
8000004: 08000401 .word 0x08000401
|
||||
8000008: 08001001 .word 0x08001001
|
||||
800000c: 08001029 .word 0x08001029
|
||||
8000010: 08001051 .word 0x08001051
|
||||
...
|
||||
8000058: 08001051 .word 0x08001051
|
||||
...
|
||||
8000068: 08001075 .word 0x08001075
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
@ -52,55 +57,110 @@ Disassembly of section .text:
|
||||
8000416: 4682 mov sl, r0
|
||||
8000418: 4683 mov fp, r0
|
||||
800041a: 4684 mov ip, r0
|
||||
800041c: 4912 ldr r1, [pc, #72] @ (8000468 <.lp1+0x2>)
|
||||
800041e: f04f 0201 mov.w r2, #1
|
||||
8000422: 6808 ldr r0, [r1, #0]
|
||||
8000424: 4310 orrs r0, r2
|
||||
8000426: 6008 str r0, [r1, #0]
|
||||
8000428: f04f 4190 mov.w r1, #1207959552 @ 0x48000000
|
||||
800042c: 2203 movs r2, #3
|
||||
800041c: 492c ldr r1, [pc, #176] @ (80004d0 <.lp1+0x2>)
|
||||
800041e: 2203 movs r2, #3
|
||||
8000420: 6808 ldr r0, [r1, #0]
|
||||
8000422: 4310 orrs r0, r2
|
||||
8000424: 6008 str r0, [r1, #0]
|
||||
8000426: f04f 4190 mov.w r1, #1207959552 @ 0x48000000
|
||||
800042a: f04f 02ff mov.w r2, #255 @ 0xff
|
||||
800042e: 6808 ldr r0, [r1, #0]
|
||||
8000430: 4390 bics r0, r2
|
||||
8000432: 2201 movs r2, #1
|
||||
8000434: 4310 orrs r0, r2
|
||||
8000436: 6008 str r0, [r1, #0]
|
||||
8000438: 490c ldr r1, [pc, #48] @ (800046c <.lp1+0x6>)
|
||||
800043a: 2201 movs r2, #1
|
||||
800043c: 6808 ldr r0, [r1, #0]
|
||||
800043e: 4310 orrs r0, r2
|
||||
8000440: 6008 str r0, [r1, #0]
|
||||
8000442: b662 cpsie i
|
||||
8000432: f04f 0255 mov.w r2, #85 @ 0x55
|
||||
8000436: 4310 orrs r0, r2
|
||||
8000438: 6008 str r0, [r1, #0]
|
||||
800043a: 4926 ldr r1, [pc, #152] @ (80004d4 <.lp1+0x6>)
|
||||
800043c: 220f movs r2, #15
|
||||
800043e: 6808 ldr r0, [r1, #0]
|
||||
8000440: 4310 orrs r0, r2
|
||||
8000442: 6008 str r0, [r1, #0]
|
||||
8000444: 4924 ldr r1, [pc, #144] @ (80004d8 <.lp1+0xa>)
|
||||
8000446: f240 3203 movw r2, #771 @ 0x303
|
||||
800044a: 6808 ldr r0, [r1, #0]
|
||||
800044c: 4390 bics r0, r2
|
||||
800044e: 6008 str r0, [r1, #0]
|
||||
8000450: 4922 ldr r1, [pc, #136] @ (80004dc <.lp1+0xe>)
|
||||
8000452: f240 3203 movw r2, #771 @ 0x303
|
||||
8000456: 6808 ldr r0, [r1, #0]
|
||||
8000458: 4390 bics r0, r2
|
||||
800045a: f240 1201 movw r2, #257 @ 0x101
|
||||
800045e: 4310 orrs r0, r2
|
||||
8000460: 6008 str r0, [r1, #0]
|
||||
8000462: 491f ldr r1, [pc, #124] @ (80004e0 <.lp1+0x12>)
|
||||
8000464: 2201 movs r2, #1
|
||||
8000466: 6808 ldr r0, [r1, #0]
|
||||
8000468: 4310 orrs r0, r2
|
||||
800046a: 6008 str r0, [r1, #0]
|
||||
800046c: 491d ldr r1, [pc, #116] @ (80004e4 <.lp1+0x16>)
|
||||
800046e: f04f 020f mov.w r2, #15
|
||||
8000472: 6808 ldr r0, [r1, #0]
|
||||
8000474: 4390 bics r0, r2
|
||||
8000476: 2201 movs r2, #1
|
||||
8000478: 4310 orrs r0, r2
|
||||
800047a: 6008 str r0, [r1, #0]
|
||||
800047c: 491a ldr r1, [pc, #104] @ (80004e8 <.lp1+0x1a>)
|
||||
800047e: f04f 020f mov.w r2, #15
|
||||
8000482: 6808 ldr r0, [r1, #0]
|
||||
8000484: 4390 bics r0, r2
|
||||
8000486: 2201 movs r2, #1
|
||||
8000488: 4310 orrs r0, r2
|
||||
800048a: 6008 str r0, [r1, #0]
|
||||
800048c: 4917 ldr r1, [pc, #92] @ (80004ec <.lp1+0x1e>)
|
||||
800048e: 2211 movs r2, #17
|
||||
8000490: 6808 ldr r0, [r1, #0]
|
||||
8000492: 4310 orrs r0, r2
|
||||
8000494: 6008 str r0, [r1, #0]
|
||||
8000496: 4916 ldr r1, [pc, #88] @ (80004f0 <.lp1+0x22>)
|
||||
8000498: 2211 movs r2, #17
|
||||
800049a: 6808 ldr r0, [r1, #0]
|
||||
800049c: 4310 orrs r0, r2
|
||||
800049e: 6008 str r0, [r1, #0]
|
||||
80004a0: 4914 ldr r1, [pc, #80] @ (80004f4 <.lp1+0x26>)
|
||||
80004a2: f44f 6288 mov.w r2, #1088 @ 0x440
|
||||
80004a6: 6808 ldr r0, [r1, #0]
|
||||
80004a8: 4310 orrs r0, r2
|
||||
80004aa: 6008 str r0, [r1, #0]
|
||||
80004ac: 4912 ldr r1, [pc, #72] @ (80004f8 <.lp1+0x2a>)
|
||||
80004ae: 6808 ldr r0, [r1, #0]
|
||||
80004b0: 2207 movs r2, #7
|
||||
80004b2: 4310 orrs r0, r2
|
||||
80004b4: 6008 str r0, [r1, #0]
|
||||
80004b6: b662 cpsie i
|
||||
|
||||
08000444 <main>:
|
||||
8000444: 4909 ldr r1, [pc, #36] @ (800046c <.lp1+0x6>)
|
||||
8000446: 4050 eors r0, r2
|
||||
8000448: 6008 str r0, [r1, #0]
|
||||
800044a: f000 f803 bl 8000454 <delay>
|
||||
800044e: f7ff bff9 b.w 8000444 <main>
|
||||
8000452: bf00 nop
|
||||
080004b8 <main>:
|
||||
80004b8: bf30 wfi
|
||||
80004ba: f7ff bffd b.w 80004b8 <main>
|
||||
80004be: bf00 nop
|
||||
|
||||
08000454 <delay>:
|
||||
8000454: 2600 movs r6, #0
|
||||
8000456: 4f06 ldr r7, [pc, #24] @ (8000470 <.lp1+0xa>)
|
||||
8000458: 3601 adds r6, #1
|
||||
800045a: 42be cmp r6, r7
|
||||
800045c: d1fc bne.n 8000458 <delay+0x4>
|
||||
800045e: 4770 bx lr
|
||||
080004c0 <delay>:
|
||||
80004c0: 480e ldr r0, [pc, #56] @ (80004fc <.lp1+0x2e>)
|
||||
80004c2: 3801 subs r0, #1
|
||||
80004c4: d1fd bne.n 80004c2 <delay+0x2>
|
||||
80004c6: 4770 bx lr
|
||||
|
||||
08000460 <stop>:
|
||||
8000460: bf00 nop
|
||||
8000462: f7ff bffd b.w 8000460 <stop>
|
||||
080004c8 <stop>:
|
||||
80004c8: bf00 nop
|
||||
80004ca: f7ff bffd b.w 80004c8 <stop>
|
||||
|
||||
08000466 <.lp1>:
|
||||
8000466: 0000 .short 0x0000
|
||||
8000468: 4002104c .word 0x4002104c
|
||||
800046c: 48000014 .word 0x48000014
|
||||
8000470: 001e8480 .word 0x001e8480
|
||||
080004ce <.lp1>:
|
||||
80004ce: 0000 .short 0x0000
|
||||
80004d0: 4002104c .word 0x4002104c
|
||||
80004d4: 48000014 .word 0x48000014
|
||||
80004d8: 48000400 .word 0x48000400
|
||||
80004dc: 4800040c .word 0x4800040c
|
||||
80004e0: 40021060 .word 0x40021060
|
||||
80004e4: 40010008 .word 0x40010008
|
||||
80004e8: 4001000c .word 0x4001000c
|
||||
80004ec: 4001040c .word 0x4001040c
|
||||
80004f0: 40010400 .word 0x40010400
|
||||
80004f4: e000e100 .word 0xe000e100
|
||||
80004f8: e0042004 .word 0xe0042004
|
||||
80004fc: 00019e10 .word 0x00019e10
|
||||
|
||||
Disassembly of section .exhand:
|
||||
|
||||
08001000 <_ISR_NMI>:
|
||||
8001000: 4917 ldr r1, [pc, #92] @ (8001060 <.lp2+0x2>)
|
||||
8001000: 4925 ldr r1, [pc, #148] @ (8001098 <.lp2+0x2>)
|
||||
8001002: f04f 0201 mov.w r2, #1
|
||||
8001006: 6808 ldr r0, [r1, #0]
|
||||
8001008: 4310 orrs r0, r2
|
||||
@ -112,7 +172,7 @@ Disassembly of section .exhand:
|
||||
8001016: 2244 movs r2, #68 @ 0x44
|
||||
8001018: 4310 orrs r0, r2
|
||||
800101a: 6008 str r0, [r1, #0]
|
||||
800101c: 4911 ldr r1, [pc, #68] @ (8001064 <.lp2+0x6>)
|
||||
800101c: 491f ldr r1, [pc, #124] @ (800109c <.lp2+0x6>)
|
||||
800101e: 220a movs r2, #10
|
||||
8001020: 6808 ldr r0, [r1, #0]
|
||||
8001022: 4390 bics r0, r2
|
||||
@ -120,7 +180,7 @@ Disassembly of section .exhand:
|
||||
8001026: e7eb b.n 8001000 <_ISR_NMI>
|
||||
|
||||
08001028 <_ISR_HARDF>:
|
||||
8001028: 490d ldr r1, [pc, #52] @ (8001060 <.lp2+0x2>)
|
||||
8001028: 491b ldr r1, [pc, #108] @ (8001098 <.lp2+0x2>)
|
||||
800102a: f04f 0201 mov.w r2, #1
|
||||
800102e: 6808 ldr r0, [r1, #0]
|
||||
8001030: 4310 orrs r0, r2
|
||||
@ -132,25 +192,57 @@ Disassembly of section .exhand:
|
||||
800103e: 2211 movs r2, #17
|
||||
8001040: 4310 orrs r0, r2
|
||||
8001042: 6008 str r0, [r1, #0]
|
||||
8001044: 4907 ldr r1, [pc, #28] @ (8001064 <.lp2+0x6>)
|
||||
8001044: 4915 ldr r1, [pc, #84] @ (800109c <.lp2+0x6>)
|
||||
8001046: 2205 movs r2, #5
|
||||
8001048: 6808 ldr r0, [r1, #0]
|
||||
800104a: 4390 bics r0, r2
|
||||
800104c: 6008 str r0, [r1, #0]
|
||||
800104e: e7eb b.n 8001028 <_ISR_HARDF>
|
||||
|
||||
08001050 <_ISR_S0>:
|
||||
08001050 <_ISR_EXTI0>:
|
||||
8001050: b500 push {lr}
|
||||
8001052: bc02 pop {r1}
|
||||
8001054: 4708 bx r1
|
||||
8001056: bf00 nop
|
||||
8001052: f7ff fa35 bl 80004c0 <delay>
|
||||
8001056: 4812 ldr r0, [pc, #72] @ (80010a0 <.lp2+0xa>)
|
||||
8001058: 6801 ldr r1, [r0, #0]
|
||||
800105a: 2201 movs r2, #1
|
||||
800105c: 4211 tst r1, r2
|
||||
800105e: d104 bne.n 800106a <_clear_exti0>
|
||||
8001060: 480e ldr r0, [pc, #56] @ (800109c <.lp2+0x6>)
|
||||
8001062: 6801 ldr r1, [r0, #0]
|
||||
8001064: 2209 movs r2, #9
|
||||
8001066: 4051 eors r1, r2
|
||||
8001068: 6001 str r1, [r0, #0]
|
||||
|
||||
08001058 <_ISR_S1>:
|
||||
8001058: b500 push {lr}
|
||||
800105a: bc02 pop {r1}
|
||||
800105c: 4708 bx r1
|
||||
0800106a <_clear_exti0>:
|
||||
800106a: 480e ldr r0, [pc, #56] @ (80010a4 <.lp2+0xe>)
|
||||
800106c: 2101 movs r1, #1
|
||||
800106e: 6001 str r1, [r0, #0]
|
||||
8001070: bd00 pop {pc}
|
||||
8001072: bf00 nop
|
||||
|
||||
0800105e <.lp2>:
|
||||
800105e: 0000 .short 0x0000
|
||||
8001060: 4002104c .word 0x4002104c
|
||||
8001064: 48000014 .word 0x48000014
|
||||
08001074 <_ISR_EXTI4>:
|
||||
8001074: b500 push {lr}
|
||||
8001076: f7ff fa23 bl 80004c0 <delay>
|
||||
800107a: 4809 ldr r0, [pc, #36] @ (80010a0 <.lp2+0xa>)
|
||||
800107c: 6801 ldr r1, [r0, #0]
|
||||
800107e: 2210 movs r2, #16
|
||||
8001080: 4211 tst r1, r2
|
||||
8001082: d104 bne.n 800108e <_clear_exti4>
|
||||
8001084: 4805 ldr r0, [pc, #20] @ (800109c <.lp2+0x6>)
|
||||
8001086: 6801 ldr r1, [r0, #0]
|
||||
8001088: 2206 movs r2, #6
|
||||
800108a: 4051 eors r1, r2
|
||||
800108c: 6001 str r1, [r0, #0]
|
||||
|
||||
0800108e <_clear_exti4>:
|
||||
800108e: 4805 ldr r0, [pc, #20] @ (80010a4 <.lp2+0xe>)
|
||||
8001090: 2110 movs r1, #16
|
||||
8001092: 6001 str r1, [r0, #0]
|
||||
8001094: bd00 pop {pc}
|
||||
|
||||
08001096 <.lp2>:
|
||||
8001096: 0000 .short 0x0000
|
||||
8001098: 4002104c .word 0x4002104c
|
||||
800109c: 48000014 .word 0x48000014
|
||||
80010a0: 48000410 .word 0x48000410
|
||||
80010a4: 40010414 .word 0x40010414
|
||||
|
||||
@ -11,61 +11,61 @@ RAM 0x20000000 0x00001800 rw
|
||||
Linker script and memory map
|
||||
|
||||
|
||||
.vectortable 0x08000000 0x14
|
||||
.vectortable 0x08000000 0x6c
|
||||
0x08000000 . = ALIGN (0x4)
|
||||
*(.vectortable)
|
||||
.vectortable 0x08000000 0x14 task2.o
|
||||
0x08000014 . = ALIGN (0x4)
|
||||
.vectortable 0x08000000 0x6c task2.o
|
||||
0x0800006c . = ALIGN (0x4)
|
||||
|
||||
.text 0x08000400 0x74
|
||||
.text 0x08000400 0x100
|
||||
*(.text)
|
||||
.text 0x08000400 0x74 task2.o
|
||||
.text 0x08000400 0x100 task2.o
|
||||
0x08000400 init
|
||||
0x08000444 main
|
||||
0x08000454 delay
|
||||
0x08000460 stop
|
||||
0x080004b8 main
|
||||
0x080004c0 delay
|
||||
0x080004c8 stop
|
||||
|
||||
.glue_7 0x08000474 0x0
|
||||
.glue_7 0x08000474 0x0 linker stubs
|
||||
.glue_7 0x08000500 0x0
|
||||
.glue_7 0x08000500 0x0 linker stubs
|
||||
|
||||
.glue_7t 0x08000474 0x0
|
||||
.glue_7t 0x08000474 0x0 linker stubs
|
||||
.glue_7t 0x08000500 0x0
|
||||
.glue_7t 0x08000500 0x0 linker stubs
|
||||
|
||||
.vfp11_veneer 0x08000474 0x0
|
||||
.vfp11_veneer 0x08000474 0x0 linker stubs
|
||||
.vfp11_veneer 0x08000500 0x0
|
||||
.vfp11_veneer 0x08000500 0x0 linker stubs
|
||||
|
||||
.v4_bx 0x08000474 0x0
|
||||
.v4_bx 0x08000474 0x0 linker stubs
|
||||
.v4_bx 0x08000500 0x0
|
||||
.v4_bx 0x08000500 0x0 linker stubs
|
||||
|
||||
.iplt 0x08000474 0x0
|
||||
.iplt 0x08000474 0x0 task2.o
|
||||
.iplt 0x08000500 0x0
|
||||
.iplt 0x08000500 0x0 task2.o
|
||||
|
||||
.exhand 0x08001000 0x68
|
||||
.exhand 0x08001000 0xa8
|
||||
*(.exhand)
|
||||
.exhand 0x08001000 0x68 task2.o
|
||||
.exhand 0x08001000 0xa8 task2.o
|
||||
LOAD task2.o
|
||||
OUTPUT(task2.elf elf32-littlearm)
|
||||
LOAD linker stubs
|
||||
|
||||
.rel.dyn 0x08001068 0x0
|
||||
.rel.iplt 0x08001068 0x0 task2.o
|
||||
.rel.dyn 0x080010a8 0x0
|
||||
.rel.iplt 0x080010a8 0x0 task2.o
|
||||
|
||||
.data 0x08001068 0x0
|
||||
.data 0x08001068 0x0 task2.o
|
||||
.data 0x080010a8 0x0
|
||||
.data 0x080010a8 0x0 task2.o
|
||||
|
||||
.igot.plt 0x08001068 0x0
|
||||
.igot.plt 0x08001068 0x0 task2.o
|
||||
.igot.plt 0x080010a8 0x0
|
||||
.igot.plt 0x080010a8 0x0 task2.o
|
||||
|
||||
.bss 0x08001068 0x0
|
||||
.bss 0x08001068 0x0 task2.o
|
||||
.bss 0x080010a8 0x0
|
||||
.bss 0x080010a8 0x0 task2.o
|
||||
|
||||
.ARM.attributes
|
||||
0x00000000 0x21
|
||||
.ARM.attributes
|
||||
0x00000000 0x21 task2.o
|
||||
|
||||
.debug_line 0x00000000 0xc1
|
||||
.debug_line 0x00000000 0xc1 task2.o
|
||||
.debug_line 0x00000000 0x112
|
||||
.debug_line 0x00000000 0x112 task2.o
|
||||
|
||||
.debug_info 0x00000000 0x22
|
||||
.debug_info 0x00000000 0x22 task2.o
|
||||
|
||||
BIN
task2/task2.o
BIN
task2/task2.o
Binary file not shown.
205
task2/task2.s
205
task2/task2.s
@ -7,43 +7,49 @@
|
||||
|
||||
.include "G431_addr.s"
|
||||
|
||||
// Zusätzliche und benötigte Adressen
|
||||
// Falls in G431_addr.s vorhanden, diesen Block löschen um Fehler zu vermeiden:
|
||||
.equ RCC_AHB2ENR, 0x4002104C
|
||||
.equ RCC_APB2ENR, 0x40021060
|
||||
|
||||
.equ GPIOA_MODER, 0x48000000
|
||||
.equ GPIOA_ODR, 0x48000014
|
||||
|
||||
.equ GPIOC_MODER, 0x48000800
|
||||
.equ GPIOC_PUPDR, 0x4800080C
|
||||
.equ GPIOC_IDR, 0x48000810
|
||||
.equ GPIOB_MODER, 0x48000400
|
||||
.equ GPIOB_PUPDR, 0x4800040C
|
||||
.equ GPIOB_IDR, 0x48000410
|
||||
|
||||
.equ SYSCFG_BASE, 0x40010000
|
||||
.equ SYSCFG_EXTICR4, (SYSCFG_BASE + 0x14)
|
||||
.equ SYSCFG_EXTICR1, (SYSCFG_BASE + 0x08)
|
||||
.equ SYSCFG_EXTICR2, (SYSCFG_BASE + 0x0C)
|
||||
|
||||
.equ EXTI_BASE, 0x40010400
|
||||
.equ EXTI_IMR1, (EXTI_BASE + 0x00)
|
||||
.equ EXTI_FTSR1, (EXTI_BASE + 0x0C)
|
||||
.equ EXTI_PR1, (EXTI_BASE + 0x14)
|
||||
|
||||
.equ NVIC_ISER1, 0xE000E104
|
||||
.equ NVIC_ISER0, 0xE000E100
|
||||
|
||||
.equ DBGMCU_CR, 0xE0042004 // Adresse des Debug Configuration Registers
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.section .vectortable,"a" // vector table at begin of ROM
|
||||
.section .vectortable,"a"
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
|
||||
.word 0x20004000 // initial Stack Pointer
|
||||
.word 0x08000401 // initial Program Counter
|
||||
.word init // initial Program Counter
|
||||
.word _ISR_NMI // non-masking interrupt
|
||||
.word _ISR_HARDF // hard fault interrupt
|
||||
|
||||
.space 0xD0 // padding 208 Bytes bis Offset 0xE0 (EXTI15_10 IRQ 40)
|
||||
.word _ISR_S0_S1 // gemeinsamer Interrupt für PC13 (S0) und PC14 (S1)
|
||||
.space 0x48 // Padding 72 Bytes (Offset 0x10 -> 0x58)
|
||||
.word _ISR_EXTI0 // EXTI0_IRQHandler (PB0 / S0) - IRQ 6
|
||||
|
||||
.space 0x0C // Padding 12 Bytes (Offset 0x5C -> 0x68)
|
||||
.word _ISR_EXTI4 // EXTI4_IRQHandler (PB4 / S1) - IRQ 10
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.text // section .text (default section for program code)
|
||||
.text
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
@ -53,9 +59,9 @@
|
||||
.global init
|
||||
.type init, %function
|
||||
init:
|
||||
CPSID i // disable interrupts globally
|
||||
CPSID i
|
||||
|
||||
MOVS r0, #0 // safely initialize the GPRs
|
||||
MOVS r0, #0
|
||||
MOVS r1, #0
|
||||
MOVS r2, #0
|
||||
MOVS r3, #0
|
||||
@ -69,43 +75,43 @@ init:
|
||||
MOV r11, r0
|
||||
MOV r12, r0
|
||||
|
||||
#--- enable port clocking
|
||||
#--- enable port clocking (GPIOA, GPIOB)
|
||||
LDR r1, =RCC_AHB2ENR
|
||||
MOVS r2, #0x05 // Bit 0 (GPIOA) und Bit 2 (GPIOC)
|
||||
MOVS r2, #0x03 // Bit 0 (GPIOA) und Bit 1 (GPIOB)
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#--- port init
|
||||
#- LEDs (PA0-PA3)
|
||||
#- LEDs (PA0 - PA3) als Output
|
||||
LDR r1, =GPIOA_MODER
|
||||
LDR r2, =0x000000FF // Maske PA0-PA3
|
||||
LDR r2, =0x000000FF
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
LDR r2, =0x00000055 // Maske Output 0101 0101
|
||||
LDR r2, =0x00000055
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- switch LED off
|
||||
LDR r1, =GPIOA_ODR
|
||||
MOVS r2, #0x0F // Maske LED0-3
|
||||
MOVS r2, #0x0F
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- buttons (PC13, PC14 als Input)
|
||||
LDR r1, =GPIOC_MODER
|
||||
LDR r2, =0x3C000000 // Maske Bits 26-29
|
||||
#- buttons (PB0, PB4) als Input
|
||||
LDR r1, =GPIOB_MODER
|
||||
LDR r2, =0x00000303 // Maske Bits 0:1 (PB0) und 8:9 (PB4)
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- Pull-Up für PC13, PC14
|
||||
LDR r1, =GPIOC_PUPDR
|
||||
LDR r2, =0x3C000000
|
||||
#- Pull-Up für PB0, PB4
|
||||
LDR r1, =GPIOB_PUPDR
|
||||
LDR r2, =0x00000303
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
LDR r2, =0x14000000 // 01 = Pull-Up für PC13 (Bits 27:26) und PC14 (Bits 29:28)
|
||||
LDR r2, =0x00000101 // 01 = Pull-Up für PB0 und PB4
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
@ -118,36 +124,51 @@ init:
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
|
||||
LDR r1, =SYSCFG_EXTICR4
|
||||
LDR r2, =0x00000FF0 // Maske für EXTI13 (Bits 7:4) und EXTI14 (Bits 11:8)
|
||||
#- connect GPIO pins to EXTI lines
|
||||
LDR r1, =SYSCFG_EXTICR1 // EXTI0 (PB0)
|
||||
LDR r2, =0x000F // Maske EXTI0 (Bits 3:0)
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
LDR r2, =0x00000220 // Port C (0010) für EXTI13 und EXTI14
|
||||
MOVS r2, #0x0001 // Port B (0001)
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- configure lines in EXTI module (EXTI_* registers)
|
||||
LDR r1, =EXTI_FTSR1 // Fallende Flanke
|
||||
LDR r2, =0x00006000 // Bits 13 und 14
|
||||
LDR r1, =SYSCFG_EXTICR2 // EXTI4 (PB4)
|
||||
LDR r2, =0x000F // Maske EXTI4 (Bits 3:0)
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r2
|
||||
MOVS r2, #0x0001 // Port B (0001)
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- configure EXTI lines (falling edge, unmask)
|
||||
LDR r1, =EXTI_FTSR1
|
||||
MOVS r2, #0x11 // Bit 0 (EXTI0) und Bit 4 (EXTI4)
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
LDR r1, =EXTI_IMR1 // Maskierung aufheben
|
||||
LDR r2, =0x00006000
|
||||
LDR r1, =EXTI_IMR1
|
||||
MOVS r2, #0x11 // Bit 0 und Bit 4
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
#- NVIC: set interrupt priority, clear pending bits
|
||||
LDR r1, =NVIC_ISER1
|
||||
LDR r2, =0x00000100 // Bit 8 für IRQ 40 (EXTI15_10)
|
||||
#- NVIC: enable interrupts EXTI0 (IRQ 6) & EXTI4 (IRQ 10)
|
||||
LDR r1, =NVIC_ISER0
|
||||
LDR r2, =0x00000440 // Bit 6 (EXTI0) und Bit 10 (EXTI4)
|
||||
LDR r0, [r1, #0]
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
CPSIE i // enable interrupts globally
|
||||
#--- wachhalten während WFI
|
||||
LDR r1, =DBGMCU_CR
|
||||
LDR r0, [r1, #0]
|
||||
MOVS r2, #0x07 // Setzt DBG_SLEEP, DBG_STOP und DBG_STANDBY Bits
|
||||
ORRS r0, r2
|
||||
STR r0, [r1, #0]
|
||||
|
||||
CPSIE i
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
@ -170,7 +191,7 @@ main:
|
||||
.global delay
|
||||
.type delay, %function
|
||||
delay:
|
||||
LDR r0, =106000 // Entprell-Zeit ~20ms
|
||||
LDR r0, =106000
|
||||
.L1:
|
||||
SUBS r0, r0, #1
|
||||
BNE .L1
|
||||
@ -190,7 +211,7 @@ stop:
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.section .exhand,"ax" // section for exception handlers
|
||||
.section .exhand,"ax"
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
@ -254,69 +275,68 @@ _ISR_HARDF:
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_S0_S1, %function
|
||||
_ISR_S0_S1:
|
||||
PUSH {r4, r5, lr} // Wichtig: Register sichern gemäß AAPCS
|
||||
.type _ISR_EXTI0, %function
|
||||
_ISR_EXTI0:
|
||||
PUSH {lr}
|
||||
|
||||
_check_S0:
|
||||
LDR r4, =EXTI_PR1
|
||||
LDR r5, [r4, #0]
|
||||
LDR r2, =0x2000 // Maske für S0 (PC13 / Bit 13)
|
||||
TST r5, r2
|
||||
BEQ _check_S1 // Wenn Bit 13 nicht gesetzt, überspringen
|
||||
|
||||
#--- do the work S0
|
||||
BL delay // Entprellen
|
||||
|
||||
LDR r0, =GPIOC_IDR
|
||||
LDR r1, [r0, #0]
|
||||
LDR r2, =0x2000
|
||||
TST r1, r2
|
||||
BNE _clear_S0 // Abbruch, wenn High (Taster prellt / schon losgelassen)
|
||||
|
||||
LDR r0, =GPIOA_ODR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x09 // LED0 & LED3 toggeln (1001)
|
||||
EORS r1, r2
|
||||
STR r1, [r0, #0]
|
||||
|
||||
_clear_S0:
|
||||
#--- clear interrupt flag S0
|
||||
LDR r4, =EXTI_PR1
|
||||
LDR r5, =0x2000
|
||||
STR r5, [r4, #0]
|
||||
|
||||
_check_S1:
|
||||
LDR r4, =EXTI_PR1
|
||||
LDR r5, [r4, #0]
|
||||
LDR r2, =0x4000 // Maske für S1 (PC14 / Bit 14)
|
||||
TST r5, r2
|
||||
BEQ _leave_ISR // Wenn Bit 14 nicht gesetzt, Ende
|
||||
|
||||
#--- do the work S1
|
||||
#--- Entprellen
|
||||
BL delay
|
||||
|
||||
LDR r0, =GPIOC_IDR
|
||||
#--- Überprüfen, ob Taster noch gedrückt ist (PB0)
|
||||
LDR r0, =GPIOB_IDR
|
||||
LDR r1, [r0, #0]
|
||||
LDR r2, =0x4000
|
||||
MOVS r2, #0x01
|
||||
TST r1, r2
|
||||
BNE _clear_S1 // Abbruch, wenn High
|
||||
BNE _clear_exti0
|
||||
|
||||
#--- LED0 & LED3 toggeln (1001 = 0x09)
|
||||
LDR r0, =GPIOA_ODR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x06 // LED1 & LED2 toggeln (0110)
|
||||
MOVS r2, #0x09
|
||||
EORS r1, r2
|
||||
STR r1, [r0, #0]
|
||||
|
||||
_clear_S1:
|
||||
#--- clear interrupt flag S1
|
||||
LDR r4, =EXTI_PR1
|
||||
LDR r5, =0x4000
|
||||
STR r5, [r4, #0]
|
||||
_clear_exti0:
|
||||
#--- Interrupt Flag löschen
|
||||
LDR r0, =EXTI_PR1
|
||||
MOVS r1, #0x01
|
||||
STR r1, [r0, #0]
|
||||
|
||||
_leave_ISR:
|
||||
#--- leave ISR
|
||||
POP {r4, r5, pc} // Register wiederherstellen und zurückkehren
|
||||
POP {pc}
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_EXTI4, %function
|
||||
_ISR_EXTI4:
|
||||
PUSH {lr}
|
||||
|
||||
#--- Entprellen
|
||||
BL delay
|
||||
|
||||
#--- Überprüfen, ob Taster noch gedrückt ist (PB4)
|
||||
LDR r0, =GPIOB_IDR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x10
|
||||
TST r1, r2
|
||||
BNE _clear_exti4
|
||||
|
||||
#--- LED1 & LED2 toggeln (0110 = 0x06)
|
||||
LDR r0, =GPIOA_ODR
|
||||
LDR r1, [r0, #0]
|
||||
MOVS r2, #0x06
|
||||
EORS r1, r2
|
||||
STR r1, [r0, #0]
|
||||
|
||||
_clear_exti4:
|
||||
#--- Interrupt Flag löschen
|
||||
LDR r0, =EXTI_PR1
|
||||
MOVS r1, #0x10
|
||||
STR r1, [r0, #0]
|
||||
|
||||
POP {pc}
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.lp2:
|
||||
@ -325,4 +345,3 @@ _leave_ISR:
|
||||
|
||||
.end
|
||||
|
||||
#************************************** E O F *******************************************#
|
||||
|
||||
@ -1,325 +0,0 @@
|
||||
#****************************************************************************************#
|
||||
# Project: task2 - ASM: Interrupts
|
||||
# File: task2.s
|
||||
#
|
||||
# Language: ASM
|
||||
#
|
||||
# Hardware: STefi Light v1.1
|
||||
# Processor: STM32G431KBT6U
|
||||
#
|
||||
# Author: Manuel Lederhofer
|
||||
# Datum: 31.10.2014
|
||||
#
|
||||
# Version: 6.0
|
||||
# History:
|
||||
# 31.10.2014 ML create file
|
||||
# 27.09.2018 ML edit comments, extend vector table
|
||||
# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
|
||||
# 27.02.2019 ML move section of exception handlers to bottom of file
|
||||
# 25.09.2019 ML minor changes for a better code and comment understanding
|
||||
# 04.09.2020 HL port from STM32L476RG to STM32F411xE
|
||||
# 21.09.2020 ML tidy up, comments and formatting
|
||||
# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
|
||||
# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
|
||||
# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
|
||||
# 24.06.2025 TK remove /* ... place your code here ... */
|
||||
#
|
||||
# Status: working
|
||||
#
|
||||
# Description:
|
||||
# See the description and requirements of the requested application
|
||||
# in the lab exercise guide.
|
||||
#
|
||||
# Notes:
|
||||
# - MCU speed at startup is 16 MHz
|
||||
#
|
||||
# ToDo:
|
||||
# - Change the example code to match the description and requirements
|
||||
# of the requested application in the lab exercise guide.
|
||||
#****************************************************************************************#
|
||||
|
||||
.include "G431_addr.s"
|
||||
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.section .vectortable,"a" // vector table at begin of ROM
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
|
||||
.word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
|
||||
.word 0x08000401 // initial Program Counter
|
||||
.word _ISR_NMI // non-masking interrupt
|
||||
.word _ISR_HARDF // hard fault interrupt
|
||||
|
||||
|
||||
|
||||
/* N.B.
|
||||
Look at the .space or the .org assembler directive to insert the address of the
|
||||
ISRs at the right place in the vector table. Verify your settings by the help of
|
||||
the list file. */
|
||||
|
||||
.word _ISR_S0
|
||||
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.text // section .text (default section for program code)
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global init
|
||||
.type init, %function
|
||||
init:
|
||||
CPSID i // disable interrupts globally
|
||||
|
||||
MOVS r0, #0 // safely initialize the GPRs
|
||||
MOVS r1, #0
|
||||
MOVS r2, #0
|
||||
MOVS r3, #0
|
||||
MOVS r4, #0
|
||||
MOVS r5, #0
|
||||
MOVS r6, #0
|
||||
MOVS r7, #0
|
||||
MOV r8, r0
|
||||
MOV r9, r0
|
||||
MOV r10, r0
|
||||
MOV r11, r0
|
||||
MOV r12, r0
|
||||
|
||||
#--- enable port clocking
|
||||
LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
|
||||
MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
|
||||
LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
|
||||
ORRS r0, r0, r2 // configure clock gating for ports
|
||||
STR r0, [r1, #0] // apply settings
|
||||
|
||||
#--- port init
|
||||
#- LEDs
|
||||
LDR r1, =GPIOA_MODER // load port A mode register address
|
||||
MOVS r2, #0x03 // prepare mask
|
||||
LDR r0, [r1, #0] // get current value of port A mode register
|
||||
BICS r0, r2 // delete bits
|
||||
MOVS r2, #0x01 // load configuration mask
|
||||
ORRS r0, r0, r2 // apply mask
|
||||
STR r0, [r1, #0] // apply result to port A mode register
|
||||
|
||||
# LDR r1, =GPIOB_MODER
|
||||
# MOVS r3, #0x03
|
||||
# LDR r0, [r1, #1]
|
||||
# BICS r0, r3
|
||||
# MOVS r3, #0x01
|
||||
# ORRS r0, r0, r3
|
||||
# STR r0, [r1, #1]
|
||||
|
||||
#- switch LED off
|
||||
LDR r1, =GPIOA_ODR // load port A output data register
|
||||
MOVS r2, #0x01 // load mask for LED
|
||||
LDR r0, [r1, #0] // get current value of GPIOA
|
||||
ORRS r0, r0, r2 // configure pin state
|
||||
STR r0, [r1, #0] // apply settings
|
||||
|
||||
#- buttons
|
||||
|
||||
/* ... place your code here ... */
|
||||
|
||||
|
||||
#--- button interrupt config
|
||||
|
||||
#- enable clock for SYSCFG module
|
||||
|
||||
|
||||
#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
|
||||
# in SYSCFG module (SYSCFG_* registers)
|
||||
|
||||
|
||||
|
||||
|
||||
#- configure lines in EXTI module (EXTI_* registers)
|
||||
|
||||
|
||||
|
||||
#- NVIC: set interrupt priority, clear pending bits
|
||||
# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
|
||||
|
||||
|
||||
|
||||
CPSIE i // enable interrupts globally
|
||||
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global main
|
||||
.type main, %function
|
||||
main:
|
||||
LDR r1, =GPIOA_ODR
|
||||
EORS r0, r0, r2
|
||||
|
||||
STR r0, [r1, #0]
|
||||
|
||||
|
||||
|
||||
BL delay
|
||||
|
||||
|
||||
B main
|
||||
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.thumb_func
|
||||
.global delay
|
||||
.type delay, %function
|
||||
delay:
|
||||
MOVS r6, #0 // ...
|
||||
LDR r7, =2000000 // ...
|
||||
.L1:
|
||||
ADDS r6, r6, #1 // ...
|
||||
CMP r6, r7 // ...
|
||||
BNE .L1 // ...
|
||||
BX lr // ...
|
||||
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.global stop
|
||||
stop:
|
||||
NOP // do nothing (NOP is here to avoid a debugger crash, only)
|
||||
B stop // if this line is reached, something went wrong
|
||||
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.lp1: // this label is only to nicify the line up in the .lst file
|
||||
.ltorg
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.section .exhand,"ax" // section for exception handlers
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_NMI, %function
|
||||
_ISR_NMI:
|
||||
#--- enable clock
|
||||
LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
|
||||
MOV r2, #0x01 // load mask
|
||||
LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
|
||||
ORRS r0, r0, r2 // configure clock gating for port
|
||||
STR r0, [r1, #0] // apply settings
|
||||
|
||||
#--- init pins
|
||||
LDR r1, =GPIOA_MODER // load port A mode register address
|
||||
MOVS r2, #0xFF // prepare mask
|
||||
LDR r0, [r1, #0] // get current value of port A mode register
|
||||
BICS r0, r0, r2 // delete bits
|
||||
MOVS r2, #0x44 // load configuration mask
|
||||
ORRS r0, r0, r2 // configure pins
|
||||
STR r0, [r1, #0] // apply settings to port A mode register
|
||||
|
||||
#--- switch some LEDs on
|
||||
LDR r1, =GPIOA_ODR // load port A data output register address
|
||||
MOVS r2, #0x0A // load mask for blue and yellow LED
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r0, r2
|
||||
STR r0, [r1, #0] // switch LEDs on
|
||||
|
||||
B _ISR_NMI
|
||||
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_HARDF, %function
|
||||
_ISR_HARDF:
|
||||
#--- enable clock
|
||||
LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
|
||||
MOV r2, #0x01 // load mask
|
||||
LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
|
||||
ORRS r0, r0, r2 // configure clock gating for port
|
||||
STR r0, [r1, #0] // apply settings
|
||||
|
||||
#--- init pins
|
||||
LDR r1, =GPIOA_MODER // load port A mode register address
|
||||
MOVS r2, #0xFF // prepare mask
|
||||
LDR r0, [r1, #0] // get current value of port A mode register
|
||||
BICS r0, r0, r2 // delete bits
|
||||
MOVS r2, #0x11 // load configuration mask
|
||||
ORRS r0, r0, r2 // configure pins
|
||||
STR r0, [r1, #0] // apply settings to port A mode register
|
||||
|
||||
#--- switch some LEDs on
|
||||
LDR r1, =GPIOA_ODR // load port A data output register address
|
||||
MOVS r2, #0x05 // load mask for red and green LED
|
||||
LDR r0, [r1, #0]
|
||||
BICS r0, r0, r2
|
||||
STR r0, [r1, #0] // switch LEDs on
|
||||
|
||||
B _ISR_HARDF
|
||||
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_S0, %function
|
||||
_ISR_S0:
|
||||
PUSH {lr} // save special content
|
||||
|
||||
#--- do the work
|
||||
|
||||
|
||||
#--- clear interrupt flag
|
||||
|
||||
|
||||
#--- leave ISR
|
||||
POP {r1} // get special content back
|
||||
BX r1 // go back to where we came from
|
||||
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.align 2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.type _ISR_S1, %function
|
||||
_ISR_S1:
|
||||
PUSH {lr} // save special content
|
||||
|
||||
#--- do the work
|
||||
|
||||
|
||||
|
||||
|
||||
#--- clear interrupt flag
|
||||
|
||||
|
||||
|
||||
#--- leave ISR
|
||||
POP {r1} // get special content back
|
||||
BX r1 // go back to where we came from
|
||||
|
||||
|
||||
#----------------------------------------------------------------------------------------#
|
||||
.lp2: // this label is only to nicify the line up in the .lst file
|
||||
.ltorg
|
||||
#----------------------------------------------------------------------------------------#
|
||||
|
||||
.end
|
||||
|
||||
#************************************** E O F *******************************************#
|
||||
Loading…
x
Reference in New Issue
Block a user