diff --git a/.metadata/.log b/.metadata/.log
index b1c995e..ec8277e 100644
--- a/.metadata/.log
+++ b/.metadata/.log
@@ -9259,3 +9259,72 @@ Command-line arguments: -os linux -ws gtk -arch x86_64
!ENTRY com.st.stm32cube.ide.mcu.ide 1 1 2026-03-20 18:06:39.545
!MESSAGE Started RMI Server, listening on port 41337
+!SESSION 2026-03-21 13:54:00.770 -----------------------------------------------
+eclipse.buildId=Version 1.16.0
+java.version=17.0.11
+java.vendor=Eclipse Adoptium
+BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=de_DE
+Command-line arguments: -os linux -ws gtk -arch x86_64
+
+!ENTRY org.eclipse.core.resources 2 10035 2026-03-21 13:54:03.586
+!MESSAGE The workspace exited with unsaved changes in the previous session; refreshing workspace to recover changes.
+
+!ENTRY com.st.stm32cube.ide.mcu.informationcenter 4 4 2026-03-21 13:54:07.401
+!MESSAGE CubeMX plugin appears to be active, Log4j initialization might be too late.
+
+!ENTRY com.st.stm32cube.ide.mcu.informationcenter 1 1 2026-03-21 13:54:07.402
+!MESSAGE Log4j2 initialized with config file /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/.metadata/.log4j2.xml
+
+!ENTRY com.st.stm32cube.ide.mcu.ide 1 1 2026-03-21 13:54:12.808
+!MESSAGE Started RMI Server, listening on port 41337
+!SESSION 2026-03-24 14:01:44.656 -----------------------------------------------
+eclipse.buildId=Version 1.16.0
+java.version=17.0.11
+java.vendor=Eclipse Adoptium
+BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=de_DE
+Command-line arguments: -os linux -ws gtk -arch x86_64
+
+!ENTRY org.eclipse.core.resources 2 10035 2026-03-24 14:01:47.209
+!MESSAGE The workspace exited with unsaved changes in the previous session; refreshing workspace to recover changes.
+
+!ENTRY com.st.stm32cube.ide.mcu.informationcenter 4 4 2026-03-24 14:01:50.655
+!MESSAGE CubeMX plugin appears to be active, Log4j initialization might be too late.
+
+!ENTRY com.st.stm32cube.ide.mcu.informationcenter 1 1 2026-03-24 14:01:50.656
+!MESSAGE Log4j2 initialized with config file /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/.metadata/.log4j2.xml
+
+!ENTRY com.st.stm32cube.ide.mcu.ide 1 1 2026-03-24 14:01:55.388
+!MESSAGE Started RMI Server, listening on port 41337
+!SESSION 2026-03-24 14:11:26.431 -----------------------------------------------
+eclipse.buildId=Version 1.16.0
+java.version=17.0.11
+java.vendor=Eclipse Adoptium
+BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=de_DE
+Command-line arguments: -os linux -ws gtk -arch x86_64
+
+!ENTRY com.st.stm32cube.ide.mcu.informationcenter 4 4 2026-03-24 14:11:31.118
+!MESSAGE CubeMX plugin appears to be active, Log4j initialization might be too late.
+
+!ENTRY com.st.stm32cube.ide.mcu.informationcenter 1 1 2026-03-24 14:11:31.119
+!MESSAGE Log4j2 initialized with config file /home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/.metadata/.log4j2.xml
+
+!ENTRY com.st.stm32cube.ide.mcu.ide 1 1 2026-03-24 14:11:45.929
+!MESSAGE Started RMI Server, listening on port 41337
+
+!ENTRY com.st.stm32cube.ide.mcu.debug 4 0 2026-03-24 14:15:22.829
+!MESSAGE Error - No active DSF-Session. tmpSessionId = 3 (contextManager row 121)
+
+!ENTRY com.st.stm32cube.ide.mcu.debug 4 0 2026-03-24 14:15:22.830
+!MESSAGE Existing sessions are:
+
+!ENTRY com.st.stm32cube.ide.mcu.debug 4 0 2026-03-24 14:17:18.477
+!MESSAGE Error - No active DSF-Session. tmpSessionId = 6 (contextManager row 121)
+
+!ENTRY com.st.stm32cube.ide.mcu.debug 4 0 2026-03-24 14:17:18.477
+!MESSAGE Existing sessions are:
+
+!ENTRY com.st.stm32cube.ide.mcu.debug 4 0 2026-03-24 14:18:01.013
+!MESSAGE Error - No active DSF-Session. tmpSessionId = 7 (contextManager row 121)
+
+!ENTRY com.st.stm32cube.ide.mcu.debug 4 0 2026-03-24 14:18:01.013
+!MESSAGE Existing sessions are:
diff --git a/.metadata/.plugins/org.eclipse.cdt.core/.log b/.metadata/.plugins/org.eclipse.cdt.core/.log
index fdc2cef..3dfd0d5 100644
--- a/.metadata/.plugins/org.eclipse.cdt.core/.log
+++ b/.metadata/.plugins/org.eclipse.cdt.core/.log
@@ -51,3 +51,4 @@
*** SESSION März 01, 2026 11:55:48.249 -----------------------------------------
*** SESSION März 13, 2026 10:49:11.272 -----------------------------------------
*** SESSION März 16, 2026 12:55:55.445 -----------------------------------------
+*** SESSION März 24, 2026 14:01:49.132 -----------------------------------------
diff --git a/.metadata/.plugins/org.eclipse.cdt.core/task1.1727452765701.pdom b/.metadata/.plugins/org.eclipse.cdt.core/task1.1727452765701.pdom
index 03a2b95..aa128eb 100644
Binary files a/.metadata/.plugins/org.eclipse.cdt.core/task1.1727452765701.pdom and b/.metadata/.plugins/org.eclipse.cdt.core/task1.1727452765701.pdom differ
diff --git a/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log b/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log
index 8f0e68b..b81bd4b 100644
--- a/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log
+++ b/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log
@@ -323,3 +323,233 @@ Finished building: default.size.stdout
Finished building: task1.list
+16:09:45 **** Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 240 0 0 240 f0 task2.elf
+Target all ready
+18:20:32 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+task2.s: Assembler messages:
+task2.s:128: Error: ARM register expected -- `movs '
+make: *** [makefile:74: task2.o] Error 1
+"make -j12 all" terminated with exit code 2. Build might be incomplete.
+18:20:48 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 260 0 0 260 104 task2.elf
+Target all ready
+18:21:57 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 260 0 0 260 104 task2.elf
+Target all ready
+18:22:48 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 240 0 0 240 f0 task2.elf
+Target all ready
+18:23:22 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 260 0 0 260 104 task2.elf
+Target all ready
+18:23:42 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 260 0 0 260 104 task2.elf
+Target all ready
+18:23:54 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 260 0 0 260 104 task2.elf
+Target all ready
+18:24:03 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 260 0 0 260 104 task2.elf
+Target all ready
+18:24:24 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 260 0 0 260 104 task2.elf
+Target all ready
+18:24:36 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 260 0 0 260 104 task2.elf
+Target all ready
+18:25:04 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 260 0 0 260 104 task2.elf
+Target all ready
+18:25:26 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 260 0 0 260 104 task2.elf
+Target all ready
+18:25:42 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 260 0 0 260 104 task2.elf
+Target all ready
+18:26:11 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 260 0 0 260 104 task2.elf
+Target all ready
+18:26:34 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 264 0 0 264 108 task2.elf
+Target all ready
+18:26:57 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 248 0 0 248 f8 task2.elf
+Target all ready
+18:27:24 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+Target all ready
+18:29:47 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 240 0 0 240 f0 task2.elf
+Target all ready
+18:35:13 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 240 0 0 240 f0 task2.elf
+Target all ready
+18:35:46 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+Target all ready
+18:35:51 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+Target all ready
+14:12:30 **** Build of configuration Debug for project task2 ****
+make -j12 all
+Target all ready
+14:12:55 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+Target all ready
+14:13:16 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+Target all ready
+14:13:43 **** Clean-only build of configuration Debug for project task1 ****
+make -j12 clean
+rm -rf ./Startup/startup_stm32g431kbtx.d ./Startup/startup_stm32g431kbtx.o ./Startup/syscalls.cyclo ./Startup/syscalls.d ./Startup/syscalls.o ./Startup/syscalls.su ./Startup/sysmem.cyclo ./Startup/sysmem.d ./Startup/sysmem.o ./Startup/sysmem.su
+rm -rf ./Src/task1.cyclo ./Src/task1.d ./Src/task1.o ./Src/task1.su ./Src/task1_it.cyclo ./Src/task1_it.d ./Src/task1_it.o ./Src/task1_it.su
+rm -rf default.size.stdout task1.elf task1.list task1.map
+
+14:13:44 **** Clean-only build of configuration Debug for project task2 ****
+make -j12 clean
+14:13:44 **** Clean-only build of configuration Debug for project task3 ****
+make -j12 clean
+makefile:62: *** multiple target patterns. Stop.
+"make -j12 clean" terminated with exit code 2. Build might be incomplete.
+14:13:44 **** Clean-only build of configuration Debug for project task4 ****
+make -j12 clean
+makefile:62: *** multiple target patterns. Stop.
+"make -j12 clean" terminated with exit code 2. Build might be incomplete.
+14:14:11 **** Build of configuration Debug for project task2 ****
+make -j12 all
+arm-none-eabi-as -o task2.o task2.s -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn > task2.als
+arm-none-eabi-ld -o task2.elf -T ldscript_rom.ld task2.o -g -Map task2.map --cref -static
+arm-none-eabi-objdump -htdr -j .text -j .data -j .bss -j .vectortable -j .exhand task2.elf > task2.lst
+arm-none-eabi-size task2.elf
+ text data bss dec hex filename
+ 240 0 0 240 f0 task2.elf
+Target all ready
+14:15:19 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+Target all ready
+14:15:29 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+Target all ready
+14:16:17 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+Target all ready
+14:17:15 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+Target all ready
+14:17:57 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+Target all ready
+14:19:07 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+Target all ready
diff --git a/.metadata/.plugins/org.eclipse.cdt.ui/task1.build.log b/.metadata/.plugins/org.eclipse.cdt.ui/task1.build.log
index 40362b7..4dc73d1 100644
--- a/.metadata/.plugins/org.eclipse.cdt.ui/task1.build.log
+++ b/.metadata/.plugins/org.eclipse.cdt.ui/task1.build.log
@@ -1,17 +1,9 @@
-15:01:24 **** Incremental Build of configuration Debug for project task1 ****
-make -j12 all
-arm-none-eabi-gcc "../Src/task1.c" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DSTM32G431KBTx -DSTM32 -DSTM32G4 -DNUCLEO_G431KB -c -I../Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"Src/task1.d" -MT"Src/task1.o" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "Src/task1.o"
-arm-none-eabi-gcc -o "task1.elf" @"objects.list" -mcpu=cortex-m4 -T"/home/tobii/02_Uni/09_Mikrocomputertechnik/praktikum/mct_bei_workspace_25w/task1/STM32G431KBTX_FLASH.ld" --specs=nosys.specs -Wl,-Map="task1.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group
-Finished building target: task1.elf
-
-arm-none-eabi-size task1.elf
-arm-none-eabi-objdump -h -S task1.elf > "task1.list"
- text data bss dec hex filename
- 1692 0 1568 3260 cbc task1.elf
-Finished building: default.size.stdout
-
-Finished building: task1.list
+14:13:43 **** Clean-only build of configuration Debug for project task1 ****
+make -j12 clean
+rm -rf ./Startup/startup_stm32g431kbtx.d ./Startup/startup_stm32g431kbtx.o ./Startup/syscalls.cyclo ./Startup/syscalls.d ./Startup/syscalls.o ./Startup/syscalls.su ./Startup/sysmem.cyclo ./Startup/sysmem.d ./Startup/sysmem.o ./Startup/sysmem.su
+rm -rf ./Src/task1.cyclo ./Src/task1.d ./Src/task1.o ./Src/task1.su ./Src/task1_it.cyclo ./Src/task1_it.d ./Src/task1_it.o ./Src/task1_it.su
+rm -rf default.size.stdout task1.elf task1.list task1.map
-15:01:24 Build Finished. 0 errors, 0 warnings. (took 330ms)
+14:13:44 Build Finished. 0 errors, 0 warnings. (took 187ms)
diff --git a/.metadata/.plugins/org.eclipse.cdt.ui/task2.build.log b/.metadata/.plugins/org.eclipse.cdt.ui/task2.build.log
index dbb8e08..5ed8344 100644
--- a/.metadata/.plugins/org.eclipse.cdt.ui/task2.build.log
+++ b/.metadata/.plugins/org.eclipse.cdt.ui/task2.build.log
@@ -1,5 +1,6 @@
-11:52:45 **** Clean-only build of configuration Debug for project task2 ****
-make -j12 clean
+14:19:07 **** Incremental Build of configuration Debug for project task2 ****
+make -j12 all
+Target all ready
-11:52:45 Build Finished. 0 errors, 0 warnings. (took 126ms)
+14:19:07 Build Finished. 0 errors, 0 warnings. (took 182ms)
diff --git a/.metadata/.plugins/org.eclipse.cdt.ui/task3.build.log b/.metadata/.plugins/org.eclipse.cdt.ui/task3.build.log
index 72c4abb..9a759c0 100644
--- a/.metadata/.plugins/org.eclipse.cdt.ui/task3.build.log
+++ b/.metadata/.plugins/org.eclipse.cdt.ui/task3.build.log
@@ -1,7 +1,7 @@
-11:52:45 **** Clean-only build of configuration Debug for project task3 ****
+14:13:44 **** Clean-only build of configuration Debug for project task3 ****
make -j12 clean
makefile:62: *** multiple target patterns. Stop.
"make -j12 clean" terminated with exit code 2. Build might be incomplete.
-11:52:45 Build Failed. 1 errors, 0 warnings. (took 126ms)
+14:13:44 Build Failed. 1 errors, 0 warnings. (took 186ms)
diff --git a/.metadata/.plugins/org.eclipse.cdt.ui/task4.build.log b/.metadata/.plugins/org.eclipse.cdt.ui/task4.build.log
index 816d22b..fc6f36c 100644
--- a/.metadata/.plugins/org.eclipse.cdt.ui/task4.build.log
+++ b/.metadata/.plugins/org.eclipse.cdt.ui/task4.build.log
@@ -1,7 +1,7 @@
-11:52:46 **** Clean-only build of configuration Debug for project task4 ****
+14:13:44 **** Clean-only build of configuration Debug for project task4 ****
make -j12 clean
makefile:62: *** multiple target patterns. Stop.
"make -j12 clean" terminated with exit code 2. Build might be incomplete.
-11:52:46 Build Failed. 1 errors, 0 warnings. (took 127ms)
+14:13:44 Build Failed. 1 errors, 0 warnings. (took 186ms)
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/12/803564f14a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/12/803564f14a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..5d43f60
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/12/803564f14a2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x03
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x01
+ ORRS r0, r0, r3
+ STR r0, [r1, #3]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/2/a0997bb54a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/2/a0997bb54a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..e84fc32
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/2/a0997bb54a2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x05
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x01
+ ORRS r0, r0, r3
+ STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/20/102cdbc14a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/20/102cdbc14a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..60018bf
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/20/102cdbc14a2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x05
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x04
+ ORRS r0, r0, r3
+ STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/24/f01031934a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/24/f01031934a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..e84fc32
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/24/f01031934a2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x05
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x01
+ ORRS r0, r0, r3
+ STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/2e/202733fa4a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/2e/202733fa4a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..b6f915b
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/2e/202733fa4a2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x03
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x01
+ ORRS r0, r0, r3
+ STR r0, [r1, #2]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/57/c00825cd4a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/57/c00825cd4a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..ce9215c
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/57/c00825cd4a2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x05
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x05
+ ORRS r0, r0, r3
+ STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/5e/c0318c4a4c2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/5e/c0318c4a4c2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..9244469
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/5e/c0318c4a4c2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+# LDR r1, =GPIOB_MODER
+# MOVS r3, #0x03
+# LDR r0, [r1, #1]
+# BICS r0, r3
+# MOVS r3, #0x01
+# ORRS r0, r0, r3
+# STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/62/7054d2ba4a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/62/7054d2ba4a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..b391d24
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/62/7054d2ba4a2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x05
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x03
+ ORRS r0, r0, r3
+ STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/64/40291de44a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/64/40291de44a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..4b73458
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/64/40291de44a2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x03
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x01
+ ORRS r0, r0, r3
+ STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/69/405e85284b2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/69/405e85284b2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..4a6a793
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/69/405e85284b2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOB_MODER
+ MOVS r3, #0x03
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x01
+ ORRS r0, r0, r3
+ STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/6a/b0d749d54a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/6a/b0d749d54a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..e956a57
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/6a/b0d749d54a2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x01
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x01
+ ORRS r0, r0, r3
+ STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/81/b0e0d9dc4a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/81/b0e0d9dc4a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..a682862
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/81/b0e0d9dc4a2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x02
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x01
+ ORRS r0, r0, r3
+ STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/87/6042399c472500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/87/6042399c472500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..fa2ba02
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/87/6042399c472500111a3cc0d2fb41a96e
@@ -0,0 +1,314 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r2
+ STR r0, [r1, #0]
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/88/a009658d4b2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/88/a009658d4b2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..ff4c18e
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/88/a009658d4b2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+# LDR r1, =GPIOA_MODER // load port A mode register address
+# MOVS r2, #0x03 // prepare mask
+# LDR r0, [r1, #0] // get current value of port A mode register
+# BICS r0, r2 // delete bits
+# MOVS r2, #0x01 // load configuration mask
+# ORRS r0, r0, r2 // apply mask
+# STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOB_MODER
+ MOVS r3, #0x03
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x01
+ ORRS r0, r0, r3
+ STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/a3/8000d91a4b2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/a3/8000d91a4b2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..9d73acd
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/a3/8000d91a4b2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x03
+ LDR r0, [r1, #2]
+ BICS r0, r3
+ MOVS r3, #0x01
+ ORRS r0, r0, r3
+ STR r0, [r1, #2]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/b2/e0f20e0b4b2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/b2/e0f20e0b4b2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..4b73458
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/b2/e0f20e0b4b2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x03
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x01
+ ORRS r0, r0, r3
+ STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/cb/f09ec06d0f2200111ca2ee31eda545ee b/.metadata/.plugins/org.eclipse.core.resources/.history/cb/f09ec06d0f2200111ca2ee31eda545ee
deleted file mode 100644
index 5d32b18..0000000
--- a/.metadata/.plugins/org.eclipse.core.resources/.history/cb/f09ec06d0f2200111ca2ee31eda545ee
+++ /dev/null
@@ -1,212 +0,0 @@
-/* ***************************************************************************************
- * Project: task1 - C:GPIO
- * File: task1.c
- *
- * Language: C
- *
- * Hardware: STefi Light v1.1
- * Processor: STM32G431KBT6U
- *
- * Author: Manuel Lederhofer
- * Datum: 10.09.2021
- *
- * Version: 2.1
- * History:
- * 10.09.2021 ML create project
- * 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
- * 18.02.2025 TK changed projectname to "C: GPIO)
- *
- * Status: under development
- *
- * Description:
- * Blinks the red LED of STefi Light, currently.
- * This file contains the main routine and the initialization.
- *
- * Notes:
- * - MCU speed at startup is 16 MHz
- *
- * Todo:
- * - Change the example code to match the description and requirements
- * of the requested application in the lab exercise guide.
- *
- ************************************************************************************** */
-
-/* ------------------------------------ INCLUDES -------------------------------------- */
-#include "stm32g431xx.h"
-#include "STefi-Light.h"
-
-/* ------------------------------------ DEFINES --------------------------------------- */
-#define LOOPS_PER_MS 1244 // NOP-loops for delay()
-#define WAITTIME 333
-
-/* ------------------------------------ TYPE DEFINITIONS ------------------------------ */
-/* ------------------------------------ GLOBAL VARIABLES ------------------------------ */
-int state = 0;
-
-/* ------------------------------------ PRIVATE VARIABLES ----------------------------- */
-
-/* ------------------------------------ PROTOTYPES ------------------------------------ */
-static void GPIO_init(void);
-static void delay(const uint16_t ms);
-
-/* ------------------------------------ M A I N --------------------------------------- */
-int main(void)
-{
- /* --- initialization --- */
- __disable_irq(); // disable interrupts globally
-
- GPIO_init();
-
- __enable_irq(); // enable interrupts globally
-
- /* --- one time tasks --- */
-
- //s0 Hilfvariablen auserhalb von while deklarieren
- int running = 0; //0 Lauflicht aus, 1 Lauflicht an
- int lastButtonState = 1; // Hilfsvariable zur Flankenerkennung
-
- /* --- infinite processing loop --- */
- while (1)
- {
- int buttonState = GPIOB->IDR & (1 << 0);
-
- // fallende Flanke erkennen
- if (lastButtonState && !buttonState)
- {
- running ^= 1; // toggle running
- /* delay(50); // entprellen */
- }
-
- lastButtonState = buttonState;
-
-
- if(running)
- {
- switch (state)
- {
- case 0:
- state++;
- GPIOA->ODR &= ~(1 << 0);
- delay(WAITTIME);
- GPIOA->ODR |= (1 << 0);
- break;
- case 1:
- state++;
- GPIOA->ODR &= ~(1 << 1);
- delay(WAITTIME);
- GPIOA->ODR |= (1 << 1);
- break;
- case 2:
- state++;
- GPIOA->ODR &= ~(1 << 2);
- delay(WAITTIME);
- GPIOA->ODR |= (1 << 2);
- break;
- case 3:
- state++;
- GPIOA->ODR &= ~(1 << 3);
- delay(WAITTIME);
- GPIOA->ODR |= (1 << 3);
- break;
- case 4:
- state++;
- GPIOA->ODR &= ~(1 << 2);
- delay(WAITTIME);
- GPIOA->ODR |= (1 << 2);
- break;
- case 5:
- state=0;
- GPIOA->ODR &= ~(1 << 1);
- delay(WAITTIME);
- GPIOA->ODR |= (1 << 1);
- break;
-
- case 99:
- GPIOA->ODR |= MASK_LED_ALL;
- while(1){
- if((GPIOB->IDR & (1 << 0)) == 0){
- delay(150);
- state=0;
- break;
- }
- }
- }
- }
-
- }
- //aktuell geht er mit drücken durch die cases
- // wegen break geht er ganz aus der if bedingung raus, nicht nur ausm switch case
-
-
-return 1;
-}
-
-/* ------------------------------------ GLOBAL FUNCTIONS ------------------------------ */
-
-/* ------------------------------------ PRIVATE FUNCTIONS ----------------------------- */
-
-/* ------------------------------------------------------------------------------------ *\
- * method: static void GPIO_init(void)
- *
- * Initializes GPIOs on STefi Light for pins with peripherals attached.
- *
- * requires: - nothing -
- * parameters: - none -
- * returns: - nothing -
- \* ------------------------------------------------------------------------------------ */
-static void GPIO_init(void)
-{
-/* enable port clocks */
-RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN; // LEDs: A
-RCC->AHB2ENR |= RCC_AHB2ENR_GPIOBEN; //Taster versuch
-
-/* --- LEDs --- */
-GPIOA->ODR |= MASK_LED_ALL;
-GPIOA->MODER &= ~(3 << 0);
-GPIOA->MODER |= (1 << 0); // set LED pin to output
-
-/* LED1 als Output */
-GPIOA->MODER &= ~(3 << 2); // Versuch: LED 1 Mode löschen :klappt so
-GPIOA->MODER |= (1 << 2); // Versuch: LED 1 PA1 = output :klappt so
-
-/* LED2 als Output */
-GPIOA->MODER &= ~(3 << 4); // Versuch: LED 2 Mode löschen :klappt
-GPIOA->MODER |= (1 << 4); // Versuch: LED 2 PA1 = output :klappt
-
-/* LED3 als output */
-GPIOA->MODER &= ~(3 << 6);
-GPIOA->MODER |= (1 << 6);
-
-/* s0 (PB0) als Input Versuch */
-GPIOB->MODER &= ~(3 << 0);
-
-/* Pull-Up Aktivieren Versuch */
-GPIOB->PUPDR &= ~(3 << 0);
-GPIOB->PUPDR |= (1 << 0); // 01 = Pull-Up
-}
-
-/* ------------------------------------------------------------------------------------ *\
- * method: static void delay(const uint16_t ms)
- *
- * Realizes a millisecond delay by very bad busy-wait.
- *
- * requires: - nothing -
- * parameters: ms - delay time in milliseconds
- * returns: - nothing -
- \* ------------------------------------------------------------------------------------ */
-static void delay(const uint16_t ms)
-{
-for (uint16_t i = 0; i < ms; ++i)
-{
- if((GPIOB->IDR & (1 << 0) && state != 99) == 0){
- state = 99;
- break;
- }
- for (uint16_t j = 0; j < LOOPS_PER_MS; ++j)
- {
- __asm("NOP");
- }
-}
-}
-
-/* ************************************ E O F ***************************************** */
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/cc/c0f5544c4a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/cc/c0f5544c4a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..427990c
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/cc/c0f5544c4a2500111a3cc0d2fb41a96e
@@ -0,0 +1,324 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x05
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x01
+ ORRS r0, r0, r3
+ STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+ LDR r1, =GPIO_IDR
+ MOVS
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r2
+ EORS r0, r0, r3
+ STR r0, [r1, #0]
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/d/7043ed744a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/d/7043ed744a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..79bd4c6
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/d/7043ed744a2500111a3cc0d2fb41a96e
@@ -0,0 +1,323 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x05
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x01
+ ORRS r0, r0, r3
+ STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r2
+ EORS r0, r0, r3
+ STR r0, [r1, #0]
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/e2/a017bba74a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/e2/a017bba74a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..18f5745
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/e2/a017bba74a2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+# LDR r1, =GPIOA_MODER
+# MOVS r3, #0x05
+# LDR r0, [r1, #1]
+# BICS r0, r3
+# MOVS r3, #0x01
+# ORRS r0, r0, r3
+# STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/ee/803b95424a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/ee/803b95424a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..d543a66
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/ee/803b95424a2500111a3cc0d2fb41a96e
@@ -0,0 +1,315 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+ LDR r1, =GPIO_IDR
+ MOVS
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r2
+ STR r0, [r1, #0]
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.history/fd/505dbbb14a2500111a3cc0d2fb41a96e b/.metadata/.plugins/org.eclipse.core.resources/.history/fd/505dbbb14a2500111a3cc0d2fb41a96e
new file mode 100644
index 0000000..670e7cc
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.core.resources/.history/fd/505dbbb14a2500111a3cc0d2fb41a96e
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+ LDR r1, =GPIOA_MODER
+ MOVS r3, #0x05
+ LDR r0, [r1, #1]
+ BICS r0, r3
+ MOVS r3, #0x02
+ ORRS r0, r0, r3
+ STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r3
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.indexes/c4/history.index b/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.indexes/c4/history.index
deleted file mode 100644
index c936047..0000000
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.indexes/c4/history.index and /dev/null differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.markers b/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.markers
index f8efdb4..5ca87f5 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.markers and b/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.markers differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.markers.snap b/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.markers.snap
index 1b39a06..3d67e0c 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.markers.snap and b/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.markers.snap differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.syncinfo.snap b/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.syncinfo.snap
index 414a6b3..91d6c54 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.syncinfo.snap and b/.metadata/.plugins/org.eclipse.core.resources/.projects/task1/.syncinfo.snap differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.indexes/properties.index b/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.indexes/properties.index
index 755788d..17d2570 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.indexes/properties.index and b/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.indexes/properties.index differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.markers b/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.markers
new file mode 100644
index 0000000..e620ef2
Binary files /dev/null and b/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.markers differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.markers.snap b/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.markers.snap
index 414a6b3..91d6c54 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.markers.snap and b/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.markers.snap differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.syncinfo.snap b/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.syncinfo.snap
index 414a6b3..91d6c54 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.syncinfo.snap and b/.metadata/.plugins/org.eclipse.core.resources/.projects/task2/.syncinfo.snap differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.projects/task3/.markers.snap b/.metadata/.plugins/org.eclipse.core.resources/.projects/task3/.markers.snap
index 414a6b3..f0e29f0 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.projects/task3/.markers.snap and b/.metadata/.plugins/org.eclipse.core.resources/.projects/task3/.markers.snap differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.projects/task3/.syncinfo.snap b/.metadata/.plugins/org.eclipse.core.resources/.projects/task3/.syncinfo.snap
index 414a6b3..91d6c54 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.projects/task3/.syncinfo.snap and b/.metadata/.plugins/org.eclipse.core.resources/.projects/task3/.syncinfo.snap differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.projects/task4/.markers.snap b/.metadata/.plugins/org.eclipse.core.resources/.projects/task4/.markers.snap
index 414a6b3..c33c1fb 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.projects/task4/.markers.snap and b/.metadata/.plugins/org.eclipse.core.resources/.projects/task4/.markers.snap differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.projects/task4/.syncinfo.snap b/.metadata/.plugins/org.eclipse.core.resources/.projects/task4/.syncinfo.snap
index 414a6b3..91d6c54 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.projects/task4/.syncinfo.snap and b/.metadata/.plugins/org.eclipse.core.resources/.projects/task4/.syncinfo.snap differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index b/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index
index c1b33e4..d23ff58 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index and b/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.root/.markers b/.metadata/.plugins/org.eclipse.core.resources/.root/.markers
index 661c3b5..e1eb401 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.root/.markers and b/.metadata/.plugins/org.eclipse.core.resources/.root/.markers differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.root/.markers.snap b/.metadata/.plugins/org.eclipse.core.resources/.root/.markers.snap
index 414a6b3..171766e 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.root/.markers.snap and b/.metadata/.plugins/org.eclipse.core.resources/.root/.markers.snap differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.root/66.tree b/.metadata/.plugins/org.eclipse.core.resources/.root/67.tree
similarity index 62%
rename from .metadata/.plugins/org.eclipse.core.resources/.root/66.tree
rename to .metadata/.plugins/org.eclipse.core.resources/.root/67.tree
index a8bbfbf..4e78ca4 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.root/66.tree and b/.metadata/.plugins/org.eclipse.core.resources/.root/67.tree differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources b/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources
index d32477e..686256b 100644
Binary files a/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources and b/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/66.snap b/.metadata/.plugins/org.eclipse.core.resources/66.snap
deleted file mode 100644
index f42c958..0000000
Binary files a/.metadata/.plugins/org.eclipse.core.resources/66.snap and /dev/null differ
diff --git a/.metadata/.plugins/org.eclipse.core.resources/67.snap b/.metadata/.plugins/org.eclipse.core.resources/67.snap
new file mode 100644
index 0000000..a3f87c5
Binary files /dev/null and b/.metadata/.plugins/org.eclipse.core.resources/67.snap differ
diff --git a/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs b/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs
index 6f57bec..bff41cd 100644
--- a/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs
+++ b/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs
@@ -5,4 +5,4 @@
//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.remoteApplicationLaunchType=org.eclipse.rse.remotecdt.dsf.debug,debug,;
eclipse.preferences.version=1
org.eclipse.debug.core.PREF_DELETE_CONFIGS_ON_PROJECT_DELETE=false
-prefWatchExpressions=\r\n\r\n
+prefWatchExpressions=\n\n
diff --git a/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.launchbar.core.prefs b/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.launchbar.core.prefs
index 79b0632..995880c 100644
--- a/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.launchbar.core.prefs
+++ b/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.launchbar.core.prefs
@@ -1,7 +1,7 @@
LaunchTargetManager/org.eclipse.launchbar.core.launchTargetType.local,Local/arch=x86_64
LaunchTargetManager/org.eclipse.launchbar.core.launchTargetType.local,Local/name=Local
LaunchTargetManager/org.eclipse.launchbar.core.launchTargetType.local,Local/os=win32
-configDescList=org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:task3 Debug,org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:task3,org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:task4,org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:task2,org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:task1
+configDescList=org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:task3 Debug,org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:task3,org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:task4,org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:task1,org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:task2
eclipse.preferences.version=1
org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:A3_Timer/activeLaunchMode=run
org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:task1/activeLaunchMode=run
diff --git a/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs b/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs
index 3a0425b..d4a53bc 100644
--- a/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs
+++ b/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs
@@ -1,6 +1,6 @@
IMPORT_FILES_AND_FOLDERS_RELATIVE=true
IMPORT_FILES_AND_FOLDERS_TYPE=23,1
eclipse.preferences.version=1
-platformState=1772304866316
+platformState=1772304866322
quickStart=false
tipsAndTricks=true
diff --git a/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml b/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml
index 3a04ff5..c599879 100644
--- a/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml
+++ b/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml
@@ -2,8 +2,8 @@
-
+
@@ -24,8 +24,8 @@
-
+
diff --git a/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi b/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi
index a041b0b..977dc6b 100644
--- a/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi
+++ b/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi
@@ -1,8 +1,8 @@
-
-
+
+
activeSchemeId:org.eclipse.ui.defaultAcceleratorConfiguration
-
+
@@ -11,9 +11,9 @@
topLevel
shellMaximized
-
-
-
+
+
+
persp.actionSet:com.st.stm32cube.ide.mcu.informationcenter.actionSet3
persp.actionSet:org.eclipse.ui.cheatsheets.actionSet
@@ -67,70 +67,71 @@
persp.viewSC:com.st.stm32cube.ide.mcu.buildanalyzer.view
persp.viewSC:com.st.stm32cube.ide.mcu.stackanalyzer.stackanalyzer.view
persp.viewSC:com.st.stm32cube.ide.mcu.sfrview
-
-
-
+
+
+ active
+
View
categoryTag:General
-
+
View
categoryTag:C/C++
-
+
View
categoryTag:General
-
-
-
-
-
-
+
+
+
+
+
+
View
categoryTag:General
-
+
View
categoryTag:General
-
+
View
categoryTag:General
-
+
View
categoryTag:General
-
+
General
-
+
View
categoryTag:C/C++
-
+
View
categoryTag:C/C++
-
+
View
categoryTag:General
-
-
+
+
View
categoryTag:General
-
+
View
categoryTag:General
-
+
View
categoryTag:Make
@@ -138,7 +139,7 @@
-
+
persp.actionSet:com.st.stm32cube.ide.mcu.informationcenter.actionSet3
persp.actionSet:org.eclipse.ui.cheatsheets.actionSet
@@ -192,121 +193,121 @@
persp.editorOnboardingCommand:Step Over$$$F6
persp.editorOnboardingCommand:Step Return$$$F7
persp.editorOnboardingCommand:Resume$$$F8
-
-
-
+
+
+
org.eclipse.e4.primaryNavigationStack
-
+
View
categoryTag:Debug
-
+
View
categoryTag:General
-
-
+
+
View
categoryTag:Debug
-
-
-
-
+
+
+
+
org.eclipse.e4.secondaryNavigationStack
-
+
View
categoryTag:Debug
-
+
View
categoryTag:Debug
-
+
View
categoryTag:Debug
-
+
View
categoryTag:General
-
+
View
categoryTag:General
-
+
View
categoryTag:General
-
+
View
categoryTag:Debug
-
+
View
categoryTag:Debug
-
+
View
categoryTag:Debug
-
+
View
categoryTag:Debug
-
+
View
categoryTag:Debug
-
+
View
categoryTag:Debug
-
+
Debug
noFocus
-
+
View
categoryTag:General
-
+
View
categoryTag:General
-
+
View
categoryTag:General
-
+
View
categoryTag:General
-
+
View
categoryTag:General
-
+
View
categoryTag:Debug
-
+
View
categoryTag:Debug
-
+
View
categoryTag:Debug
-
+
View
categoryTag:Debug
-
+
View
categoryTag:Debug
@@ -315,2195 +316,2193 @@
-
-
+
+
View
categoryTag:Help
-
+
View
categoryTag:General
-
+
View
categoryTag:Help
-
+
View
categoryTag:Help
-
+
View
categoryTag:General
-
+
ViewMenu
menuContribution:menu
-
+
-
+
View
categoryTag:Help
-
-
+
+
org.eclipse.e4.primaryDataStack
EditorStack
- active
- noFocus
-
+
Editor
removeOnHide
org.eclipse.cdt.ui.editor.asm.AsmEditor
-
-
- Editor
- removeOnHide
- org.eclipse.cdt.ui.editor.CEditor
-
-
-
- Editor
- removeOnHide
- org.eclipse.cdt.ui.editor.CEditor
-
-
-
- Editor
- removeOnHide
- org.eclipse.cdt.ui.editor.CEditor
-
-
-
- Editor
- removeOnHide
- org.eclipse.cdt.ui.editor.CEditor
-
-
+
Editor
removeOnHide
org.eclipse.cdt.ui.editor.CEditor
-
-
+
+
+ Editor
+ removeOnHide
+ org.eclipse.cdt.ui.editor.asm.AsmEditor
+
+
+
+ Editor
+ removeOnHide
+ org.eclipse.cdt.ui.editor.asm.AsmEditor
+
+
+
+ Editor
+ removeOnHide
+ org.eclipse.ui.genericeditor.GenericEditor
+
+
+
+ Editor
+ removeOnHide
+ org.eclipse.cdt.ui.editor.asm.AsmEditor
+
+
+
Editor
removeOnHide
org.eclipse.cdt.ui.editor.asm.AsmEditor
- active
-
+
View
categoryTag:General
-
+ active
+
ViewMenu
menuContribution:menu
-
+
-
+
View
categoryTag:C/C++
-
+
View
categoryTag:General
-
+
-
+
View
categoryTag:General
-
+
ViewMenu
menuContribution:menu
-
+
-
+
View
categoryTag:General
-
+
ViewMenu
menuContribution:menu
-
+
-
+
View
categoryTag:General
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+
ViewMenu
menuContribution:menu
-
+
-
+
View
categoryTag:General
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+
ViewMenu
menuContribution:menu
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+
-
+
View
categoryTag:General
-
+
ViewMenu
menuContribution:menu
-
+
-
+
View
categoryTag:General
-
+
View
categoryTag:Make
-
+
ViewMenu
menuContribution:menu
-
+
-
+
View
categoryTag:C/C++
-
+
ViewMenu
menuContribution:menu
-
+
-
+
View
categoryTag:C/C++
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+
ViewMenu
menuContribution:menu
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+
-
+
View
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ViewMenu
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ViewMenu
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ViewMenu
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ViewMenu
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ViewMenu
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ViewMenu
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View
categoryTag:Debug
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View
categoryTag:Debug
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ViewMenu
menuContribution:menu
-
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-
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View
categoryTag:Debug
activeOnClose
-
+
ViewMenu
menuContribution:menu
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+
-
+
View
categoryTag:Debug
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ViewMenu
menuContribution:menu
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ViewMenu
menuContribution:menu
-
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toolbarSeparator
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toolbarSeparator
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Draggable
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toolbarSeparator
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Draggable
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Draggable
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Draggable
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toolbarSeparator
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Draggable
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toolbarSeparator
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toolbarSeparator
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SHOW_RESTORE_MENU
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stretch
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TrimStack
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diff --git a/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/task2/2026/3/13/refactorings.history b/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/task2/2026/3/13/refactorings.history
new file mode 100644
index 0000000..b384294
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/task2/2026/3/13/refactorings.history
@@ -0,0 +1,3 @@
+
+
+
\ No newline at end of file
diff --git a/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/task2/2026/3/13/refactorings.index b/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/task2/2026/3/13/refactorings.index
new file mode 100644
index 0000000..9ee7ec3
--- /dev/null
+++ b/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/task2/2026/3/13/refactorings.index
@@ -0,0 +1,2 @@
+1774358097434 Rename resource 'task2.s'
+1774358106409 Rename resource 'task2_efe.s'
diff --git a/.metadata/version.ini b/.metadata/version.ini
index 5a2a0e8..4ec6510 100644
--- a/.metadata/version.ini
+++ b/.metadata/version.ini
@@ -1,3 +1,3 @@
-#Fri Mar 20 18:06:30 CET 2026
+#Tue Mar 24 14:11:27 CET 2026
org.eclipse.core.runtime=2
org.eclipse.platform=4.30.0.v20231201-0110
diff --git a/Zusätliche Abgaben/Termin2.typ b/Zusätliche Abgaben/Termin2.typ
index afddcf6..0f86cb8 100644
--- a/Zusätliche Abgaben/Termin2.typ
+++ b/Zusätliche Abgaben/Termin2.typ
@@ -1,9 +1,17 @@
= 3.2 Aufgabe 2 - ASM: Interrupts, Entprellen
== Aufgabenstellung:
-Das Programm soll per Tastendruck den Zustand der LEDs wechseln. Taster *S-1* soll *LED0* und *LED3* ein-bzw. auschalten, Taster *S1 LED1* und *LED2*
+Das Programm soll per Tastendruck den Zustand der LEDs wechseln. Taster *S1* soll *LED0* und *LED3* ein-bzw. auschalten, Taster *S1 LED1* und *LED2*
== Vorbereitungsfragen:
=== a. Welche vier Einträge stehen am Beginn der ARM Exception Vector Table?
+#table(
+ columns: (1fr, auto, auto),
+ inset: 10pt,
+ align: horizon,
+ table.header(
+ [*Postion*], [*Vektor*], [*Beschreibung*]
+ ),
+ [0], [WWDG],
=== b. Wie viele Interrupt-Prioritätsstufen unterstützt ein ARM-Controller maximal?
=== c. An welchen Positionen in der Exception Vector Table stehen die Adressen der ISRs für die Tasten? (ST Dokumentation)
=== d. Schauen Sie sich das Prellen eines Tasters an und überlegen Sie sich eine Lösung.
-=== e. Erstellen Sie ein komplettes Flussdiagramm für Ihren Lösungsansatz.
\ No newline at end of file
+=== e. Erstellen Sie ein komplettes Flussdiagramm für Ihren Lösungsansatz.
diff --git a/task1/Debug/Src/task1.cyclo b/task1/Debug/Src/task1.cyclo
deleted file mode 100644
index fba7d9b..0000000
--- a/task1/Debug/Src/task1.cyclo
+++ /dev/null
@@ -1,3 +0,0 @@
-../Src/task1.c:53:5:main 14
-../Src/task1.c:157:13:GPIO_init 1
-../Src/task1.c:197:13:delay 6
diff --git a/task1/Debug/Src/task1.d b/task1/Debug/Src/task1.d
deleted file mode 100644
index 88b76a7..0000000
--- a/task1/Debug/Src/task1.d
+++ /dev/null
@@ -1,11 +0,0 @@
-Src/task1.o: ../Src/task1.c ../Inc/stm32g431xx.h ../Inc/core_cm4.h \
- ../Inc/cmsis_version.h ../Inc/cmsis_compiler.h ../Inc/cmsis_gcc.h \
- ../Inc/mpu_armv7.h ../Inc/system_stm32g4xx.h ../Inc/STefi-Light.h
-../Inc/stm32g431xx.h:
-../Inc/core_cm4.h:
-../Inc/cmsis_version.h:
-../Inc/cmsis_compiler.h:
-../Inc/cmsis_gcc.h:
-../Inc/mpu_armv7.h:
-../Inc/system_stm32g4xx.h:
-../Inc/STefi-Light.h:
diff --git a/task1/Debug/Src/task1.o b/task1/Debug/Src/task1.o
deleted file mode 100644
index ea0955b..0000000
Binary files a/task1/Debug/Src/task1.o and /dev/null differ
diff --git a/task1/Debug/Src/task1.su b/task1/Debug/Src/task1.su
deleted file mode 100644
index 92aa987..0000000
--- a/task1/Debug/Src/task1.su
+++ /dev/null
@@ -1,3 +0,0 @@
-../Src/task1.c:53:5:main 24 static,ignoring_inline_asm
-../Src/task1.c:157:13:GPIO_init 4 static
-../Src/task1.c:197:13:delay 24 static,ignoring_inline_asm
diff --git a/task1/Debug/Src/task1_it.cyclo b/task1/Debug/Src/task1_it.cyclo
deleted file mode 100644
index 98e7272..0000000
--- a/task1/Debug/Src/task1_it.cyclo
+++ /dev/null
@@ -1,2 +0,0 @@
-../Src/task1_it.c:56:6:ISR_error 1
-../Src/task1_it.c:76:6:ISR_default 1
diff --git a/task1/Debug/Src/task1_it.d b/task1/Debug/Src/task1_it.d
deleted file mode 100644
index 77538df..0000000
--- a/task1/Debug/Src/task1_it.d
+++ /dev/null
@@ -1,11 +0,0 @@
-Src/task1_it.o: ../Src/task1_it.c ../Inc/stm32g431xx.h ../Inc/core_cm4.h \
- ../Inc/cmsis_version.h ../Inc/cmsis_compiler.h ../Inc/cmsis_gcc.h \
- ../Inc/mpu_armv7.h ../Inc/system_stm32g4xx.h ../Inc/STefi-Light.h
-../Inc/stm32g431xx.h:
-../Inc/core_cm4.h:
-../Inc/cmsis_version.h:
-../Inc/cmsis_compiler.h:
-../Inc/cmsis_gcc.h:
-../Inc/mpu_armv7.h:
-../Inc/system_stm32g4xx.h:
-../Inc/STefi-Light.h:
diff --git a/task1/Debug/Src/task1_it.o b/task1/Debug/Src/task1_it.o
deleted file mode 100644
index 21c0e1e..0000000
Binary files a/task1/Debug/Src/task1_it.o and /dev/null differ
diff --git a/task1/Debug/Src/task1_it.su b/task1/Debug/Src/task1_it.su
deleted file mode 100644
index e608c86..0000000
--- a/task1/Debug/Src/task1_it.su
+++ /dev/null
@@ -1,2 +0,0 @@
-../Src/task1_it.c:56:6:ISR_error 4 static
-../Src/task1_it.c:76:6:ISR_default 4 static
diff --git a/task1/Debug/Startup/startup_stm32g431kbtx.d b/task1/Debug/Startup/startup_stm32g431kbtx.d
deleted file mode 100644
index 11b27a3..0000000
--- a/task1/Debug/Startup/startup_stm32g431kbtx.d
+++ /dev/null
@@ -1 +0,0 @@
-Startup/startup_stm32g431kbtx.o: ../Startup/startup_stm32g431kbtx.s
diff --git a/task1/Debug/Startup/startup_stm32g431kbtx.o b/task1/Debug/Startup/startup_stm32g431kbtx.o
deleted file mode 100644
index c80d4e0..0000000
Binary files a/task1/Debug/Startup/startup_stm32g431kbtx.o and /dev/null differ
diff --git a/task1/Debug/Startup/syscalls.cyclo b/task1/Debug/Startup/syscalls.cyclo
deleted file mode 100644
index d5a22f4..0000000
--- a/task1/Debug/Startup/syscalls.cyclo
+++ /dev/null
@@ -1,18 +0,0 @@
-../Startup/syscalls.c:44:6:initialise_monitor_handles 1
-../Startup/syscalls.c:48:5:_getpid 1
-../Startup/syscalls.c:53:5:_kill 1
-../Startup/syscalls.c:61:6:_exit 1
-../Startup/syscalls.c:67:27:_read 2
-../Startup/syscalls.c:80:27:_write 2
-../Startup/syscalls.c:92:5:_close 1
-../Startup/syscalls.c:99:5:_fstat 1
-../Startup/syscalls.c:106:5:_isatty 1
-../Startup/syscalls.c:112:5:_lseek 1
-../Startup/syscalls.c:120:5:_open 1
-../Startup/syscalls.c:128:5:_wait 1
-../Startup/syscalls.c:135:5:_unlink 1
-../Startup/syscalls.c:142:5:_times 1
-../Startup/syscalls.c:148:5:_stat 1
-../Startup/syscalls.c:155:5:_link 1
-../Startup/syscalls.c:163:5:_fork 1
-../Startup/syscalls.c:169:5:_execve 1
diff --git a/task1/Debug/Startup/syscalls.d b/task1/Debug/Startup/syscalls.d
deleted file mode 100644
index 1c09811..0000000
--- a/task1/Debug/Startup/syscalls.d
+++ /dev/null
@@ -1 +0,0 @@
-Startup/syscalls.o: ../Startup/syscalls.c
diff --git a/task1/Debug/Startup/syscalls.o b/task1/Debug/Startup/syscalls.o
deleted file mode 100644
index 55d03fe..0000000
Binary files a/task1/Debug/Startup/syscalls.o and /dev/null differ
diff --git a/task1/Debug/Startup/syscalls.su b/task1/Debug/Startup/syscalls.su
deleted file mode 100644
index db376b7..0000000
--- a/task1/Debug/Startup/syscalls.su
+++ /dev/null
@@ -1,18 +0,0 @@
-../Startup/syscalls.c:44:6:initialise_monitor_handles 4 static
-../Startup/syscalls.c:48:5:_getpid 4 static
-../Startup/syscalls.c:53:5:_kill 16 static
-../Startup/syscalls.c:61:6:_exit 16 static
-../Startup/syscalls.c:67:27:_read 32 static
-../Startup/syscalls.c:80:27:_write 32 static
-../Startup/syscalls.c:92:5:_close 16 static
-../Startup/syscalls.c:99:5:_fstat 16 static
-../Startup/syscalls.c:106:5:_isatty 16 static
-../Startup/syscalls.c:112:5:_lseek 24 static
-../Startup/syscalls.c:120:5:_open 12 static
-../Startup/syscalls.c:128:5:_wait 16 static
-../Startup/syscalls.c:135:5:_unlink 16 static
-../Startup/syscalls.c:142:5:_times 16 static
-../Startup/syscalls.c:148:5:_stat 16 static
-../Startup/syscalls.c:155:5:_link 16 static
-../Startup/syscalls.c:163:5:_fork 8 static
-../Startup/syscalls.c:169:5:_execve 24 static
diff --git a/task1/Debug/Startup/sysmem.cyclo b/task1/Debug/Startup/sysmem.cyclo
deleted file mode 100644
index 4092bc6..0000000
--- a/task1/Debug/Startup/sysmem.cyclo
+++ /dev/null
@@ -1 +0,0 @@
-../Startup/sysmem.c:53:7:_sbrk 3
diff --git a/task1/Debug/Startup/sysmem.d b/task1/Debug/Startup/sysmem.d
deleted file mode 100644
index 17ffda1..0000000
--- a/task1/Debug/Startup/sysmem.d
+++ /dev/null
@@ -1 +0,0 @@
-Startup/sysmem.o: ../Startup/sysmem.c
diff --git a/task1/Debug/Startup/sysmem.o b/task1/Debug/Startup/sysmem.o
deleted file mode 100644
index c167de8..0000000
Binary files a/task1/Debug/Startup/sysmem.o and /dev/null differ
diff --git a/task1/Debug/Startup/sysmem.su b/task1/Debug/Startup/sysmem.su
deleted file mode 100644
index 718d300..0000000
--- a/task1/Debug/Startup/sysmem.su
+++ /dev/null
@@ -1 +0,0 @@
-../Startup/sysmem.c:53:7:_sbrk 32 static
diff --git a/task1/Debug/task1.elf b/task1/Debug/task1.elf
deleted file mode 100755
index c3d2c10..0000000
Binary files a/task1/Debug/task1.elf and /dev/null differ
diff --git a/task1/Debug/task1.list b/task1/Debug/task1.list
deleted file mode 100644
index da448ba..0000000
--- a/task1/Debug/task1.list
+++ /dev/null
@@ -1,764 +0,0 @@
-
-task1.elf: file format elf32-littlearm
-
-Sections:
-Idx Name Size VMA LMA File off Algn
- 0 .isr_vector 000001d8 08000000 08000000 00001000 2**2
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 1 .text 000004bc 080001d8 080001d8 000011d8 2**2
- CONTENTS, ALLOC, LOAD, READONLY, CODE
- 2 .rodata 00000000 08000694 0800069c 0000169c 2**0
- CONTENTS, ALLOC, LOAD, DATA
- 3 .ARM.extab 00000000 08000694 08000694 0000169c 2**0
- CONTENTS
- 4 .ARM 00000000 08000694 08000694 0000169c 2**0
- CONTENTS
- 5 .preinit_array 00000000 08000694 0800069c 0000169c 2**0
- CONTENTS, ALLOC, LOAD, DATA
- 6 .init_array 00000004 08000694 08000694 00001694 2**2
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 7 .fini_array 00000004 08000698 08000698 00001698 2**2
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 8 .data 00000000 20000000 20000000 0000169c 2**0
- CONTENTS, ALLOC, LOAD, DATA
- 9 .ccmsram 00000000 10000000 10000000 0000169c 2**0
- CONTENTS
- 10 .bss 00000020 20000000 20000000 00002000 2**2
- ALLOC
- 11 ._user_heap_stack 00000600 20000020 20000020 00002000 2**0
- ALLOC
- 12 .ARM.attributes 00000030 00000000 00000000 0000169c 2**0
- CONTENTS, READONLY
- 13 .debug_info 000007eb 00000000 00000000 000016cc 2**0
- CONTENTS, READONLY, DEBUGGING, OCTETS
- 14 .debug_abbrev 00000296 00000000 00000000 00001eb7 2**0
- CONTENTS, READONLY, DEBUGGING, OCTETS
- 15 .debug_aranges 00000078 00000000 00000000 00002150 2**3
- CONTENTS, READONLY, DEBUGGING, OCTETS
- 16 .debug_rnglists 0000003a 00000000 00000000 000021c8 2**0
- CONTENTS, READONLY, DEBUGGING, OCTETS
- 17 .debug_macro 00013740 00000000 00000000 00002202 2**0
- CONTENTS, READONLY, DEBUGGING, OCTETS
- 18 .debug_line 00000a3e 00000000 00000000 00015942 2**0
- CONTENTS, READONLY, DEBUGGING, OCTETS
- 19 .debug_str 0006f831 00000000 00000000 00016380 2**0
- CONTENTS, READONLY, DEBUGGING, OCTETS
- 20 .comment 00000043 00000000 00000000 00085bb1 2**0
- CONTENTS, READONLY
- 21 .debug_frame 000000e4 00000000 00000000 00085bf4 2**2
- CONTENTS, READONLY, DEBUGGING, OCTETS
- 22 .debug_line_str 0000007a 00000000 00000000 00085cd8 2**0
- CONTENTS, READONLY, DEBUGGING, OCTETS
-
-Disassembly of section .text:
-
-080001d8 <__do_global_dtors_aux>:
- 80001d8: b510 push {r4, lr}
- 80001da: 4c05 ldr r4, [pc, #20] @ (80001f0 <__do_global_dtors_aux+0x18>)
- 80001dc: 7823 ldrb r3, [r4, #0]
- 80001de: b933 cbnz r3, 80001ee <__do_global_dtors_aux+0x16>
- 80001e0: 4b04 ldr r3, [pc, #16] @ (80001f4 <__do_global_dtors_aux+0x1c>)
- 80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x12>
- 80001e4: 4804 ldr r0, [pc, #16] @ (80001f8 <__do_global_dtors_aux+0x20>)
- 80001e6: f3af 8000 nop.w
- 80001ea: 2301 movs r3, #1
- 80001ec: 7023 strb r3, [r4, #0]
- 80001ee: bd10 pop {r4, pc}
- 80001f0: 20000000 .word 0x20000000
- 80001f4: 00000000 .word 0x00000000
- 80001f8: 0800067c .word 0x0800067c
-
-080001fc :
- 80001fc: b508 push {r3, lr}
- 80001fe: 4b03 ldr r3, [pc, #12] @ (800020c )
- 8000200: b11b cbz r3, 800020a
- 8000202: 4903 ldr r1, [pc, #12] @ (8000210 )
- 8000204: 4803 ldr r0, [pc, #12] @ (8000214 )
- 8000206: f3af 8000 nop.w
- 800020a: bd08 pop {r3, pc}
- 800020c: 00000000 .word 0x00000000
- 8000210: 20000004 .word 0x20000004
- 8000214: 0800067c .word 0x0800067c
-
-08000218 :
-static void GPIO_init(void);
-static void delay(const uint16_t ms);
-
-/* ------------------------------------ M A I N --------------------------------------- */
-int main(void)
-{
- 8000218: b580 push {r7, lr}
- 800021a: b084 sub sp, #16
- 800021c: af00 add r7, sp, #0
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
- 800021e: b672 cpsid i
-}
- 8000220: bf00 nop
- /* --- initialization --- */
- __disable_irq(); // disable interrupts globally
-
- GPIO_init();
- 8000222: f000 f8e9 bl 80003f8
- __ASM volatile ("cpsie i" : : : "memory");
- 8000226: b662 cpsie i
-}
- 8000228: bf00 nop
- __enable_irq(); // enable interrupts globally
-
- /* --- one time tasks --- */
-
- //s0 Hilfvariablen auserhalb von while deklarieren
- int running = 0; //0 Lauflicht aus, 1 Lauflicht an
- 800022a: 2300 movs r3, #0
- 800022c: 60fb str r3, [r7, #12]
- int lastButtonState = 1; // Hilfsvariable zur Flankenerkennung
- 800022e: 2301 movs r3, #1
- 8000230: 60bb str r3, [r7, #8]
-
- /* --- infinite processing loop --- */
- while (1)
- {
- int buttonState = GPIOB->IDR & (1 << 0);
- 8000232: 4b6f ldr r3, [pc, #444] @ (80003f0 )
- 8000234: 691b ldr r3, [r3, #16]
- 8000236: f003 0301 and.w r3, r3, #1
- 800023a: 607b str r3, [r7, #4]
-
- // fallende Flanke erkennen
- if (lastButtonState && !buttonState)
- 800023c: 68bb ldr r3, [r7, #8]
- 800023e: 2b00 cmp r3, #0
- 8000240: d006 beq.n 8000250
- 8000242: 687b ldr r3, [r7, #4]
- 8000244: 2b00 cmp r3, #0
- 8000246: d103 bne.n 8000250
- {
- running ^= 1; // toggle running
- 8000248: 68fb ldr r3, [r7, #12]
- 800024a: f083 0301 eor.w r3, r3, #1
- 800024e: 60fb str r3, [r7, #12]
- /* delay(50); // entprellen */
- }
-
- lastButtonState = buttonState;
- 8000250: 687b ldr r3, [r7, #4]
- 8000252: 60bb str r3, [r7, #8]
-
-
- if(running)
- 8000254: 68fb ldr r3, [r7, #12]
- 8000256: 2b00 cmp r3, #0
- 8000258: d0eb beq.n 8000232
- {
- switch (state)
- 800025a: 4b66 ldr r3, [pc, #408] @ (80003f4 )
- 800025c: 681b ldr r3, [r3, #0]
- 800025e: 2b05 cmp r3, #5
- 8000260: dc12 bgt.n 8000288
- 8000262: 2b00 cmp r3, #0
- 8000264: dbe5 blt.n 8000232
- 8000266: 2b05 cmp r3, #5
- 8000268: d8e3 bhi.n 8000232
- 800026a: a201 add r2, pc, #4 @ (adr r2, 8000270 )
- 800026c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8000270: 08000291 .word 0x08000291
- 8000274: 080002c5 .word 0x080002c5
- 8000278: 080002f9 .word 0x080002f9
- 800027c: 0800032d .word 0x0800032d
- 8000280: 08000361 .word 0x08000361
- 8000284: 08000395 .word 0x08000395
- 8000288: 2b63 cmp r3, #99 @ 0x63
- 800028a: f000 809b beq.w 80003c4
- 800028e: e0ad b.n 80003ec
- {
- case 0:
- state++;
- 8000290: 4b58 ldr r3, [pc, #352] @ (80003f4 )
- 8000292: 681b ldr r3, [r3, #0]
- 8000294: 3301 adds r3, #1
- 8000296: 4a57 ldr r2, [pc, #348] @ (80003f4 )
- 8000298: 6013 str r3, [r2, #0]
- GPIOA->ODR &= ~(1 << 0);
- 800029a: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 800029e: 695b ldr r3, [r3, #20]
- 80002a0: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 80002a4: f023 0301 bic.w r3, r3, #1
- 80002a8: 6153 str r3, [r2, #20]
- delay(WAITTIME);
- 80002aa: f240 104d movw r0, #333 @ 0x14d
- 80002ae: f000 f915 bl 80004dc
- GPIOA->ODR |= (1 << 0);
- 80002b2: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 80002b6: 695b ldr r3, [r3, #20]
- 80002b8: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 80002bc: f043 0301 orr.w r3, r3, #1
- 80002c0: 6153 str r3, [r2, #20]
- break;
- 80002c2: e093 b.n 80003ec
- case 1:
- state++;
- 80002c4: 4b4b ldr r3, [pc, #300] @ (80003f4 )
- 80002c6: 681b ldr r3, [r3, #0]
- 80002c8: 3301 adds r3, #1
- 80002ca: 4a4a ldr r2, [pc, #296] @ (80003f4 )
- 80002cc: 6013 str r3, [r2, #0]
- GPIOA->ODR &= ~(1 << 1);
- 80002ce: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 80002d2: 695b ldr r3, [r3, #20]
- 80002d4: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 80002d8: f023 0302 bic.w r3, r3, #2
- 80002dc: 6153 str r3, [r2, #20]
- delay(WAITTIME);
- 80002de: f240 104d movw r0, #333 @ 0x14d
- 80002e2: f000 f8fb bl 80004dc
- GPIOA->ODR |= (1 << 1);
- 80002e6: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 80002ea: 695b ldr r3, [r3, #20]
- 80002ec: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 80002f0: f043 0302 orr.w r3, r3, #2
- 80002f4: 6153 str r3, [r2, #20]
- break;
- 80002f6: e079 b.n 80003ec
- case 2:
- state++;
- 80002f8: 4b3e ldr r3, [pc, #248] @ (80003f4 )
- 80002fa: 681b ldr r3, [r3, #0]
- 80002fc: 3301 adds r3, #1
- 80002fe: 4a3d ldr r2, [pc, #244] @ (80003f4 )
- 8000300: 6013 str r3, [r2, #0]
- GPIOA->ODR &= ~(1 << 2);
- 8000302: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000306: 695b ldr r3, [r3, #20]
- 8000308: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 800030c: f023 0304 bic.w r3, r3, #4
- 8000310: 6153 str r3, [r2, #20]
- delay(WAITTIME);
- 8000312: f240 104d movw r0, #333 @ 0x14d
- 8000316: f000 f8e1 bl 80004dc
- GPIOA->ODR |= (1 << 2);
- 800031a: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 800031e: 695b ldr r3, [r3, #20]
- 8000320: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 8000324: f043 0304 orr.w r3, r3, #4
- 8000328: 6153 str r3, [r2, #20]
- break;
- 800032a: e05f b.n 80003ec
- case 3:
- state++;
- 800032c: 4b31 ldr r3, [pc, #196] @ (80003f4 )
- 800032e: 681b ldr r3, [r3, #0]
- 8000330: 3301 adds r3, #1
- 8000332: 4a30 ldr r2, [pc, #192] @ (80003f4 )
- 8000334: 6013 str r3, [r2, #0]
- GPIOA->ODR &= ~(1 << 3);
- 8000336: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 800033a: 695b ldr r3, [r3, #20]
- 800033c: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 8000340: f023 0308 bic.w r3, r3, #8
- 8000344: 6153 str r3, [r2, #20]
- delay(WAITTIME);
- 8000346: f240 104d movw r0, #333 @ 0x14d
- 800034a: f000 f8c7 bl 80004dc
- GPIOA->ODR |= (1 << 3);
- 800034e: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000352: 695b ldr r3, [r3, #20]
- 8000354: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 8000358: f043 0308 orr.w r3, r3, #8
- 800035c: 6153 str r3, [r2, #20]
- break;
- 800035e: e045 b.n 80003ec
- case 4:
- state++;
- 8000360: 4b24 ldr r3, [pc, #144] @ (80003f4 )
- 8000362: 681b ldr r3, [r3, #0]
- 8000364: 3301 adds r3, #1
- 8000366: 4a23 ldr r2, [pc, #140] @ (80003f4 )
- 8000368: 6013 str r3, [r2, #0]
- GPIOA->ODR &= ~(1 << 2);
- 800036a: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 800036e: 695b ldr r3, [r3, #20]
- 8000370: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 8000374: f023 0304 bic.w r3, r3, #4
- 8000378: 6153 str r3, [r2, #20]
- delay(WAITTIME);
- 800037a: f240 104d movw r0, #333 @ 0x14d
- 800037e: f000 f8ad bl 80004dc
- GPIOA->ODR |= (1 << 2);
- 8000382: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000386: 695b ldr r3, [r3, #20]
- 8000388: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 800038c: f043 0304 orr.w r3, r3, #4
- 8000390: 6153 str r3, [r2, #20]
- break;
- 8000392: e02b b.n 80003ec
- case 5:
- state=0;
- 8000394: 4b17 ldr r3, [pc, #92] @ (80003f4 )
- 8000396: 2200 movs r2, #0
- 8000398: 601a str r2, [r3, #0]
- GPIOA->ODR &= ~(1 << 1);
- 800039a: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 800039e: 695b ldr r3, [r3, #20]
- 80003a0: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 80003a4: f023 0302 bic.w r3, r3, #2
- 80003a8: 6153 str r3, [r2, #20]
- delay(WAITTIME);
- 80003aa: f240 104d movw r0, #333 @ 0x14d
- 80003ae: f000 f895 bl 80004dc
- GPIOA->ODR |= (1 << 1);
- 80003b2: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 80003b6: 695b ldr r3, [r3, #20]
- 80003b8: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 80003bc: f043 0302 orr.w r3, r3, #2
- 80003c0: 6153 str r3, [r2, #20]
- break;
- 80003c2: e013 b.n 80003ec
-
- case 99:
- GPIOA->ODR |= MASK_LED_ALL;
- 80003c4: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 80003c8: 695b ldr r3, [r3, #20]
- 80003ca: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 80003ce: f043 030f orr.w r3, r3, #15
- 80003d2: 6153 str r3, [r2, #20]
- while(1){
- if((GPIOB->IDR & (1 << 0)) == 0){
- 80003d4: 4b06 ldr r3, [pc, #24] @ (80003f0 )
- 80003d6: 691b ldr r3, [r3, #16]
- 80003d8: f003 0301 and.w r3, r3, #1
- 80003dc: 2b00 cmp r3, #0
- 80003de: d1f9 bne.n 80003d4
- delay(150);
- 80003e0: 2096 movs r0, #150 @ 0x96
- 80003e2: f000 f87b bl 80004dc
- state=0;
- 80003e6: 4b03 ldr r3, [pc, #12] @ (80003f4 )
- 80003e8: 2200 movs r2, #0
- 80003ea: 601a str r2, [r3, #0]
- {
- 80003ec: e721 b.n 8000232
- 80003ee: bf00 nop
- 80003f0: 48000400 .word 0x48000400
- 80003f4: 2000001c .word 0x2000001c
-
-080003f8 :
- * requires: - nothing -
- * parameters: - none -
- * returns: - nothing -
- \* ------------------------------------------------------------------------------------ */
-static void GPIO_init(void)
-{
- 80003f8: b480 push {r7}
- 80003fa: af00 add r7, sp, #0
-/* enable port clocks */
-RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN; // LEDs: A
- 80003fc: 4b35 ldr r3, [pc, #212] @ (80004d4 )
- 80003fe: 6cdb ldr r3, [r3, #76] @ 0x4c
- 8000400: 4a34 ldr r2, [pc, #208] @ (80004d4 )
- 8000402: f043 0301 orr.w r3, r3, #1
- 8000406: 64d3 str r3, [r2, #76] @ 0x4c
-RCC->AHB2ENR |= RCC_AHB2ENR_GPIOBEN; //Taster versuch
- 8000408: 4b32 ldr r3, [pc, #200] @ (80004d4 )
- 800040a: 6cdb ldr r3, [r3, #76] @ 0x4c
- 800040c: 4a31 ldr r2, [pc, #196] @ (80004d4 )
- 800040e: f043 0302 orr.w r3, r3, #2
- 8000412: 64d3 str r3, [r2, #76] @ 0x4c
-
-/* --- LEDs --- */
-GPIOA->ODR |= MASK_LED_ALL;
- 8000414: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000418: 695b ldr r3, [r3, #20]
- 800041a: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 800041e: f043 030f orr.w r3, r3, #15
- 8000422: 6153 str r3, [r2, #20]
-GPIOA->MODER &= ~(3 << 0);
- 8000424: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000428: 681b ldr r3, [r3, #0]
- 800042a: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 800042e: f023 0303 bic.w r3, r3, #3
- 8000432: 6013 str r3, [r2, #0]
-GPIOA->MODER |= (1 << 0); // set LED pin to output
- 8000434: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000438: 681b ldr r3, [r3, #0]
- 800043a: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 800043e: f043 0301 orr.w r3, r3, #1
- 8000442: 6013 str r3, [r2, #0]
-
-/* LED1 als Output */
-GPIOA->MODER &= ~(3 << 2); // Versuch: LED 1 Mode löschen :klappt so
- 8000444: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000448: 681b ldr r3, [r3, #0]
- 800044a: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 800044e: f023 030c bic.w r3, r3, #12
- 8000452: 6013 str r3, [r2, #0]
-GPIOA->MODER |= (1 << 2); // Versuch: LED 1 PA1 = output :klappt so
- 8000454: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000458: 681b ldr r3, [r3, #0]
- 800045a: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 800045e: f043 0304 orr.w r3, r3, #4
- 8000462: 6013 str r3, [r2, #0]
-
-/* LED2 als Output */
-GPIOA->MODER &= ~(3 << 4); // Versuch: LED 2 Mode löschen :klappt
- 8000464: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000468: 681b ldr r3, [r3, #0]
- 800046a: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 800046e: f023 0330 bic.w r3, r3, #48 @ 0x30
- 8000472: 6013 str r3, [r2, #0]
-GPIOA->MODER |= (1 << 4); // Versuch: LED 2 PA1 = output :klappt
- 8000474: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000478: 681b ldr r3, [r3, #0]
- 800047a: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 800047e: f043 0310 orr.w r3, r3, #16
- 8000482: 6013 str r3, [r2, #0]
-
-/* LED3 als output */
-GPIOA->MODER &= ~(3 << 6);
- 8000484: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000488: 681b ldr r3, [r3, #0]
- 800048a: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 800048e: f023 03c0 bic.w r3, r3, #192 @ 0xc0
- 8000492: 6013 str r3, [r2, #0]
-GPIOA->MODER |= (1 << 6);
- 8000494: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000498: 681b ldr r3, [r3, #0]
- 800049a: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 800049e: f043 0340 orr.w r3, r3, #64 @ 0x40
- 80004a2: 6013 str r3, [r2, #0]
-
-/* s0 (PB0) als Input Versuch */
-GPIOB->MODER &= ~(3 << 0);
- 80004a4: 4b0c ldr r3, [pc, #48] @ (80004d8 )
- 80004a6: 681b ldr r3, [r3, #0]
- 80004a8: 4a0b ldr r2, [pc, #44] @ (80004d8 )
- 80004aa: f023 0303 bic.w r3, r3, #3
- 80004ae: 6013 str r3, [r2, #0]
-
-/* Pull-Up Aktivieren Versuch */
-GPIOB->PUPDR &= ~(3 << 0);
- 80004b0: 4b09 ldr r3, [pc, #36] @ (80004d8 )
- 80004b2: 68db ldr r3, [r3, #12]
- 80004b4: 4a08 ldr r2, [pc, #32] @ (80004d8 )
- 80004b6: f023 0303 bic.w r3, r3, #3
- 80004ba: 60d3 str r3, [r2, #12]
-GPIOB->PUPDR |= (1 << 0); // 01 = Pull-Up
- 80004bc: 4b06 ldr r3, [pc, #24] @ (80004d8 )
- 80004be: 68db ldr r3, [r3, #12]
- 80004c0: 4a05 ldr r2, [pc, #20] @ (80004d8 )
- 80004c2: f043 0301 orr.w r3, r3, #1
- 80004c6: 60d3 str r3, [r2, #12]
-}
- 80004c8: bf00 nop
- 80004ca: 46bd mov sp, r7
- 80004cc: f85d 7b04 ldr.w r7, [sp], #4
- 80004d0: 4770 bx lr
- 80004d2: bf00 nop
- 80004d4: 40021000 .word 0x40021000
- 80004d8: 48000400 .word 0x48000400
-
-080004dc :
- * requires: - nothing -
- * parameters: ms - delay time in milliseconds
- * returns: - nothing -
- \* ------------------------------------------------------------------------------------ */
-static void delay(const uint16_t ms)
-{
- 80004dc: b480 push {r7}
- 80004de: b085 sub sp, #20
- 80004e0: af00 add r7, sp, #0
- 80004e2: 4603 mov r3, r0
- 80004e4: 80fb strh r3, [r7, #6]
-for (uint16_t i = 0; i < ms; ++i)
- 80004e6: 2300 movs r3, #0
- 80004e8: 81fb strh r3, [r7, #14]
- 80004ea: e021 b.n 8000530
-{
- if((GPIOB->IDR & (1 << 0) && state != 99) == 0){
- 80004ec: 4b16 ldr r3, [pc, #88] @ (8000548 )
- 80004ee: 691b ldr r3, [r3, #16]
- 80004f0: f003 0301 and.w r3, r3, #1
- 80004f4: 2b00 cmp r3, #0
- 80004f6: d005 beq.n 8000504
- 80004f8: 4b14 ldr r3, [pc, #80] @ (800054c )
- 80004fa: 681b ldr r3, [r3, #0]
- 80004fc: 2b63 cmp r3, #99 @ 0x63
- 80004fe: d001 beq.n 8000504
- 8000500: 2301 movs r3, #1
- 8000502: e000 b.n 8000506
- 8000504: 2300 movs r3, #0
- 8000506: 2b00 cmp r3, #0
- 8000508: d103 bne.n 8000512
- state = 99;
- 800050a: 4b10 ldr r3, [pc, #64] @ (800054c )
- 800050c: 2263 movs r2, #99 @ 0x63
- 800050e: 601a str r2, [r3, #0]
- break;
- 8000510: e013 b.n 800053a
- }
- for (uint16_t j = 0; j < LOOPS_PER_MS; ++j)
- 8000512: 2300 movs r3, #0
- 8000514: 81bb strh r3, [r7, #12]
- 8000516: e003 b.n 8000520
- {
- __asm("NOP");
- 8000518: bf00 nop
- for (uint16_t j = 0; j < LOOPS_PER_MS; ++j)
- 800051a: 89bb ldrh r3, [r7, #12]
- 800051c: 3301 adds r3, #1
- 800051e: 81bb strh r3, [r7, #12]
- 8000520: 89bb ldrh r3, [r7, #12]
- 8000522: f240 42db movw r2, #1243 @ 0x4db
- 8000526: 4293 cmp r3, r2
- 8000528: d9f6 bls.n 8000518
-for (uint16_t i = 0; i < ms; ++i)
- 800052a: 89fb ldrh r3, [r7, #14]
- 800052c: 3301 adds r3, #1
- 800052e: 81fb strh r3, [r7, #14]
- 8000530: 89fa ldrh r2, [r7, #14]
- 8000532: 88fb ldrh r3, [r7, #6]
- 8000534: 429a cmp r2, r3
- 8000536: d3d9 bcc.n 80004ec
- }
-}
-}
- 8000538: bf00 nop
- 800053a: bf00 nop
- 800053c: 3714 adds r7, #20
- 800053e: 46bd mov sp, r7
- 8000540: f85d 7b04 ldr.w r7, [sp], #4
- 8000544: 4770 bx lr
- 8000546: bf00 nop
- 8000548: 48000400 .word 0x48000400
- 800054c: 2000001c .word 0x2000001c
-
-08000550 :
- *
- * Default interrupt handler for core interrupts.
- * Enables the green and red LED on the STefi Light board.
-\* ------------------------------------------------------------------------------------ */
-void ISR_error(void)
-{
- 8000550: b480 push {r7}
- 8000552: af00 add r7, sp, #0
- /* init */
- RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN; // PA: clock on (LEDs)
- 8000554: 4b10 ldr r3, [pc, #64] @ (8000598 )
- 8000556: 6cdb ldr r3, [r3, #76] @ 0x4c
- 8000558: 4a0f ldr r2, [pc, #60] @ (8000598 )
- 800055a: f043 0301 orr.w r3, r3, #1
- 800055e: 64d3 str r3, [r2, #76] @ 0x4c
- GPIOA->ODR |= MASK_LED_ALL;
- 8000560: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000564: 695b ldr r3, [r3, #20]
- 8000566: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 800056a: f043 030f orr.w r3, r3, #15
- 800056e: 6153 str r3, [r2, #20]
- GPIOA->MODER = (GPIOA->MODER & 0xFFFFFF00) | 0x11;
- 8000570: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000574: 681b ldr r3, [r3, #0]
- 8000576: f023 03ff bic.w r3, r3, #255 @ 0xff
- 800057a: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 800057e: f043 0311 orr.w r3, r3, #17
- 8000582: 6013 str r3, [r2, #0]
-
- while(1)
- { /* light up the LEDs permanently */
- GPIOA->ODR &= ~(MASK_LED_GREEN | MASK_LED_RED);
- 8000584: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 8000588: 695b ldr r3, [r3, #20]
- 800058a: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 800058e: f023 0305 bic.w r3, r3, #5
- 8000592: 6153 str r3, [r2, #20]
- 8000594: e7f6 b.n 8000584
- 8000596: bf00 nop
- 8000598: 40021000 .word 0x40021000
-
-0800059c :
- *
- * Default interrupt handler for non-core interrupts.
- * Enables the blue and yellow LED on the STefi Light board.
-\* ------------------------------------------------------------------------------------ */
-void ISR_default(void)
-{
- 800059c: b480 push {r7}
- 800059e: af00 add r7, sp, #0
- /* init */
- RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN; // PA: clock on (LEDs)
- 80005a0: 4b10 ldr r3, [pc, #64] @ (80005e4 )
- 80005a2: 6cdb ldr r3, [r3, #76] @ 0x4c
- 80005a4: 4a0f ldr r2, [pc, #60] @ (80005e4 )
- 80005a6: f043 0301 orr.w r3, r3, #1
- 80005aa: 64d3 str r3, [r2, #76] @ 0x4c
- GPIOA->ODR |= MASK_LED_ALL;
- 80005ac: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 80005b0: 695b ldr r3, [r3, #20]
- 80005b2: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 80005b6: f043 030f orr.w r3, r3, #15
- 80005ba: 6153 str r3, [r2, #20]
- GPIOA->MODER = (GPIOA->MODER & 0xFFFFFF00) | 0x44;
- 80005bc: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 80005c0: 681b ldr r3, [r3, #0]
- 80005c2: f023 03ff bic.w r3, r3, #255 @ 0xff
- 80005c6: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 80005ca: f043 0344 orr.w r3, r3, #68 @ 0x44
- 80005ce: 6013 str r3, [r2, #0]
-
- while(1)
- { /* light up the LEDs permanently */
- GPIOA->ODR &= ~(MASK_LED_BLUE | MASK_LED_YELLOW);
- 80005d0: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
- 80005d4: 695b ldr r3, [r3, #20]
- 80005d6: f04f 4290 mov.w r2, #1207959552 @ 0x48000000
- 80005da: f023 030a bic.w r3, r3, #10
- 80005de: 6153 str r3, [r2, #20]
- 80005e0: e7f6 b.n 80005d0
- 80005e2: bf00 nop
- 80005e4: 40021000 .word 0x40021000
-
-080005e8 :
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- 80005e8: 480c ldr r0, [pc, #48] @ (800061c )
- mov sp, r0 /* set stack pointer */
- 80005ea: 4685 mov sp, r0
-/* Call the clock system initialization function.*/
-// bl SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
- ldr r0, =_sdata
- 80005ec: 480c ldr r0, [pc, #48] @ (8000620 )
- ldr r1, =_edata
- 80005ee: 490d ldr r1, [pc, #52] @ (8000624 )
- ldr r2, =_sidata
- 80005f0: 4a0d ldr r2, [pc, #52] @ (8000628 )
- movs r3, #0
- 80005f2: 2300 movs r3, #0
- b LoopCopyDataInit
- 80005f4: e002 b.n 80005fc
-
-080005f6 :
-
-CopyDataInit:
- ldr r4, [r2, r3]
- 80005f6: 58d4 ldr r4, [r2, r3]
- str r4, [r0, r3]
- 80005f8: 50c4 str r4, [r0, r3]
- adds r3, r3, #4
- 80005fa: 3304 adds r3, #4
-
-080005fc :
-
-LoopCopyDataInit:
- adds r4, r0, r3
- 80005fc: 18c4 adds r4, r0, r3
- cmp r4, r1
- 80005fe: 428c cmp r4, r1
- bcc CopyDataInit
- 8000600: d3f9 bcc.n 80005f6
-
-/* Zero fill the bss segment. */
- ldr r2, =_sbss
- 8000602: 4a0a ldr r2, [pc, #40] @ (800062c )
- ldr r4, =_ebss
- 8000604: 4c0a ldr r4, [pc, #40] @ (8000630 )
- movs r3, #0
- 8000606: 2300 movs r3, #0
- b LoopFillZerobss
- 8000608: e001 b.n 800060e
-
-0800060a :
-
-FillZerobss:
- str r3, [r2]
- 800060a: 6013 str r3, [r2, #0]
- adds r2, r2, #4
- 800060c: 3204 adds r2, #4
-
-0800060e :
-
-LoopFillZerobss:
- cmp r2, r4
- 800060e: 42a2 cmp r2, r4
- bcc FillZerobss
- 8000610: d3fb bcc.n 800060a
-
-/* Call static constructors */
- bl __libc_init_array
- 8000612: f000 f80f bl 8000634 <__libc_init_array>
-/* Call the application's entry point.*/
- bl main
- 8000616: f7ff fdff bl 8000218
-
-0800061a :
-
-LoopForever:
- b LoopForever
- 800061a: e7fe b.n 800061a
- ldr r0, =_estack
- 800061c: 20008000 .word 0x20008000
- ldr r0, =_sdata
- 8000620: 20000000 .word 0x20000000
- ldr r1, =_edata
- 8000624: 20000000 .word 0x20000000
- ldr r2, =_sidata
- 8000628: 0800069c .word 0x0800069c
- ldr r2, =_sbss
- 800062c: 20000000 .word 0x20000000
- ldr r4, =_ebss
- 8000630: 20000020 .word 0x20000020
-
-08000634 <__libc_init_array>:
- 8000634: b570 push {r4, r5, r6, lr}
- 8000636: 4d0d ldr r5, [pc, #52] @ (800066c <__libc_init_array+0x38>)
- 8000638: 4c0d ldr r4, [pc, #52] @ (8000670 <__libc_init_array+0x3c>)
- 800063a: 1b64 subs r4, r4, r5
- 800063c: 10a4 asrs r4, r4, #2
- 800063e: 2600 movs r6, #0
- 8000640: 42a6 cmp r6, r4
- 8000642: d109 bne.n 8000658 <__libc_init_array+0x24>
- 8000644: 4d0b ldr r5, [pc, #44] @ (8000674 <__libc_init_array+0x40>)
- 8000646: 4c0c ldr r4, [pc, #48] @ (8000678 <__libc_init_array+0x44>)
- 8000648: f000 f818 bl 800067c <_init>
- 800064c: 1b64 subs r4, r4, r5
- 800064e: 10a4 asrs r4, r4, #2
- 8000650: 2600 movs r6, #0
- 8000652: 42a6 cmp r6, r4
- 8000654: d105 bne.n 8000662 <__libc_init_array+0x2e>
- 8000656: bd70 pop {r4, r5, r6, pc}
- 8000658: f855 3b04 ldr.w r3, [r5], #4
- 800065c: 4798 blx r3
- 800065e: 3601 adds r6, #1
- 8000660: e7ee b.n 8000640 <__libc_init_array+0xc>
- 8000662: f855 3b04 ldr.w r3, [r5], #4
- 8000666: 4798 blx r3
- 8000668: 3601 adds r6, #1
- 800066a: e7f2 b.n 8000652 <__libc_init_array+0x1e>
- 800066c: 08000694 .word 0x08000694
- 8000670: 08000694 .word 0x08000694
- 8000674: 08000694 .word 0x08000694
- 8000678: 08000698 .word 0x08000698
-
-0800067c <_init>:
- 800067c: b5f8 push {r3, r4, r5, r6, r7, lr}
- 800067e: bf00 nop
- 8000680: bcf8 pop {r3, r4, r5, r6, r7}
- 8000682: bc08 pop {r3}
- 8000684: 469e mov lr, r3
- 8000686: 4770 bx lr
-
-08000688 <_fini>:
- 8000688: b5f8 push {r3, r4, r5, r6, r7, lr}
- 800068a: bf00 nop
- 800068c: bcf8 pop {r3, r4, r5, r6, r7}
- 800068e: bc08 pop {r3}
- 8000690: 469e mov lr, r3
- 8000692: 4770 bx lr
diff --git a/task1/Debug/task1.map b/task1/Debug/task1.map
deleted file mode 100644
index 64ef3fe..0000000
--- a/task1/Debug/task1.map
+++ /dev/null
@@ -1,825 +0,0 @@
-Archive member included to satisfy reference by file (symbol)
-
-/opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-exit.o)
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-
-Memory Configuration
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-Name Origin Length Attributes
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-RAM 0x20000000 0x00008000 xrw
-FLASH 0x08000000 0x00020000 xr
-*default* 0x00000000 0xffffffff
-
-Linker script and memory map
-
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crti.o
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
-LOAD ./Src/task1.o
-LOAD ./Src/task1_it.o
-LOAD ./Startup/startup_stm32g431kbtx.o
-LOAD ./Startup/syscalls.o
-LOAD ./Startup/sysmem.o
-START GROUP
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a
-END GROUP
-START GROUP
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/libgcc.a
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a
-END GROUP
-START GROUP
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/libgcc.a
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a
-END GROUP
-START GROUP
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/libgcc.a
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a
-END GROUP
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtend.o
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtn.o
- 0x20008000 _estack = (ORIGIN (RAM) + LENGTH (RAM))
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-
-.isr_vector 0x08000000 0x1d8
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- *(.isr_vector)
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-.text 0x080001d8 0x4bc
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- *(.text*)
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- *(.init)
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- *(.fini)
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-
-.rodata 0x08000694 0x0
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- *(.rodata)
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-.ARM.extab 0x08000694 0x0
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-.ARM 0x08000694 0x0
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-.preinit_array 0x08000694 0x0
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-.init_array 0x08000694 0x4
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-.fini_array 0x08000698 0x4
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- [!provide] PROVIDE (__fini_array_start = .)
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- [!provide] PROVIDE (__fini_array_end = .)
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-
-.rel.dyn 0x0800069c 0x0
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-
-.data 0x20000000 0x0 load address 0x0800069c
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-.igot.plt 0x20000000 0x0 load address 0x0800069c
- .igot.plt 0x20000000 0x0 /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crtbegin.o
-
-.ccmsram 0x10000000 0x0 load address 0x0800069c
- 0x10000000 . = ALIGN (0x4)
- 0x10000000 _sccmsram = .
- *(.ccmsram)
- *(.ccmsram*)
- 0x10000000 . = ALIGN (0x4)
- 0x10000000 _eccmsram = .
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-.bss 0x20000000 0x20
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- *(.bss*)
- .bss.state 0x2000001c 0x4 ./Src/task1.o
- 0x2000001c state
- *(COMMON)
- 0x20000020 . = ALIGN (0x4)
- 0x20000020 _ebss = .
- 0x20000020 __bss_end__ = _ebss
-
-._user_heap_stack
- 0x20000020 0x600
- 0x20000020 . = ALIGN (0x8)
- [!provide] PROVIDE (end = .)
- 0x20000020 PROVIDE (_end = .)
- 0x20000220 . = (. + _Min_Heap_Size)
- *fill* 0x20000020 0x200
- 0x20000620 . = (. + _Min_Stack_Size)
- *fill* 0x20000220 0x400
- 0x20000620 . = ALIGN (0x8)
-
-/DISCARD/
- libc.a(*)
- libm.a(*)
- libgcc.a(*)
-
-.ARM.attributes
- 0x00000000 0x30
- *(.ARM.attributes)
- .ARM.attributes
- 0x00000000 0x22 /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/crti.o
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- .ARM.attributes
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- .ARM.attributes
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- .ARM.attributes
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- .ARM.attributes
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- .ARM.attributes
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-OUTPUT(task1.elf elf32-littlearm)
-LOAD linker stubs
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc.a
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a
-LOAD /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+fp/hard/libgcc.a
-
-.debug_info 0x00000000 0x7eb
- .debug_info 0x00000000 0x42f ./Src/task1.o
- .debug_info 0x0000042f 0x38b ./Src/task1_it.o
- .debug_info 0x000007ba 0x31 ./Startup/startup_stm32g431kbtx.o
-
-.debug_abbrev 0x00000000 0x296
- .debug_abbrev 0x00000000 0x173 ./Src/task1.o
- .debug_abbrev 0x00000173 0xfd ./Src/task1_it.o
- .debug_abbrev 0x00000270 0x26 ./Startup/startup_stm32g431kbtx.o
-
-.debug_aranges 0x00000000 0x78
- .debug_aranges
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- .debug_aranges
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- .debug_aranges
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-
-.debug_rnglists
- 0x00000000 0x3a
- .debug_rnglists
- 0x00000000 0x21 ./Src/task1.o
- .debug_rnglists
- 0x00000021 0x19 ./Src/task1_it.o
-
-.debug_macro 0x00000000 0x13740
- .debug_macro 0x00000000 0xd4 ./Src/task1.o
- .debug_macro 0x000000d4 0xac0 ./Src/task1.o
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- .debug_macro 0x00000bbc 0x22 ./Src/task1.o
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- .debug_macro 0x00000cbd 0x103 ./Src/task1.o
- .debug_macro 0x00000dc0 0x6a ./Src/task1.o
- .debug_macro 0x00000e2a 0x1df ./Src/task1.o
- .debug_macro 0x00001009 0x1c ./Src/task1.o
- .debug_macro 0x00001025 0x22 ./Src/task1.o
- .debug_macro 0x00001047 0xfb ./Src/task1.o
- .debug_macro 0x00001142 0x1011 ./Src/task1.o
- .debug_macro 0x00002153 0x11f ./Src/task1.o
- .debug_macro 0x00002272 0x11396 ./Src/task1.o
- .debug_macro 0x00013608 0x70 ./Src/task1.o
- .debug_macro 0x00013678 0xc8 ./Src/task1_it.o
-
-.debug_line 0x00000000 0xa3e
- .debug_line 0x00000000 0x58f ./Src/task1.o
- .debug_line 0x0000058f 0x445 ./Src/task1_it.o
- .debug_line 0x000009d4 0x6a ./Startup/startup_stm32g431kbtx.o
-
-.debug_str 0x00000000 0x6f831
- .debug_str 0x00000000 0x6f7b8 ./Src/task1.o
- 0x6f954 (size before relaxing)
- .debug_str 0x0006f7b8 0x48 ./Src/task1_it.o
- 0x6f900 (size before relaxing)
- .debug_str 0x0006f800 0x31 ./Startup/startup_stm32g431kbtx.o
- 0x96 (size before relaxing)
-
-.comment 0x00000000 0x43
- .comment 0x00000000 0x43 ./Src/task1.o
- 0x44 (size before relaxing)
- .comment 0x00000043 0x44 ./Src/task1_it.o
-
-.debug_frame 0x00000000 0xe4
- .debug_frame 0x00000000 0x78 ./Src/task1.o
- .debug_frame 0x00000078 0x40 ./Src/task1_it.o
- .debug_frame 0x000000b8 0x2c /opt/st/stm32cubeide_1.16.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.200.202406132123/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-init.o)
-
-.debug_line_str
- 0x00000000 0x7a
- .debug_line_str
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diff --git a/task2/task2.als b/task2/task2.als
new file mode 100644
index 0000000..8dd4b29
--- /dev/null
+++ b/task2/task2.als
@@ -0,0 +1,1620 @@
+ GNU assembler version 2.40.0 (arm-none-eabi)
+ using BFD version (GNU Tools for STM32 12.3.rel1.20240612-1315) 2.40.0.20230627.
+ options passed : -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn
+ input file : task2.s
+ output file : task2.o
+ target : arm-none-eabi
+ time stamp : 2026-03-24T14:14:11.000+0100
+
+ 1 #****************************************************************************************#
+ 2 # Project: task2 - ASM: Interrupts
+ 3 # File: task2.s
+ 4 #
+ 5 # Language: ASM
+ 6 #
+ 7 # Hardware: STefi Light v1.1
+ 8 # Processor: STM32G431KBT6U
+ 9 #
+ 10 # Author: Manuel Lederhofer
+ 11 # Datum: 31.10.2014
+ 12 #
+ 13 # Version: 6.0
+ 14 # History:
+ 15 # 31.10.2014 ML create file
+ 16 # 27.09.2018 ML edit comments, extend vector table
+ 17 # 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+ 18 # 27.02.2019 ML move section of exception handlers to bottom of file
+ 19 # 25.09.2019 ML minor changes for a better code and comment understanding
+ 20 # 04.09.2020 HL port from STM32L476RG to STM32F411xE
+ 21 # 21.09.2020 ML tidy up, comments and formatting
+ 22 # 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+ 23 # 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+ 24 # 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+ 25 # 24.06.2025 TK remove /* ... place your code here ... */
+ 26 #
+ 27 # Status: working
+ 28 #
+ 29 # Description:
+ 30 # See the description and requirements of the requested application
+ 31 # in the lab exercise guide.
+ 32 #
+ 33 # Notes:
+ 34 # - MCU speed at startup is 16 MHz
+ 35 #
+ 36 # ToDo:
+ 37 # - Change the example code to match the description and requirements
+ 38 # of the requested application in the lab exercise guide.
+ 39 #****************************************************************************************#
+ 40
+ 41 .include "G431_addr.s"
+ 1 #*****************************************************************************************
+ 2 # Project: task2 - switch triggered LEDs
+ 3 # File: G431_addr.s
+ 4 #
+ 5 # Language: ASM
+ 6 #
+ 7 # Hardware: STefi v1.1
+ 8 # Processor: STM32G431KBT6U
+ 9 #
+ 10 # Author: Manuel Lederhofer
+ 11 # Datum: 20.08.2015
+ 12 #
+ 13 # Version: 3.0
+ 14 # History:
+ 15 # 20.08.2015 ML create file
+ 16 # 07.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+ 17 # 27.02.2019 ML change from absolute addresses to BASE + OFFSET notation and
+ 18 # add more timer modules
+ 19 # 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+ 20 #
+ 21 # Status: working
+ 22 #
+ 23 # Description:
+ 24 # Connects assembly addresses for STM32G431 MCU to symbolic register names
+ 25 # used in the datasheets.
+ 26 #
+ 27 # Notes:
+ 28 # - default MCU speed at startup is 16 MHz.
+ 29 #
+ 30 # ToDo:
+ 31 # - none -
+ 32 #*****************************************************************************************
+ 33
+ 34
+ 35 #----------------------------------------------------------------------------------------#
+ 36 # MCU Bus Base Addresses
+ 37 #----------------------------------------------------------------------------------------#
+ 38
+ 39 .equ APB1_BASE, 0x40000000
+ 40 .equ APB2_BASE, 0x40010000
+ 41 .equ AHB1_BASE, 0x40020000
+ 42 .equ AHB2_BASE, 0x48000000
+ 43 .equ AHB3_BASE, 0xA0000000 //!!! FSMC + QSPI registers = AHB3 ?
+ 44 .equ PPB_BASE, 0xE0000000 /* Cortex M4 with FPU Internal Peripherals */
+ 45
+ 46 #----------------------------------------------------------------------------------------#
+ 47 # System Configuration Controller
+ 48 #
+ 49 # address space: 0x4001_0000 .. 0x4001_0029
+ 50 #----------------------------------------------------------------------------------------#
+ 51
+ 52 .equ SYSCFG_BASE, APB2_BASE
+ 53
+ 54 .equ SYSCFG_MEMRMP, SYSCFG_BASE + 0x00
+ 55 .equ SYSCFG_CFGR1, SYSCFG_BASE + 0x04
+ 56 .equ SYSCFG_EXTICR1, SYSCFG_BASE + 0x08
+ 57 .equ SYSCFG_EXTICR2, SYSCFG_BASE + 0x0C
+ 58 .equ SYSCFG_EXTICR3, SYSCFG_BASE + 0x10
+ 59 .equ SYSCFG_EXTICR4, SYSCFG_BASE + 0x14
+ 60 .equ SYSCFG_SCSR, SYSCFG_BASE + 0x18
+ 61 .equ SYSCFG_CFGR2, SYSCFG_BASE + 0x1C
+ 62 .equ SYSCFG_SWPR, SYSCFG_BASE + 0x20
+ 63 .equ SYSCFG_SKR, SYSCFG_BASE + 0x24
+ 64
+ 65 #----------------------------------------------------------------------------------------#
+ 66 # Extended Interrupts And Events Controller
+ 67 #
+ 68 # address space: 0x4001_0400 .. 0x4001_07FF
+ 69 #----------------------------------------------------------------------------------------#
+ 70
+ 71 .equ EXTI_BASE, APB2_BASE + 0x400
+ 72
+ 73 .equ EXTI_IMR1, EXTI_BASE + 0x00
+ 74 .equ EXTI_EMR1, EXTI_BASE + 0x04
+ 75 .equ EXTI_RTSR1, EXTI_BASE + 0x08
+ 76 .equ EXTI_FTSR1, EXTI_BASE + 0x0C
+ 77 .equ EXTI_SWIER1, EXTI_BASE + 0x10
+ 78 .equ EXTI_PR1, EXTI_BASE + 0x14
+ 79
+ 80 .equ EXTI_IMR2, EXTI_BASE + 0x20
+ 81 .equ EXTI_EMR2, EXTI_BASE + 0x24
+ 82 .equ EXTI_RTSR2, EXTI_BASE + 0x28
+ 83 .equ EXTI_FTSR2, EXTI_BASE + 0x2C
+ 84 .equ EXTI_SWIER2, EXTI_BASE + 0x30
+ 85 .equ EXTI_PR2, EXTI_BASE + 0x34
+ 86
+ 87 #----------------------------------------------------------------------------------------#
+ 88 # TIM module common configuration
+ 89 #
+ 90 # Every timer has 1 KB address space:
+ 91 #
+ 92 # TIM2 .. TIM7: 0x4000_0000 .. 0x4000_17FF (APB1)
+ 93 # TIM1: 0x4001_2C00 .. 0x4001_2FFF (APB2)
+ 94 # TIM8: 0x4001_3400 .. 0x4001_37FF (APB2)
+ 95 # TIM15 .. TIM17: 0x4001_4000 .. 0x4001_4BFF (APB2)
+ 96 # TIM20: 0x4001_5000 .. 0x4001_53FF (APB2)
+ 97 #
+ 98 # note:
+ 99 # TIM2 + TIM5 are 32 bit timers. All others have a width of 16 bit.
+ 100 # Below, the timers on one line share a common register set description.
+ 101 #
+ 102 # TIM 1, 8, 20 advances control timers
+ 103 # TIM 2, 3, 4, 5 general purpose timers (TIM2/5 = 32 bit)
+ 104 # TIM 15 general purpose timers
+ 105 # TIM 16, 17 general purpose timers
+ 106 # TIM 6, 7 basic timers
+ 107 #----------------------------------------------------------------------------------------#
+ 108
+ 109 .equ TIM_CR1_OFFSET, 0x00
+ 110 .equ TIM_CR2_OFFSET, 0x04
+ 111 .equ TIM_SMCR_OFFSET, 0x08
+ 112 .equ TIM_DIER_OFFSET, 0x0C
+ 113 .equ TIM_SR_OFFSET, 0x10
+ 114 .equ TIM_EGR_OFFSET, 0x14
+ 115 .equ TIM_CCMR1_OFFSET, 0x18
+ 116 .equ TIM_CCMR2_OFFSET, 0x1C
+ 117 .equ TIM_CCER_OFFSET, 0x20
+ 118 .equ TIM_CNT_OFFSET, 0x24
+ 119 .equ TIM_PSC_OFFSET, 0x28
+ 120 .equ TIM_ARR_OFFSET, 0x2C
+ 121 .equ TIM_RCR_OFFSET, 0x30
+ 122 .equ TIM_CCR1_OFFSET, 0x34
+ 123 .equ TIM_CCR2_OFFSET, 0x38
+ 124 .equ TIM_CCR3_OFFSET, 0x3C
+ 125 .equ TIM_CCR4_OFFSET, 0x40
+ 126 .equ TIM_BDTR_OFFSET, 0x44
+ 127 .equ TIM_CCR5_OFFSET, 0x48
+ 128 .equ TIM_CCR6_OFFSET, 0x4C
+ 129 .equ TIM_CCMR3_OFFSET, 0x50
+ 130 .equ TIM_DTR2_OFFSET, 0x54
+ 131 .equ TIM_ECR_OFFSET, 0x58
+ 132 .equ TIM_TISEL_OFFSET, 0x5C
+ 133 .equ TIM_AF1_OFFSET, 0x60
+ 134 .equ TIM_AF2_OFFSET, 0x64
+ 135 .equ TIM_OR1_OFFSET, 0x68
+ 136
+ 137 .equ TIM_DCR_OFFSET, 0x3DC
+ 138 .equ TIM_DMAR_OFFSET, 0x3E0
+ 139
+ 140 #- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
+ 141
+ 142 #--- Genral Purpose Timer - TIM2 / address space: 0x4000_0000 .. 0x4000_03FF
+ 143
+ 144 .equ TIM2_BASE, APB1_BASE
+ 145
+ 146 .equ TIM2_CR1, TIM2_BASE + TIM_CR1_OFFSET
+ 147 .equ TIM2_CR2, TIM2_BASE + TIM_CR2_OFFSET
+ 148 .equ TIM2_SMCR, TIM2_BASE + TIM_SMCR_OFFSET
+ 149 .equ TIM2_DIER, TIM2_BASE + TIM_DIER_OFFSET
+ 150 .equ TIM2_SR, TIM2_BASE + TIM_SR_OFFSET
+ 151 .equ TIM2_EGR, TIM2_BASE + TIM_EGR_OFFSET
+ 152 .equ TIM2_CCMR1, TIM2_BASE + TIM_CCMR1_OFFSET
+ 153 .equ TIM2_CCMR2, TIM2_BASE + TIM_CCMR2_OFFSET
+ 154 .equ TIM2_CCER, TIM2_BASE + TIM_CCER_OFFSET
+ 155 .equ TIM2_CNT, TIM2_BASE + TIM_CNT_OFFSET
+ 156 .equ TIM2_PSC, TIM2_BASE + TIM_PSC_OFFSET
+ 157 .equ TIM2_ARR, TIM2_BASE + TIM_ARR_OFFSET
+ 158
+ 159 .equ TIM2_CCR1, TIM2_BASE + TIM_CCR1_OFFSET
+ 160 .equ TIM2_CCR2, TIM2_BASE + TIM_CCR2_OFFSET
+ 161 .equ TIM2_CCR3, TIM2_BASE + TIM_CCR3_OFFSET
+ 162 .equ TIM2_CCR4, TIM2_BASE + TIM_CCR4_OFFSET
+ 163
+ 164 .equ TIM2_ECR, TIM2_BASE + TIM_ECR_OFFSET
+ 165 .equ TIM2_TISEL, TIM2_BASE + TIM_TISEL_OFFSET
+ 166 .equ TIM2_AF1, TIM2_BASE + TIM_ECR_OFFSET
+ 167 .equ TIM2_AF2, TIM2_BASE + TIM_ECR_OFFSET
+ 168
+ 169 .equ TIM2_DCR, TIM2_BASE + TIM_DCR_OFFSET
+ 170 .equ TIM2_DMAR, TIM2_BASE + TIM_DMAR_OFFSET
+ 171
+ 172 #--- Genral Purpose Timer - TIM3 / address space: 0x4000_0400 .. 0x4000_07FF
+ 173
+ 174 .equ TIM3_BASE, APB1_BASE + 0x400
+ 175
+ 176 .equ TIM3_CR1, TIM3_BASE + TIM_CR1_OFFSET
+ 177 .equ TIM3_CR2, TIM3_BASE + TIM_CR2_OFFSET
+ 178 .equ TIM3_SMCR, TIM3_BASE + TIM_SMCR_OFFSET
+ 179 .equ TIM3_DIER, TIM3_BASE + TIM_DIER_OFFSET
+ 180 .equ TIM3_SR, TIM3_BASE + TIM_SR_OFFSET
+ 181 .equ TIM3_EGR, TIM3_BASE + TIM_EGR_OFFSET
+ 182 .equ TIM3_CCMR1, TIM3_BASE + TIM_CCMR1_OFFSET
+ 183 .equ TIM3_CCMR2, TIM3_BASE + TIM_CCMR2_OFFSET
+ 184 .equ TIM3_CCER, TIM3_BASE + TIM_CCER_OFFSET
+ 185 .equ TIM3_CNT, TIM3_BASE + TIM_CNT_OFFSET
+ 186 .equ TIM3_PSC, TIM3_BASE + TIM_PSC_OFFSET
+ 187 .equ TIM3_ARR, TIM3_BASE + TIM_ARR_OFFSET
+ 188
+ 189 .equ TIM3_CCR1, TIM3_BASE + TIM_CCR1_OFFSET
+ 190 .equ TIM3_CCR2, TIM3_BASE + TIM_CCR2_OFFSET
+ 191 .equ TIM3_CCR3, TIM3_BASE + TIM_CCR3_OFFSET
+ 192 .equ TIM3_CCR4, TIM3_BASE + TIM_CCR4_OFFSET
+ 193
+ 194 .equ TIM3_ECR, TIM3_BASE + TIM_ECR_OFFSET
+ 195 .equ TIM3_TISEL, TIM3_BASE + TIM_TISEL_OFFSET
+ 196 .equ TIM3_AF1, TIM3_BASE + TIM_ECR_OFFSET
+ 197 .equ TIM3_AF2, TIM3_BASE + TIM_ECR_OFFSET
+ 198
+ 199 .equ TIM3_DCR, TIM3_BASE + TIM_DCR_OFFSET
+ 200 .equ TIM3_DMAR, TIM3_BASE + TIM_DMAR_OFFSET
+ 201
+ 202 #--- Genral Purpose Timer - TIM4 / address space: 0x4000_0800 .. 0x4000_0BFF
+ 203
+ 204 .equ TIM4_BASE, APB1_BASE + 0x800
+ 205
+ 206 .equ TIM4_CR1, TIM4_BASE + TIM_CR1_OFFSET
+ 207 .equ TIM4_CR2, TIM4_BASE + TIM_CR2_OFFSET
+ 208 .equ TIM4_SMCR, TIM4_BASE + TIM_SMCR_OFFSET
+ 209 .equ TIM4_DIER, TIM4_BASE + TIM_DIER_OFFSET
+ 210 .equ TIM4_SR, TIM4_BASE + TIM_SR_OFFSET
+ 211 .equ TIM4_EGR, TIM4_BASE + TIM_EGR_OFFSET
+ 212 .equ TIM4_CCMR1, TIM4_BASE + TIM_CCMR1_OFFSET
+ 213 .equ TIM4_CCMR2, TIM4_BASE + TIM_CCMR2_OFFSET
+ 214 .equ TIM4_CCER, TIM4_BASE + TIM_CCER_OFFSET
+ 215 .equ TIM4_CNT, TIM4_BASE + TIM_CNT_OFFSET
+ 216 .equ TIM4_PSC, TIM4_BASE + TIM_PSC_OFFSET
+ 217 .equ TIM4_ARR, TIM4_BASE + TIM_ARR_OFFSET
+ 218
+ 219 .equ TIM4_CCR1, TIM4_BASE + TIM_CCR1_OFFSET
+ 220 .equ TIM4_CCR2, TIM4_BASE + TIM_CCR2_OFFSET
+ 221 .equ TIM4_CCR3, TIM4_BASE + TIM_CCR3_OFFSET
+ 222 .equ TIM4_CCR4, TIM4_BASE + TIM_CCR4_OFFSET
+ 223
+ 224 .equ TIM4_ECR, TIM4_BASE + TIM_ECR_OFFSET
+ 225 .equ TIM4_TISEL, TIM4_BASE + TIM_TISEL_OFFSET
+ 226 .equ TIM4_AF1, TIM4_BASE + TIM_ECR_OFFSET
+ 227 .equ TIM4_AF2, TIM4_BASE + TIM_ECR_OFFSET
+ 228
+ 229 .equ TIM4_DCR, TIM4_BASE + TIM_DCR_OFFSET
+ 230 .equ TIM4_DMAR, TIM4_BASE + TIM_DMAR_OFFSET
+ 231
+ 232 #--- Genral Purpose Timer - TIM5 / address space: 0x4000_0C00 .. 0x4000_0FFF
+ 233
+ 234 .equ TIM5_BASE, APB1_BASE + 0xC00
+ 235
+ 236 .equ TIM5_CR1, TIM5_BASE + TIM_CR1_OFFSET
+ 237 .equ TIM5_CR2, TIM5_BASE + TIM_CR2_OFFSET
+ 238 .equ TIM5_SMCR, TIM5_BASE + TIM_SMCR_OFFSET
+ 239 .equ TIM5_DIER, TIM5_BASE + TIM_DIER_OFFSET
+ 240 .equ TIM5_SR, TIM5_BASE + TIM_SR_OFFSET
+ 241 .equ TIM5_EGR, TIM5_BASE + TIM_EGR_OFFSET
+ 242 .equ TIM5_CCMR1, TIM5_BASE + TIM_CCMR1_OFFSET
+ 243 .equ TIM5_CCMR2, TIM5_BASE + TIM_CCMR2_OFFSET
+ 244 .equ TIM5_CCER, TIM5_BASE + TIM_CCER_OFFSET
+ 245 .equ TIM5_CNT, TIM5_BASE + TIM_CNT_OFFSET
+ 246 .equ TIM5_PSC, TIM5_BASE + TIM_PSC_OFFSET
+ 247 .equ TIM5_ARR, TIM5_BASE + TIM_ARR_OFFSET
+ 248
+ 249 .equ TIM5_CCR1, TIM5_BASE + TIM_CCR1_OFFSET
+ 250 .equ TIM5_CCR2, TIM5_BASE + TIM_CCR2_OFFSET
+ 251 .equ TIM5_CCR3, TIM5_BASE + TIM_CCR3_OFFSET
+ 252 .equ TIM5_CCR4, TIM5_BASE + TIM_CCR4_OFFSET
+ 253
+ 254 .equ TIM5_ECR, TIM5_BASE + TIM_ECR_OFFSET
+ 255 .equ TIM5_TISEL, TIM5_BASE + TIM_TISEL_OFFSET
+ 256 .equ TIM5_AF1, TIM5_BASE + TIM_ECR_OFFSET
+ 257 .equ TIM5_AF2, TIM5_BASE + TIM_ECR_OFFSET
+ 258
+ 259 .equ TIM5_DCR, TIM5_BASE + TIM_DCR_OFFSET
+ 260 .equ TIM5_DMAR, TIM5_BASE + TIM_DMAR_OFFSET
+ 261
+ 262 #--- Basic Timer - TIM6 / address space: 0x4000_1000 .. 0x4000_13FF
+ 263
+ 264 .equ TIM6_BASE, APB1_BASE + 0x1000
+ 265
+ 266 .equ TIM6_CR1, TIM6_BASE + TIM_CR1_OFFSET
+ 267 .equ TIM6_CR2, TIM6_BASE + TIM_CR2_OFFSET
+ 268
+ 269 .equ TIM6_DIER, TIM6_BASE + TIM_DIER_OFFSET
+ 270 .equ TIM6_SR, TIM6_BASE + TIM_SR_OFFSET
+ 271 .equ TIM6_EGR, TIM6_BASE + TIM_EGR_OFFSET
+ 272
+ 273 .equ TIM6_CNT, TIM6_BASE + TIM_CNT_OFFSET
+ 274 .equ TIM6_PSC, TIM6_BASE + TIM_PSC_OFFSET
+ 275 .equ TIM6_ARR, TIM6_BASE + TIM_ARR_OFFSET
+ 276
+ 277 #--- Basic Timer - TIM7 / address space: 0x4000_1400 .. 0x4000_17FF
+ 278
+ 279 .equ TIM7_BASE, APB1_BASE + 0x1400
+ 280
+ 281 .equ TIM7_CR1, TIM7_BASE + TIM_CR1_OFFSET
+ 282 .equ TIM7_CR2, TIM7_BASE + TIM_CR2_OFFSET
+ 283
+ 284 .equ TIM7_DIER, TIM7_BASE + TIM_DIER_OFFSET
+ 285 .equ TIM7_SR, TIM7_BASE + TIM_SR_OFFSET
+ 286 .equ TIM7_EGR, TIM7_BASE + TIM_EGR_OFFSET
+ 287
+ 288 .equ TIM7_CNT, TIM7_BASE + TIM_CNT_OFFSET
+ 289 .equ TIM7_PSC, TIM7_BASE + TIM_PSC_OFFSET
+ 290 .equ TIM7_ARR, TIM7_BASE + TIM_ARR_OFFSET
+ 291
+ 292 #--- Advanced Control Timer - TIM1 / address space: 0x4001_2C00 .. 0x4001_2FFF
+ 293
+ 294 .equ TIM1_BASE, APB2_BASE + 0x2C00
+ 295
+ 296 .equ TIM1_CR1, TIM1_BASE + TIM_CR1_OFFSET
+ 297 .equ TIM1_CR2, TIM1_BASE + TIM_CR2_OFFSET
+ 298 .equ TIM1_SMCR, TIM1_BASE + TIM_SMCR_OFFSET
+ 299 .equ TIM1_DIER, TIM1_BASE + TIM_DIER_OFFSET
+ 300 .equ TIM1_SR, TIM1_BASE + TIM_SR_OFFSET
+ 301 .equ TIM1_EGR, TIM1_BASE + TIM_EGR_OFFSET
+ 302 .equ TIM1_CCMR1, TIM1_BASE + TIM_CCMR1_OFFSET
+ 303 .equ TIM1_CCMR2, TIM1_BASE + TIM_CCMR2_OFFSET
+ 304 .equ TIM1_CCER, TIM1_BASE + TIM_CCER_OFFSET
+ 305 .equ TIM1_CNT, TIM1_BASE + TIM_CNT_OFFSET
+ 306 .equ TIM1_PSC, TIM1_BASE + TIM_PSC_OFFSET
+ 307 .equ TIM1_ARR, TIM1_BASE + TIM_ARR_OFFSET
+ 308 .equ TIM1_RCR, TIM1_BASE + TIM_RCR_OFFSET
+ 309 .equ TIM1_CCR1, TIM1_BASE + TIM_CCR1_OFFSET
+ 310 .equ TIM1_CCR2, TIM1_BASE + TIM_CCR2_OFFSET
+ 311 .equ TIM1_CCR3, TIM1_BASE + TIM_CCR3_OFFSET
+ 312 .equ TIM1_CCR4, TIM1_BASE + TIM_CCR4_OFFSET
+ 313 .equ TIM1_BDTR, TIM1_BASE + TIM_BDTR_OFFSET
+ 314 .equ TIM1_CCR5, TIM1_BASE + TIM_CCR5_OFFSET
+ 315 .equ TIM1_CCR6, TIM1_BASE + TIM_CCR6_OFFSET
+ 316 .equ TIM1_CCMR3, TIM1_BASE + TIM_CCMR3_OFFSET
+ 317 .equ TIM1_DTR2, TIM1_BASE + TIM_DTR2_OFFSET
+ 318 .equ TIM1_ECR, TIM1_BASE + TIM_ECR_OFFSET
+ 319 .equ TIM1_TISEL, TIM1_BASE + TIM_TISEL_OFFSET
+ 320 .equ TIM1_AF1, TIM1_BASE + TIM_AF1_OFFSET
+ 321 .equ TIM1_AF2, TIM1_BASE + TIM_AF2_OFFSET
+ 322
+ 323 .equ TIM1_DCR, TIM1_BASE + TIM_DCR_OFFSET
+ 324 .equ TIM1_DMAR, TIM1_BASE + TIM_DMAR_OFFSET
+ 325
+ 326 #--- Advanced Control Timer - TIM8 / address space: 0x4001_3400 .. 0x4001_37FF
+ 327
+ 328 .equ TIM8_BASE, APB2_BASE + 0x3400
+ 329
+ 330 .equ TIM8_CR1, TIM8_BASE + TIM_CR1_OFFSET
+ 331 .equ TIM8_CR2, TIM8_BASE + TIM_CR2_OFFSET
+ 332 .equ TIM8_SMCR, TIM8_BASE + TIM_SMCR_OFFSET
+ 333 .equ TIM8_DIER, TIM8_BASE + TIM_DIER_OFFSET
+ 334 .equ TIM8_SR, TIM8_BASE + TIM_SR_OFFSET
+ 335 .equ TIM8_EGR, TIM8_BASE + TIM_EGR_OFFSET
+ 336 .equ TIM8_CCMR1, TIM8_BASE + TIM_CCMR1_OFFSET
+ 337 .equ TIM8_CCMR2, TIM8_BASE + TIM_CCMR2_OFFSET
+ 338 .equ TIM8_CCER, TIM8_BASE + TIM_CCER_OFFSET
+ 339 .equ TIM8_CNT, TIM8_BASE + TIM_CNT_OFFSET
+ 340 .equ TIM8_PSC, TIM8_BASE + TIM_PSC_OFFSET
+ 341 .equ TIM8_ARR, TIM8_BASE + TIM_ARR_OFFSET
+ 342 .equ TIM8_RCR, TIM8_BASE + TIM_RCR_OFFSET
+ 343 .equ TIM8_CCR1, TIM8_BASE + TIM_CCR1_OFFSET
+ 344 .equ TIM8_CCR2, TIM8_BASE + TIM_CCR2_OFFSET
+ 345 .equ TIM8_CCR3, TIM8_BASE + TIM_CCR3_OFFSET
+ 346 .equ TIM8_CCR4, TIM8_BASE + TIM_CCR4_OFFSET
+ 347 .equ TIM8_BDTR, TIM8_BASE + TIM_BDTR_OFFSET
+ 348 .equ TIM8_CCR5, TIM8_BASE + TIM_CCR5_OFFSET
+ 349 .equ TIM8_CCR6, TIM8_BASE + TIM_CCR6_OFFSET
+ 350 .equ TIM8_CCMR3, TIM8_BASE + TIM_CCMR3_OFFSET
+ 351 .equ TIM8_DTR2, TIM8_BASE + TIM_DTR2_OFFSET
+ 352 .equ TIM8_ECR, TIM8_BASE + TIM_ECR_OFFSET
+ 353 .equ TIM8_TISEL, TIM8_BASE + TIM_TISEL_OFFSET
+ 354 .equ TIM8_AF1, TIM8_BASE + TIM_AF1_OFFSET
+ 355 .equ TIM8_AF2, TIM8_BASE + TIM_AF2_OFFSET
+ 356
+ 357 .equ TIM8_DCR, TIM8_BASE + TIM_DCR_OFFSET
+ 358 .equ TIM8_DMAR, TIM8_BASE + TIM_DMAR_OFFSET
+ 359
+ 360 #--- Advanced Control Timer - TIM20 / address space: 0x4001_5000 .. 0x4001_53FF
+ 361
+ 362 .equ TIM20_BASE, APB2_BASE + 0x5000
+ 363
+ 364 .equ TIM20_CR1, TIM20_BASE + TIM_CR1_OFFSET
+ 365 .equ TIM20_CR2, TIM20_BASE + TIM_CR2_OFFSET
+ 366 .equ TIM20_SMCR, TIM20_BASE + TIM_SMCR_OFFSET
+ 367 .equ TIM20_DIER, TIM20_BASE + TIM_DIER_OFFSET
+ 368 .equ TIM20_SR, TIM20_BASE + TIM_SR_OFFSET
+ 369 .equ TIM20_EGR, TIM20_BASE + TIM_EGR_OFFSET
+ 370 .equ TIM20_CCMR1, TIM20_BASE + TIM_CCMR1_OFFSET
+ 371 .equ TIM20_CCMR2, TIM20_BASE + TIM_CCMR2_OFFSET
+ 372 .equ TIM20_CCER, TIM20_BASE + TIM_CCER_OFFSET
+ 373 .equ TIM20_CNT, TIM20_BASE + TIM_CNT_OFFSET
+ 374 .equ TIM20_PSC, TIM20_BASE + TIM_PSC_OFFSET
+ 375 .equ TIM20_ARR, TIM20_BASE + TIM_ARR_OFFSET
+ 376 .equ TIM20_RCR, TIM20_BASE + TIM_RCR_OFFSET
+ 377 .equ TIM20_CCR1, TIM20_BASE + TIM_CCR1_OFFSET
+ 378 .equ TIM20_CCR2, TIM20_BASE + TIM_CCR2_OFFSET
+ 379 .equ TIM20_CCR3, TIM20_BASE + TIM_CCR3_OFFSET
+ 380 .equ TIM20_CCR4, TIM20_BASE + TIM_CCR4_OFFSET
+ 381 .equ TIM20_BDTR, TIM20_BASE + TIM_BDTR_OFFSET
+ 382 .equ TIM20_CCR5, TIM20_BASE + TIM_CCR5_OFFSET
+ 383 .equ TIM20_CCR6, TIM20_BASE + TIM_CCR6_OFFSET
+ 384 .equ TIM20_CCMR3, TIM20_BASE + TIM_CCMR3_OFFSET
+ 385 .equ TIM20_DTR2, TIM20_BASE + TIM_DTR2_OFFSET
+ 386 .equ TIM20_ECR, TIM20_BASE + TIM_ECR_OFFSET
+ 387 .equ TIM20_TISEL, TIM20_BASE + TIM_TISEL_OFFSET
+ 388 .equ TIM20_AF1, TIM20_BASE + TIM_AF1_OFFSET
+ 389 .equ TIM20_AF2, TIM20_BASE + TIM_AF2_OFFSET
+ 390
+ 391 .equ TIM20_DCR, TIM20_BASE + TIM_DCR_OFFSET
+ 392 .equ TIM20_DMAR, TIM20_BASE + TIM_DMAR_OFFSET
+ 393
+ 394 #--- Genral Purpose Timer - TIM15 / address space: 0x4001_4000 .. 0x4001_43FF
+ 395
+ 396 .equ TIM15_BASE, APB2_BASE + 0x4000
+ 397
+ 398 .equ TIM15_CR1, TIM15_BASE + TIM_CR1_OFFSET
+ 399 .equ TIM15_CR2, TIM15_BASE + TIM_CR2_OFFSET
+ 400 .equ TIM15_SMCR, TIM15_BASE + TIM_SMCR_OFFSET
+ 401 .equ TIM15_DIER, TIM15_BASE + TIM_DIER_OFFSET
+ 402 .equ TIM15_SR, TIM15_BASE + TIM_SR_OFFSET
+ 403 .equ TIM15_EGR, TIM15_BASE + TIM_EGR_OFFSET
+ 404 .equ TIM15_CCMR1, TIM15_BASE + TIM_CCMR1_OFFSET
+ 405
+ 406 .equ TIM15_CCER, TIM15_BASE + TIM_CCER_OFFSET
+ 407 .equ TIM15_CNT, TIM15_BASE + TIM_CNT_OFFSET
+ 408 .equ TIM15_PSC, TIM15_BASE + TIM_PSC_OFFSET
+ 409 .equ TIM15_ARR, TIM15_BASE + TIM_ARR_OFFSET
+ 410 .equ TIM15_RCR, TIM15_BASE + TIM_RCR_OFFSET
+ 411 .equ TIM15_CCR1, TIM15_BASE + TIM_CCR1_OFFSET
+ 412 .equ TIM15_CCR2, TIM15_BASE + TIM_CCR2_OFFSET
+ 413
+ 414 .equ TIM15_BDTR, TIM15_BASE + TIM_BDTR_OFFSET
+ 415
+ 416 .equ TIM15_DTR2, TIM15_BASE + TIM_DTR2_OFFSET
+ 417
+ 418 .equ TIM15_TISEL, TIM15_BASE + TIM_TISEL_OFFSET
+ 419 .equ TIM15_AF1, TIM15_BASE + TIM_AF1_OFFSET
+ 420 .equ TIM15_AF2, TIM15_BASE + TIM_AF2_OFFSET
+ 421
+ 422 .equ TIM15_DCR, TIM15_BASE + TIM_DCR_OFFSET
+ 423 .equ TIM15_DMAR, TIM15_BASE + TIM_DMAR_OFFSET
+ 424
+ 425 #--- Genral Purpose Timer - TIM16 / address space: 0x4001_4400 .. 0x4001_47FF
+ 426
+ 427 .equ TIM16_BASE, APB2_BASE + 0x4400
+ 428
+ 429 .equ TIM16_CR1, TIM16_BASE + TIM_CR1_OFFSET
+ 430 .equ TIM16_CR2, TIM16_BASE + TIM_CR2_OFFSET
+ 431
+ 432 .equ TIM16_DIER, TIM16_BASE + TIM_DIER_OFFSET
+ 433 .equ TIM16_SR, TIM16_BASE + TIM_SR_OFFSET
+ 434 .equ TIM16_EGR, TIM16_BASE + TIM_EGR_OFFSET
+ 435 .equ TIM16_CCMR1, TIM16_BASE + TIM_CCMR1_OFFSET
+ 436
+ 437 .equ TIM16_CCER, TIM16_BASE + TIM_CCER_OFFSET
+ 438 .equ TIM16_CNT, TIM16_BASE + TIM_CNT_OFFSET
+ 439 .equ TIM16_PSC, TIM16_BASE + TIM_PSC_OFFSET
+ 440 .equ TIM16_ARR, TIM16_BASE + TIM_ARR_OFFSET
+ 441 .equ TIM16_RCR, TIM16_BASE + TIM_RCR_OFFSET
+ 442 .equ TIM16_CCR1, TIM16_BASE + TIM_CCR1_OFFSET
+ 443
+ 444 .equ TIM16_BDTR, TIM16_BASE + TIM_BDTR_OFFSET
+ 445
+ 446 .equ TIM16_DTR2, TIM16_BASE + TIM_DTR2_OFFSET
+ 447
+ 448 .equ TIM16_TISEL, TIM16_BASE + TIM_TISEL_OFFSET
+ 449 .equ TIM16_AF1, TIM16_BASE + TIM_AF1_OFFSET
+ 450 .equ TIM16_AF2, TIM16_BASE + TIM_AF2_OFFSET
+ 451 .equ TIM16_OR1, TIM16_BASE + TIM_OR1_OFFSET
+ 452
+ 453 .equ TIM16_DCR, TIM16_BASE + TIM_DCR_OFFSET
+ 454 .equ TIM16_DMAR, TIM16_BASE + TIM_DMAR_OFFSET
+ 455
+ 456 #--- Genral Purpose Timer - TIM17 / address space: 0x4001_4800 .. 0x4001_4BFF
+ 457
+ 458 .equ TIM17_BASE, APB2_BASE + 0x4800
+ 459
+ 460 .equ TIM17_CR1, TIM17_BASE + TIM_CR1_OFFSET
+ 461 .equ TIM17_CR2, TIM17_BASE + TIM_CR2_OFFSET
+ 462
+ 463 .equ TIM17_DIER, TIM17_BASE + TIM_DIER_OFFSET
+ 464 .equ TIM17_SR, TIM17_BASE + TIM_SR_OFFSET
+ 465 .equ TIM17_EGR, TIM17_BASE + TIM_EGR_OFFSET
+ 466 .equ TIM17_CCMR1, TIM17_BASE + TIM_CCMR1_OFFSET
+ 467
+ 468 .equ TIM17_CCER, TIM17_BASE + TIM_CCER_OFFSET
+ 469 .equ TIM17_CNT, TIM17_BASE + TIM_CNT_OFFSET
+ 470 .equ TIM17_PSC, TIM17_BASE + TIM_PSC_OFFSET
+ 471 .equ TIM17_ARR, TIM17_BASE + TIM_ARR_OFFSET
+ 472 .equ TIM17_RCR, TIM17_BASE + TIM_RCR_OFFSET
+ 473 .equ TIM17_CCR1, TIM17_BASE + TIM_CCR1_OFFSET
+ 474
+ 475 .equ TIM17_BDTR, TIM17_BASE + TIM_BDTR_OFFSET
+ 476
+ 477 .equ TIM17_DTR2, TIM17_BASE + TIM_DTR2_OFFSET
+ 478
+ 479 .equ TIM17_TISEL, TIM17_BASE + TIM_TISEL_OFFSET
+ 480 .equ TIM17_AF1, TIM17_BASE + TIM_AF1_OFFSET
+ 481 .equ TIM17_AF2, TIM17_BASE + TIM_AF2_OFFSET
+ 482 .equ TIM17_OR1, TIM17_BASE + TIM_OR1_OFFSET
+ 483
+ 484 .equ TIM17_DCR, TIM17_BASE + TIM_DCR_OFFSET
+ 485 .equ TIM17_DMAR, TIM17_BASE + TIM_DMAR_OFFSET
+ 486
+ 487 #----------------------------------------------------------------------------------------#
+ 488 # Reset and Clock Control
+ 489 #
+ 490 # address space: 0x4002_1000 .. 0x4002_13FF
+ 491 #----------------------------------------------------------------------------------------#
+ 492
+ 493 .equ RCC_BASE, AHB1_BASE + 0x1000
+ 494
+ 495 .equ RCC_CR, RCC_BASE + 0x00
+ 496 .equ RCC_ICSCR, RCC_BASE + 0x04
+ 497 .equ RCC_CFGR, RCC_BASE + 0x08
+ 498 .equ RCC_PLLCFGR, RCC_BASE + 0x0C
+ 499
+ 500 .equ RCC_CIER, RCC_BASE + 0x18
+ 501 .equ RCC_CIFR, RCC_BASE + 0x1C
+ 502 .equ RCC_CICR, RCC_BASE + 0x20
+ 503
+ 504 .equ RCC_AHB1RSTR, RCC_BASE + 0x28
+ 505 .equ RCC_AHB2RSTR, RCC_BASE + 0x2C
+ 506 .equ RCC_AHB3RSTR, RCC_BASE + 0x30
+ 507
+ 508 .equ RCC_APB1RSTR1, RCC_BASE + 0x38
+ 509 .equ RCC_APB1RSTR2, RCC_BASE + 0x3C
+ 510 .equ RCC_APB2RSTR, RCC_BASE + 0x40
+ 511
+ 512 .equ RCC_AHB1ENR, RCC_BASE + 0x48
+ 513 .equ RCC_AHB2ENR, RCC_BASE + 0x4C
+ 514 .equ RCC_AHB3ENR, RCC_BASE + 0x50
+ 515
+ 516 .equ RCC_APB1ENR1, RCC_BASE + 0x58
+ 517 .equ RCC_APB1ENR2, RCC_BASE + 0x5C
+ 518 .equ RCC_APB2ENR, RCC_BASE + 0x60
+ 519
+ 520 .equ RCC_AHB1SMENR, RCC_BASE + 0x68
+ 521 .equ RCC_AHB2SMENR, RCC_BASE + 0x6C
+ 522 .equ RCC_AHB3SMENR, RCC_BASE + 0x70
+ 523
+ 524 .equ RCC_APB1SMENR1, RCC_BASE + 0x78
+ 525 .equ RCC_APB1SMENR2, RCC_BASE + 0x7C
+ 526 .equ RCC_APB2SMENR, RCC_BASE + 0x80
+ 527
+ 528 .equ RCC_CCIPR, RCC_BASE + 0x88
+ 529
+ 530 .equ RCC_BDCR, RCC_BASE + 0x90
+ 531 .equ RCC_CSR, RCC_BASE + 0x94
+ 532 .equ RCC_CRRCR, RCC_BASE + 0x98
+ 533 .equ RCC_CCIPR2, RCC_BASE + 0x9C
+ 534
+ 535 #----------------------------------------------------------------------------------------#
+ 536 # GPIO module common configuration
+ 537 #
+ 538 # address space: 0x4800_0000 .. 0x4800_1FFF
+ 539 #----------------------------------------------------------------------------------------#
+ 540
+ 541 .equ GPIO_BASE, AHB2_BASE
+ 542
+ 543 .equ GPIO_MODER_OFFSET, 0x00
+ 544 .equ GPIO_OTYPER_OFFSET, 0x04
+ 545 .equ GPIO_OSPEEDR_OFFSET, 0x08
+ 546 .equ GPIO_PUPDR_OFFSET, 0x0C
+ 547 .equ GPIO_IDR_OFFSET, 0x10
+ 548 .equ GPIO_ODR_OFFSET, 0x14
+ 549 .equ GPIO_BSRR_OFFSET, 0x18
+ 550 .equ GPIO_LCKR_OFFSET, 0x1C
+ 551 .equ GPIO_AFRL_OFFSET, 0x20
+ 552 .equ GPIO_AFRH_OFFSET, 0x24
+ 553 .equ GPIO_BRR_OFFSET, 0x28
+ 554
+ 555 #- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
+ 556
+ 557 #--- Port A GPIO configuration / address space: 0x4800_0000 .. 0x4800_03FF
+ 558
+ 559 .equ GPIOA_BASE, GPIO_BASE
+ 560
+ 561 .equ GPIOA_MODER, GPIOA_BASE + GPIO_MODER_OFFSET
+ 562 .equ GPIOA_OTYPER, GPIOA_BASE + GPIO_OTYPER_OFFSET
+ 563 .equ GPIOA_OSPEEDR, GPIOA_BASE + GPIO_OSPEEDR_OFFSET
+ 564 .equ GPIOA_PUPDR, GPIOA_BASE + GPIO_PUPDR_OFFSET
+ 565 .equ GPIOA_IDR, GPIOA_BASE + GPIO_IDR_OFFSET
+ 566 .equ GPIOA_ODR, GPIOA_BASE + GPIO_ODR_OFFSET
+ 567 .equ GPIOA_BSRR, GPIOA_BASE + GPIO_BSRR_OFFSET
+ 568 .equ GPIOA_LCKR, GPIOA_BASE + GPIO_LCKR_OFFSET
+ 569 .equ GPIOA_AFRL, GPIOA_BASE + GPIO_AFRL_OFFSET
+ 570 .equ GPIOA_AFRH, GPIOA_BASE + GPIO_AFRH_OFFSET
+ 571 .equ GPIOA_BRR, GPIOA_BASE + GPIO_BRR_OFFSET
+ 572
+ 573 #--- Port B GPIO configuration / address space: 0x4800_0400 .. 0x4800_07FF
+ 574
+ 575 .equ GPIOB_BASE, GPIO_BASE + 0x400
+ 576
+ 577 .equ GPIOB_MODER, GPIOB_BASE + GPIO_MODER_OFFSET
+ 578 .equ GPIOB_OTYPER, GPIOB_BASE + GPIO_OTYPER_OFFSET
+ 579 .equ GPIOB_OSPEEDR, GPIOB_BASE + GPIO_OSPEEDR_OFFSET
+ 580 .equ GPIOB_PUPDR, GPIOB_BASE + GPIO_PUPDR_OFFSET
+ 581 .equ GPIOB_IDR, GPIOB_BASE + GPIO_IDR_OFFSET
+ 582 .equ GPIOB_ODR, GPIOB_BASE + GPIO_ODR_OFFSET
+ 583 .equ GPIOB_BSRR, GPIOB_BASE + GPIO_BSRR_OFFSET
+ 584 .equ GPIOB_LCKR, GPIOB_BASE + GPIO_LCKR_OFFSET
+ 585 .equ GPIOB_AFRL, GPIOB_BASE + GPIO_AFRL_OFFSET
+ 586 .equ GPIOB_AFRH, GPIOB_BASE + GPIO_AFRH_OFFSET
+ 587 .equ GPIOB_BRR, GPIOB_BASE + GPIO_BRR_OFFSET
+ 588
+ 589 #--- Port C GPIO configuration / address space: 0x4800_0800 .. 0x4800_0BFF
+ 590
+ 591 .equ GPIOC_BASE, GPIO_BASE + 0x800
+ 592
+ 593 .equ GPIOC_MODER, GPIOC_BASE + GPIO_MODER_OFFSET
+ 594 .equ GPIOC_OTYPER, GPIOC_BASE + GPIO_OTYPER_OFFSET
+ 595 .equ GPIOC_OSPEEDR, GPIOC_BASE + GPIO_OSPEEDR_OFFSET
+ 596 .equ GPIOC_PUPDR, GPIOC_BASE + GPIO_PUPDR_OFFSET
+ 597 .equ GPIOC_IDR, GPIOC_BASE + GPIO_IDR_OFFSET
+ 598 .equ GPIOC_ODR, GPIOC_BASE + GPIO_ODR_OFFSET
+ 599 .equ GPIOC_BSRR, GPIOC_BASE + GPIO_BSRR_OFFSET
+ 600 .equ GPIOC_LCKR, GPIOC_BASE + GPIO_LCKR_OFFSET
+ 601 .equ GPIOC_AFRL, GPIOC_BASE + GPIO_AFRL_OFFSET
+ 602 .equ GPIOC_AFRH, GPIOC_BASE + GPIO_AFRH_OFFSET
+ 603 .equ GPIOC_BRR, GPIOC_BASE + GPIO_BRR_OFFSET
+ 604
+ 605 #--- Port D GPIO configuration / address space: 0x4800_0C00 .. 0x4800_0FFF
+ 606
+ 607 .equ GPIOD_BASE, GPIO_BASE + 0xC00
+ 608
+ 609 .equ GPIOD_MODER, GPIOD_BASE + GPIO_MODER_OFFSET
+ 610 .equ GPIOD_OTYPER, GPIOD_BASE + GPIO_OTYPER_OFFSET
+ 611 .equ GPIOD_OSPEEDR, GPIOD_BASE + GPIO_OSPEEDR_OFFSET
+ 612 .equ GPIOD_PUPDR, GPIOD_BASE + GPIO_PUPDR_OFFSET
+ 613 .equ GPIOD_IDR, GPIOD_BASE + GPIO_IDR_OFFSET
+ 614 .equ GPIOD_ODR, GPIOD_BASE + GPIO_ODR_OFFSET
+ 615 .equ GPIOD_BSRR, GPIOD_BASE + GPIO_BSRR_OFFSET
+ 616 .equ GPIOD_LCKR, GPIOD_BASE + GPIO_LCKR_OFFSET
+ 617 .equ GPIOD_AFRL, GPIOD_BASE + GPIO_AFRL_OFFSET
+ 618 .equ GPIOD_AFRH, GPIOD_BASE + GPIO_AFRH_OFFSET
+ 619 .equ GPIOD_BRR, GPIOD_BASE + GPIO_BRR_OFFSET
+ 620
+ 621 #--- Port E GPIO configuration / address space: 0x4800_1000 .. 0x4800_13FF
+ 622
+ 623 .equ GPIOE_BASE, GPIO_BASE + 0x1000
+ 624
+ 625 .equ GPIOE_MODER, GPIOE_BASE + GPIO_MODER_OFFSET
+ 626 .equ GPIOE_OTYPER, GPIOE_BASE + GPIO_OTYPER_OFFSET
+ 627 .equ GPIOE_OSPEEDR, GPIOE_BASE + GPIO_OSPEEDR_OFFSET
+ 628 .equ GPIOE_PUPDR, GPIOE_BASE + GPIO_PUPDR_OFFSET
+ 629 .equ GPIOE_IDR, GPIOE_BASE + GPIO_IDR_OFFSET
+ 630 .equ GPIOE_ODR, GPIOE_BASE + GPIO_ODR_OFFSET
+ 631 .equ GPIOE_BSRR, GPIOE_BASE + GPIO_BSRR_OFFSET
+ 632 .equ GPIOE_LCKR, GPIOE_BASE + GPIO_LCKR_OFFSET
+ 633 .equ GPIOE_AFRL, GPIOE_BASE + GPIO_AFRL_OFFSET
+ 634 .equ GPIOE_AFRH, GPIOE_BASE + GPIO_AFRH_OFFSET
+ 635 .equ GPIOE_BRR, GPIOE_BASE + GPIO_BRR_OFFSET
+ 636
+ 637 #--- Port F GPIO configuration / address space: 0x4800_1400 .. 0x4800_17FF
+ 638
+ 639 .equ GPIOF_BASE, GPIO_BASE + 0x1400
+ 640
+ 641 .equ GPIOF_MODER, GPIOF_BASE + GPIO_MODER_OFFSET
+ 642 .equ GPIOF_OTYPER, GPIOF_BASE + GPIO_OTYPER_OFFSET
+ 643 .equ GPIOF_OSPEEDR, GPIOF_BASE + GPIO_OSPEEDR_OFFSET
+ 644 .equ GPIOF_PUPDR, GPIOF_BASE + GPIO_PUPDR_OFFSET
+ 645 .equ GPIOF_IDR, GPIOF_BASE + GPIO_IDR_OFFSET
+ 646 .equ GPIOF_ODR, GPIOF_BASE + GPIO_ODR_OFFSET
+ 647 .equ GPIOF_BSRR, GPIOF_BASE + GPIO_BSRR_OFFSET
+ 648 .equ GPIOF_LCKR, GPIOF_BASE + GPIO_LCKR_OFFSET
+ 649 .equ GPIOF_AFRL, GPIOF_BASE + GPIO_AFRL_OFFSET
+ 650 .equ GPIOF_AFRH, GPIOF_BASE + GPIO_AFRH_OFFSET
+ 651 .equ GPIOF_BRR, GPIOF_BASE + GPIO_BRR_OFFSET
+ 652
+ 653 #--- Port G GPIO configuration / address space: 0x4800_1800 .. 0x4800_1BFF
+ 654
+ 655 .equ GPIOG_BASE, GPIO_BASE + 0x1800
+ 656
+ 657 .equ GPIOG_MODER, GPIOG_BASE + GPIO_MODER_OFFSET
+ 658 .equ GPIOG_OTYPER, GPIOG_BASE + GPIO_OTYPER_OFFSET
+ 659 .equ GPIOG_OSPEEDR, GPIOG_BASE + GPIO_OSPEEDR_OFFSET
+ 660 .equ GPIOG_PUPDR, GPIOG_BASE + GPIO_PUPDR_OFFSET
+ 661 .equ GPIOG_IDR, GPIOG_BASE + GPIO_IDR_OFFSET
+ 662 .equ GPIOG_ODR, GPIOG_BASE + GPIO_ODR_OFFSET
+ 663 .equ GPIOG_BSRR, GPIOG_BASE + GPIO_BSRR_OFFSET
+ 664 .equ GPIOG_LCKR, GPIOG_BASE + GPIO_LCKR_OFFSET
+ 665 .equ GPIOG_AFRL, GPIOG_BASE + GPIO_AFRL_OFFSET
+ 666 .equ GPIOG_AFRH, GPIOG_BASE + GPIO_AFRH_OFFSET
+ 667 .equ GPIOG_BRR, GPIOG_BASE + GPIO_BRR_OFFSET
+ 668
+ 669 #----------------------------------------------------------------------------------------#
+ 670 # System Control Space
+ 671 #
+ 672 # address space: 0xE000_E000 .. 0xE000_EFFF
+ 673 #----------------------------------------------------------------------------------------#
+ 674
+ 675 .equ SCS_BASE, PPB_BASE + 0xE000
+ 676
+ 677 #----------------------------------------------------------------------------------------#
+ 678 # System Timer (SysTick)
+ 679 #
+ 680 # address space: 0xE000_E010 .. 0xE000_E01F
+ 681 #----------------------------------------------------------------------------------------#
+ 682
+ 683 .equ STK_BASE, SCS_BASE + 10 // 0xE000_E010
+ 684
+ 685 .equ STK_CTRL, SCS_BASE + 0x00
+ 686 .equ STK_LOAD, SCS_BASE + 0x04
+ 687 .equ STK_VAL, SCS_BASE + 0x08
+ 688 .equ STK_CALIB, SCS_BASE + 0x0C
+ 689
+ 690 #----------------------------------------------------------------------------------------#
+ 691 # Nested Vector Interrupt Controller
+ 692 #
+ 693 # address space: 0xE000_E100 .. 0xE000_E4EF
+ 694 #----------------------------------------------------------------------------------------#
+ 695
+ 696 .equ NVIC_BASE, SCS_BASE + 0x100 // 0xE000_E100
+ 697
+ 698 .equ NVIC_ISER0, NVIC_BASE + 0x00
+ 699 .equ NVIC_ISER1, NVIC_BASE + 0x04
+ 700 .equ NVIC_ISER2, NVIC_BASE + 0x08
+ 701 .equ NVIC_ISER3, NVIC_BASE + 0x0C
+ 702
+ 703 .equ NVIC_ICER0, NVIC_BASE + 0x80
+ 704 .equ NVIC_ICER1, NVIC_BASE + 0x84
+ 705 .equ NVIC_ICER2, NVIC_BASE + 0x88
+ 706 .equ NVIC_ICER3, NVIC_BASE + 0x8C
+ 707
+ 708 .equ NVIC_ISPR0, NVIC_BASE + 0x100
+ 709 .equ NVIC_ISPR1, NVIC_BASE + 0x104
+ 710 .equ NVIC_ISPR2, NVIC_BASE + 0x108
+ 711 .equ NVIC_ISPR3, NVIC_BASE + 0x10C
+ 712
+ 713 .equ NVIC_ICPR0, NVIC_BASE + 0x180
+ 714 .equ NVIC_ICPR1, NVIC_BASE + 0x184
+ 715 .equ NVIC_ICPR2, NVIC_BASE + 0x188
+ 716 .equ NVIC_ICPR3, NVIC_BASE + 0x18C
+ 717
+ 718 .equ NVIC_IABR0, NVIC_BASE + 0x200
+ 719 .equ NVIC_IABR1, NVIC_BASE + 0x204
+ 720 .equ NVIC_IABR2, NVIC_BASE + 0x208
+ 721 .equ NVIC_IABR3, NVIC_BASE + 0x20C
+ 722
+ 723 .equ NVIC_IPR0, NVIC_BASE + 0x300
+ 724 .equ NVIC_IPR1, NVIC_BASE + 0x304
+ 725 .equ NVIC_IPR2, NVIC_BASE + 0x308
+ 726 .equ NVIC_IPR3, NVIC_BASE + 0x30C
+ 727 .equ NVIC_IPR4, NVIC_BASE + 0x310
+ 728 .equ NVIC_IPR5, NVIC_BASE + 0x314
+ 729 .equ NVIC_IPR6, NVIC_BASE + 0x318
+ 730 .equ NVIC_IPR7, NVIC_BASE + 0x31C
+ 731 .equ NVIC_IPR8, NVIC_BASE + 0x320
+ 732 .equ NVIC_IPR9, NVIC_BASE + 0x324
+ 733 .equ NVIC_IPR10, NVIC_BASE + 0x328
+ 734 .equ NVIC_IPR11, NVIC_BASE + 0x32C
+ 735 .equ NVIC_IPR12, NVIC_BASE + 0x330
+ 736 .equ NVIC_IPR13, NVIC_BASE + 0x334
+ 737 .equ NVIC_IPR14, NVIC_BASE + 0x338
+ 738 .equ NVIC_IPR15, NVIC_BASE + 0x33C
+ 739 .equ NVIC_IPR16, NVIC_BASE + 0x340
+ 740 .equ NVIC_IPR17, NVIC_BASE + 0x344
+ 741 .equ NVIC_IPR18, NVIC_BASE + 0x348
+ 742 .equ NVIC_IPR19, NVIC_BASE + 0x34C
+ 743 .equ NVIC_IPR20, NVIC_BASE + 0x350
+ 744 .equ NVIC_IPR21, NVIC_BASE + 0x354
+ 745 .equ NVIC_IPR22, NVIC_BASE + 0x358
+ 746 .equ NVIC_IPR23, NVIC_BASE + 0x35C
+ 747 .equ NVIC_IPR24, NVIC_BASE + 0x360
+ 748 .equ NVIC_IPR25, NVIC_BASE + 0x364
+ 749
+ 750 .equ STIR, NVIC_BASE + 0xE00
+ 751
+ 752 #----------------------------------------------------------------------------------------#
+ 753 # MCU Debug Component
+ 754 #
+ 755 # address space: 0xE004_2000 .. 0xE004_2013
+ 756 #----------------------------------------------------------------------------------------#
+ 757
+ 758 .equ DBGMCU_BASE, PPB_BASE + 0x42000
+ 759
+ 760 .equ DBGMCU_IDCODE, DBGMCU_BASE + 0x00
+ 761 .equ DBGMCU_CR, DBGMCU_BASE + 0x04
+ 762 .equ DBGMCU_APB1FZR1, DBGMCU_BASE + 0x08
+ 763 .equ DBGMCU_APB1FZR2, DBGMCU_BASE + 0x0C
+ 764 .equ DBGMCU_APB2DZR, DBGMCU_BASE + 0x10
+ 42
+ 43
+ 44 #----------------------------------------------------------------------------------------#
+ 45 .section .vectortable,"a" // vector table at begin of ROM
+ 46 #----------------------------------------------------------------------------------------#
+ 47
+ 48 .align 2
+ 49
+ 50 0000 00400020 .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRA
+ 51 0004 01040008 .word 0x08000401 // initial Program Counter
+ 52 0008 00000000 .word _ISR_NMI // non-masking interrupt
+ 53 000c 00000000 .word _ISR_HARDF // hard fault interrupt
+ 54
+ 55
+ 56
+ 57 /* N.B.
+ 58 Look at the .space or the .org assembler directive to insert the address of the
+ 59 ISRs at the right place in the vector table. Verify your settings by the help of
+ 60 the list file. */
+ 61
+ 62 0010 00000000 .word _ISR_S0
+ 63
+ 64
+ 65 #----------------------------------------------------------------------------------------#
+ 66 .text // section .text (default section for program code)
+ 67 #----------------------------------------------------------------------------------------#
+ 68
+ 69 .align 2
+ 70 .syntax unified
+ 71 .thumb
+ 72 .thumb_func
+ 73 .global init
+ 75 init:
+ 76 0000 72B6 CPSID i // disable interrupts globally
+ 77
+ 78 0002 0020 MOVS r0, #0 // safely initialize the GPRs
+ 79 0004 0021 MOVS r1, #0
+ 80 0006 0022 MOVS r2, #0
+ 81 0008 0023 MOVS r3, #0
+ 82 000a 0024 MOVS r4, #0
+ 83 000c 0025 MOVS r5, #0
+ 84 000e 0026 MOVS r6, #0
+ 85 0010 0027 MOVS r7, #0
+ 86 0012 8046 MOV r8, r0
+ 87 0014 8146 MOV r9, r0
+ 88 0016 8246 MOV r10, r0
+ 89 0018 8346 MOV r11, r0
+ 90 001a 8446 MOV r12, r0
+ 91
+ 92 #--- enable port clocking
+ 93 001c 1249 LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ 94 001e 4FF00102 MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ 95 0022 0868 LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ 96 0024 1043 ORRS r0, r0, r2 // configure clock gating for ports
+ 97 0026 0860 STR r0, [r1, #0] // apply settings
+ 98
+ 99 #--- port init
+ 100 #- LEDs
+ 101 0028 4FF09041 LDR r1, =GPIOA_MODER // load port A mode register address
+ 102 002c 0322 MOVS r2, #0x03 // prepare mask
+ 103 002e 0868 LDR r0, [r1, #0] // get current value of port A mode register
+ 104 0030 9043 BICS r0, r2 // delete bits
+ 105 0032 0122 MOVS r2, #0x01 // load configuration mask
+ 106 0034 1043 ORRS r0, r0, r2 // apply mask
+ 107 0036 0860 STR r0, [r1, #0] // apply result to port A mode register
+ 108
+ 109 # LDR r1, =GPIOB_MODER
+ 110 # MOVS r3, #0x03
+ 111 # LDR r0, [r1, #1]
+ 112 # BICS r0, r3
+ 113 # MOVS r3, #0x01
+ 114 # ORRS r0, r0, r3
+ 115 # STR r0, [r1, #1]
+ 116
+ 117 #- switch LED off
+ 118 0038 0C49 LDR r1, =GPIOA_ODR // load port A output data register
+ 119 003a 0122 MOVS r2, #0x01 // load mask for LED
+ 120 003c 0868 LDR r0, [r1, #0] // get current value of GPIOA
+ 121 003e 1043 ORRS r0, r0, r2 // configure pin state
+ 122 0040 0860 STR r0, [r1, #0] // apply settings
+ 123
+ 124 #- buttons
+ 125
+ 126 /* ... place your code here ... */
+ 127
+ 128
+ 129 #--- button interrupt config
+ 130
+ 131 #- enable clock for SYSCFG module
+ 132
+ 133
+ 134 #- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+ 135 # in SYSCFG module (SYSCFG_* registers)
+ 136
+ 137
+ 138
+ 139
+ 140 #- configure lines in EXTI module (EXTI_* registers)
+ 141
+ 142
+ 143
+ 144 #- NVIC: set interrupt priority, clear pending bits
+ 145 # and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+ 146
+ 147
+ 148
+ 149 0042 62B6 CPSIE i // enable interrupts globally
+ 150
+ 151
+ 152 #----------------------------------------------------------------------------------------#
+ 153
+ 154 .align 2
+ 155 .syntax unified
+ 156 .thumb
+ 157 .thumb_func
+ 158 .global main
+ 160 main:
+ 161 0044 0949 LDR r1, =GPIOA_ODR
+ 162 0046 5040 EORS r0, r0, r2
+ 163
+ 164 0048 0860 STR r0, [r1, #0]
+ 165
+ 166
+ 167
+ 168 004a FFF7FEFF BL delay
+ 169
+ 170
+ 171 004e FFF7FEBF B main
+ 172
+ 173
+ 174 #----------------------------------------------------------------------------------------#
+ 175
+ 176 0052 00BF .align 2
+ 177 .syntax unified
+ 178 .thumb
+ 179 .thumb_func
+ 180 .global delay
+ 182 delay:
+ 183 0054 0026 MOVS r6, #0 // ...
+ 184 0056 064F LDR r7, =2000000 // ...
+ 185 .L1:
+ 186 0058 0136 ADDS r6, r6, #1 // ...
+ 187 005a BE42 CMP r6, r7 // ...
+ 188 005c FCD1 BNE .L1 // ...
+ 189 005e 7047 BX lr // ...
+ 190
+ 191
+ 192 #----------------------------------------------------------------------------------------#
+ 193
+ 194 .align 2
+ 195 .global stop
+ 196 stop:
+ 197 0060 00BF NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ 198 0062 FFF7FEBF B stop // if this line is reached, something went wrong
+ 199
+ 200
+ 201 #----------------------------------------------------------------------------------------#
+ 202 .lp1: // this label is only to nicify the line up in the .lst file
+ 203 0066 00004C10 .ltorg
+ 203 02401400
+ 203 00488084
+ 203 1E00
+ 204 #----------------------------------------------------------------------------------------#
+ 205
+ 206
+ 207 #----------------------------------------------------------------------------------------#
+ 208 .section .exhand,"ax" // section for exception handlers
+ 209 #----------------------------------------------------------------------------------------#
+ 210
+ 211 .align 2
+ 212 .syntax unified
+ 213 .thumb
+ 215 _ISR_NMI:
+ 216 #--- enable clock
+ 217 0000 1749 LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ 218 0002 4FF00102 MOV r2, #0x01 // load mask
+ 219 0006 0868 LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ 220 0008 1043 ORRS r0, r0, r2 // configure clock gating for port
+ 221 000a 0860 STR r0, [r1, #0] // apply settings
+ 222
+ 223 #--- init pins
+ 224 000c 4FF09041 LDR r1, =GPIOA_MODER // load port A mode register address
+ 225 0010 FF22 MOVS r2, #0xFF // prepare mask
+ 226 0012 0868 LDR r0, [r1, #0] // get current value of port A mode register
+ 227 0014 9043 BICS r0, r0, r2 // delete bits
+ 228 0016 4422 MOVS r2, #0x44 // load configuration mask
+ 229 0018 1043 ORRS r0, r0, r2 // configure pins
+ 230 001a 0860 STR r0, [r1, #0] // apply settings to port A mode register
+ 231
+ 232 #--- switch some LEDs on
+ 233 001c 1149 LDR r1, =GPIOA_ODR // load port A data output register address
+ 234 001e 0A22 MOVS r2, #0x0A // load mask for blue and yellow LED
+ 235 0020 0868 LDR r0, [r1, #0]
+ 236 0022 9043 BICS r0, r0, r2
+ 237 0024 0860 STR r0, [r1, #0] // switch LEDs on
+ 238
+ 239 0026 EBE7 B _ISR_NMI
+ 240
+ 241
+ 242 #----------------------------------------------------------------------------------------#
+ 243
+ 244 .align 2
+ 245 .syntax unified
+ 246 .thumb
+ 248 _ISR_HARDF:
+ 249 #--- enable clock
+ 250 0028 0D49 LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ 251 002a 4FF00102 MOV r2, #0x01 // load mask
+ 252 002e 0868 LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ 253 0030 1043 ORRS r0, r0, r2 // configure clock gating for port
+ 254 0032 0860 STR r0, [r1, #0] // apply settings
+ 255
+ 256 #--- init pins
+ 257 0034 4FF09041 LDR r1, =GPIOA_MODER // load port A mode register address
+ 258 0038 FF22 MOVS r2, #0xFF // prepare mask
+ 259 003a 0868 LDR r0, [r1, #0] // get current value of port A mode register
+ 260 003c 9043 BICS r0, r0, r2 // delete bits
+ 261 003e 1122 MOVS r2, #0x11 // load configuration mask
+ 262 0040 1043 ORRS r0, r0, r2 // configure pins
+ 263 0042 0860 STR r0, [r1, #0] // apply settings to port A mode register
+ 264
+ 265 #--- switch some LEDs on
+ 266 0044 0749 LDR r1, =GPIOA_ODR // load port A data output register address
+ 267 0046 0522 MOVS r2, #0x05 // load mask for red and green LED
+ 268 0048 0868 LDR r0, [r1, #0]
+ 269 004a 9043 BICS r0, r0, r2
+ 270 004c 0860 STR r0, [r1, #0] // switch LEDs on
+ 271
+ 272 004e EBE7 B _ISR_HARDF
+ 273
+ 274
+ 275 #----------------------------------------------------------------------------------------#
+ 276
+ 277 .align 2
+ 278 .syntax unified
+ 279 .thumb
+ 281 _ISR_S0:
+ 282 0050 00B5 PUSH {lr} // save special content
+ 283
+ 284 #--- do the work
+ 285
+ 286
+ 287 #--- clear interrupt flag
+ 288
+ 289
+ 290 #--- leave ISR
+ 291 0052 02BC POP {r1} // get special content back
+ 292 0054 0847 BX r1 // go back to where we came from
+ 293
+ 294
+ 295 #----------------------------------------------------------------------------------------#
+ 296
+ 297 0056 00BF .align 2
+ 298 .syntax unified
+ 299 .thumb
+ 301 _ISR_S1:
+ 302 0058 00B5 PUSH {lr} // save special content
+ 303
+ 304 #--- do the work
+ 305
+ 306
+ 307
+ 308
+ 309 #--- clear interrupt flag
+ 310
+ 311
+ 312
+ 313 #--- leave ISR
+ 314 005a 02BC POP {r1} // get special content back
+ 315 005c 0847 BX r1 // go back to where we came from
+ 316
+ 317
+ 318 #----------------------------------------------------------------------------------------#
+ 319 .lp2: // this label is only to nicify the line up in the .lst file
+ 320 005e 00004C10 .ltorg
+ 320 02401400
+ 320 0048
+ 321 #----------------------------------------------------------------------------------------#
+ 322
+ 323 .end
+DEFINED SYMBOLS
+ G431_addr.s:39 *ABS*:40000000 APB1_BASE
+ G431_addr.s:40 *ABS*:40010000 APB2_BASE
+ G431_addr.s:41 *ABS*:40020000 AHB1_BASE
+ G431_addr.s:42 *ABS*:48000000 AHB2_BASE
+ G431_addr.s:43 *ABS*:a0000000 AHB3_BASE
+ G431_addr.s:44 *ABS*:e0000000 PPB_BASE
+ G431_addr.s:52 *ABS*:40010000 SYSCFG_BASE
+ G431_addr.s:54 *ABS*:40010000 SYSCFG_MEMRMP
+ G431_addr.s:55 *ABS*:40010004 SYSCFG_CFGR1
+ G431_addr.s:56 *ABS*:40010008 SYSCFG_EXTICR1
+ G431_addr.s:57 *ABS*:4001000c SYSCFG_EXTICR2
+ G431_addr.s:58 *ABS*:40010010 SYSCFG_EXTICR3
+ G431_addr.s:59 *ABS*:40010014 SYSCFG_EXTICR4
+ G431_addr.s:60 *ABS*:40010018 SYSCFG_SCSR
+ G431_addr.s:61 *ABS*:4001001c SYSCFG_CFGR2
+ G431_addr.s:62 *ABS*:40010020 SYSCFG_SWPR
+ G431_addr.s:63 *ABS*:40010024 SYSCFG_SKR
+ G431_addr.s:71 *ABS*:40010400 EXTI_BASE
+ G431_addr.s:73 *ABS*:40010400 EXTI_IMR1
+ G431_addr.s:74 *ABS*:40010404 EXTI_EMR1
+ G431_addr.s:75 *ABS*:40010408 EXTI_RTSR1
+ G431_addr.s:76 *ABS*:4001040c EXTI_FTSR1
+ G431_addr.s:77 *ABS*:40010410 EXTI_SWIER1
+ G431_addr.s:78 *ABS*:40010414 EXTI_PR1
+ G431_addr.s:80 *ABS*:40010420 EXTI_IMR2
+ G431_addr.s:81 *ABS*:40010424 EXTI_EMR2
+ G431_addr.s:82 *ABS*:40010428 EXTI_RTSR2
+ G431_addr.s:83 *ABS*:4001042c EXTI_FTSR2
+ G431_addr.s:84 *ABS*:40010430 EXTI_SWIER2
+ G431_addr.s:85 *ABS*:40010434 EXTI_PR2
+ G431_addr.s:109 *ABS*:00000000 TIM_CR1_OFFSET
+ G431_addr.s:110 *ABS*:00000004 TIM_CR2_OFFSET
+ G431_addr.s:111 *ABS*:00000008 TIM_SMCR_OFFSET
+ G431_addr.s:112 *ABS*:0000000c TIM_DIER_OFFSET
+ G431_addr.s:113 *ABS*:00000010 TIM_SR_OFFSET
+ G431_addr.s:114 *ABS*:00000014 TIM_EGR_OFFSET
+ G431_addr.s:115 *ABS*:00000018 TIM_CCMR1_OFFSET
+ G431_addr.s:116 *ABS*:0000001c TIM_CCMR2_OFFSET
+ G431_addr.s:117 *ABS*:00000020 TIM_CCER_OFFSET
+ G431_addr.s:118 *ABS*:00000024 TIM_CNT_OFFSET
+ G431_addr.s:119 *ABS*:00000028 TIM_PSC_OFFSET
+ G431_addr.s:120 *ABS*:0000002c TIM_ARR_OFFSET
+ G431_addr.s:121 *ABS*:00000030 TIM_RCR_OFFSET
+ G431_addr.s:122 *ABS*:00000034 TIM_CCR1_OFFSET
+ G431_addr.s:123 *ABS*:00000038 TIM_CCR2_OFFSET
+ G431_addr.s:124 *ABS*:0000003c TIM_CCR3_OFFSET
+ G431_addr.s:125 *ABS*:00000040 TIM_CCR4_OFFSET
+ G431_addr.s:126 *ABS*:00000044 TIM_BDTR_OFFSET
+ G431_addr.s:127 *ABS*:00000048 TIM_CCR5_OFFSET
+ G431_addr.s:128 *ABS*:0000004c TIM_CCR6_OFFSET
+ G431_addr.s:129 *ABS*:00000050 TIM_CCMR3_OFFSET
+ G431_addr.s:130 *ABS*:00000054 TIM_DTR2_OFFSET
+ G431_addr.s:131 *ABS*:00000058 TIM_ECR_OFFSET
+ G431_addr.s:132 *ABS*:0000005c TIM_TISEL_OFFSET
+ G431_addr.s:133 *ABS*:00000060 TIM_AF1_OFFSET
+ G431_addr.s:134 *ABS*:00000064 TIM_AF2_OFFSET
+ G431_addr.s:135 *ABS*:00000068 TIM_OR1_OFFSET
+ G431_addr.s:137 *ABS*:000003dc TIM_DCR_OFFSET
+ G431_addr.s:138 *ABS*:000003e0 TIM_DMAR_OFFSET
+ G431_addr.s:144 *ABS*:40000000 TIM2_BASE
+ G431_addr.s:146 *ABS*:40000000 TIM2_CR1
+ G431_addr.s:147 *ABS*:40000004 TIM2_CR2
+ G431_addr.s:148 *ABS*:40000008 TIM2_SMCR
+ G431_addr.s:149 *ABS*:4000000c TIM2_DIER
+ G431_addr.s:150 *ABS*:40000010 TIM2_SR
+ G431_addr.s:151 *ABS*:40000014 TIM2_EGR
+ G431_addr.s:152 *ABS*:40000018 TIM2_CCMR1
+ G431_addr.s:153 *ABS*:4000001c TIM2_CCMR2
+ G431_addr.s:154 *ABS*:40000020 TIM2_CCER
+ G431_addr.s:155 *ABS*:40000024 TIM2_CNT
+ G431_addr.s:156 *ABS*:40000028 TIM2_PSC
+ G431_addr.s:157 *ABS*:4000002c TIM2_ARR
+ G431_addr.s:159 *ABS*:40000034 TIM2_CCR1
+ G431_addr.s:160 *ABS*:40000038 TIM2_CCR2
+ G431_addr.s:161 *ABS*:4000003c TIM2_CCR3
+ G431_addr.s:162 *ABS*:40000040 TIM2_CCR4
+ G431_addr.s:164 *ABS*:40000058 TIM2_ECR
+ G431_addr.s:165 *ABS*:4000005c TIM2_TISEL
+ G431_addr.s:166 *ABS*:40000058 TIM2_AF1
+ G431_addr.s:167 *ABS*:40000058 TIM2_AF2
+ G431_addr.s:169 *ABS*:400003dc TIM2_DCR
+ G431_addr.s:170 *ABS*:400003e0 TIM2_DMAR
+ G431_addr.s:174 *ABS*:40000400 TIM3_BASE
+ G431_addr.s:176 *ABS*:40000400 TIM3_CR1
+ G431_addr.s:177 *ABS*:40000404 TIM3_CR2
+ G431_addr.s:178 *ABS*:40000408 TIM3_SMCR
+ G431_addr.s:179 *ABS*:4000040c TIM3_DIER
+ G431_addr.s:180 *ABS*:40000410 TIM3_SR
+ G431_addr.s:181 *ABS*:40000414 TIM3_EGR
+ G431_addr.s:182 *ABS*:40000418 TIM3_CCMR1
+ G431_addr.s:183 *ABS*:4000041c TIM3_CCMR2
+ G431_addr.s:184 *ABS*:40000420 TIM3_CCER
+ G431_addr.s:185 *ABS*:40000424 TIM3_CNT
+ G431_addr.s:186 *ABS*:40000428 TIM3_PSC
+ G431_addr.s:187 *ABS*:4000042c TIM3_ARR
+ G431_addr.s:189 *ABS*:40000434 TIM3_CCR1
+ G431_addr.s:190 *ABS*:40000438 TIM3_CCR2
+ G431_addr.s:191 *ABS*:4000043c TIM3_CCR3
+ G431_addr.s:192 *ABS*:40000440 TIM3_CCR4
+ G431_addr.s:194 *ABS*:40000458 TIM3_ECR
+ G431_addr.s:195 *ABS*:4000045c TIM3_TISEL
+ G431_addr.s:196 *ABS*:40000458 TIM3_AF1
+ G431_addr.s:197 *ABS*:40000458 TIM3_AF2
+ G431_addr.s:199 *ABS*:400007dc TIM3_DCR
+ G431_addr.s:200 *ABS*:400007e0 TIM3_DMAR
+ G431_addr.s:204 *ABS*:40000800 TIM4_BASE
+ G431_addr.s:206 *ABS*:40000800 TIM4_CR1
+ G431_addr.s:207 *ABS*:40000804 TIM4_CR2
+ G431_addr.s:208 *ABS*:40000808 TIM4_SMCR
+ G431_addr.s:209 *ABS*:4000080c TIM4_DIER
+ G431_addr.s:210 *ABS*:40000810 TIM4_SR
+ G431_addr.s:211 *ABS*:40000814 TIM4_EGR
+ G431_addr.s:212 *ABS*:40000818 TIM4_CCMR1
+ G431_addr.s:213 *ABS*:4000081c TIM4_CCMR2
+ G431_addr.s:214 *ABS*:40000820 TIM4_CCER
+ G431_addr.s:215 *ABS*:40000824 TIM4_CNT
+ G431_addr.s:216 *ABS*:40000828 TIM4_PSC
+ G431_addr.s:217 *ABS*:4000082c TIM4_ARR
+ G431_addr.s:219 *ABS*:40000834 TIM4_CCR1
+ G431_addr.s:220 *ABS*:40000838 TIM4_CCR2
+ G431_addr.s:221 *ABS*:4000083c TIM4_CCR3
+ G431_addr.s:222 *ABS*:40000840 TIM4_CCR4
+ G431_addr.s:224 *ABS*:40000858 TIM4_ECR
+ G431_addr.s:225 *ABS*:4000085c TIM4_TISEL
+ G431_addr.s:226 *ABS*:40000858 TIM4_AF1
+ G431_addr.s:227 *ABS*:40000858 TIM4_AF2
+ G431_addr.s:229 *ABS*:40000bdc TIM4_DCR
+ G431_addr.s:230 *ABS*:40000be0 TIM4_DMAR
+ G431_addr.s:234 *ABS*:40000c00 TIM5_BASE
+ G431_addr.s:236 *ABS*:40000c00 TIM5_CR1
+ G431_addr.s:237 *ABS*:40000c04 TIM5_CR2
+ G431_addr.s:238 *ABS*:40000c08 TIM5_SMCR
+ G431_addr.s:239 *ABS*:40000c0c TIM5_DIER
+ G431_addr.s:240 *ABS*:40000c10 TIM5_SR
+ G431_addr.s:241 *ABS*:40000c14 TIM5_EGR
+ G431_addr.s:242 *ABS*:40000c18 TIM5_CCMR1
+ G431_addr.s:243 *ABS*:40000c1c TIM5_CCMR2
+ G431_addr.s:244 *ABS*:40000c20 TIM5_CCER
+ G431_addr.s:245 *ABS*:40000c24 TIM5_CNT
+ G431_addr.s:246 *ABS*:40000c28 TIM5_PSC
+ G431_addr.s:247 *ABS*:40000c2c TIM5_ARR
+ G431_addr.s:249 *ABS*:40000c34 TIM5_CCR1
+ G431_addr.s:250 *ABS*:40000c38 TIM5_CCR2
+ G431_addr.s:251 *ABS*:40000c3c TIM5_CCR3
+ G431_addr.s:252 *ABS*:40000c40 TIM5_CCR4
+ G431_addr.s:254 *ABS*:40000c58 TIM5_ECR
+ G431_addr.s:255 *ABS*:40000c5c TIM5_TISEL
+ G431_addr.s:256 *ABS*:40000c58 TIM5_AF1
+ G431_addr.s:257 *ABS*:40000c58 TIM5_AF2
+ G431_addr.s:259 *ABS*:40000fdc TIM5_DCR
+ G431_addr.s:260 *ABS*:40000fe0 TIM5_DMAR
+ G431_addr.s:264 *ABS*:40001000 TIM6_BASE
+ G431_addr.s:266 *ABS*:40001000 TIM6_CR1
+ G431_addr.s:267 *ABS*:40001004 TIM6_CR2
+ G431_addr.s:269 *ABS*:4000100c TIM6_DIER
+ G431_addr.s:270 *ABS*:40001010 TIM6_SR
+ G431_addr.s:271 *ABS*:40001014 TIM6_EGR
+ G431_addr.s:273 *ABS*:40001024 TIM6_CNT
+ G431_addr.s:274 *ABS*:40001028 TIM6_PSC
+ G431_addr.s:275 *ABS*:4000102c TIM6_ARR
+ G431_addr.s:279 *ABS*:40001400 TIM7_BASE
+ G431_addr.s:281 *ABS*:40001400 TIM7_CR1
+ G431_addr.s:282 *ABS*:40001404 TIM7_CR2
+ G431_addr.s:284 *ABS*:4000140c TIM7_DIER
+ G431_addr.s:285 *ABS*:40001410 TIM7_SR
+ G431_addr.s:286 *ABS*:40001414 TIM7_EGR
+ G431_addr.s:288 *ABS*:40001424 TIM7_CNT
+ G431_addr.s:289 *ABS*:40001428 TIM7_PSC
+ G431_addr.s:290 *ABS*:4000142c TIM7_ARR
+ G431_addr.s:294 *ABS*:40012c00 TIM1_BASE
+ G431_addr.s:296 *ABS*:40012c00 TIM1_CR1
+ G431_addr.s:297 *ABS*:40012c04 TIM1_CR2
+ G431_addr.s:298 *ABS*:40012c08 TIM1_SMCR
+ G431_addr.s:299 *ABS*:40012c0c TIM1_DIER
+ G431_addr.s:300 *ABS*:40012c10 TIM1_SR
+ G431_addr.s:301 *ABS*:40012c14 TIM1_EGR
+ G431_addr.s:302 *ABS*:40012c18 TIM1_CCMR1
+ G431_addr.s:303 *ABS*:40012c1c TIM1_CCMR2
+ G431_addr.s:304 *ABS*:40012c20 TIM1_CCER
+ G431_addr.s:305 *ABS*:40012c24 TIM1_CNT
+ G431_addr.s:306 *ABS*:40012c28 TIM1_PSC
+ G431_addr.s:307 *ABS*:40012c2c TIM1_ARR
+ G431_addr.s:308 *ABS*:40012c30 TIM1_RCR
+ G431_addr.s:309 *ABS*:40012c34 TIM1_CCR1
+ G431_addr.s:310 *ABS*:40012c38 TIM1_CCR2
+ G431_addr.s:311 *ABS*:40012c3c TIM1_CCR3
+ G431_addr.s:312 *ABS*:40012c40 TIM1_CCR4
+ G431_addr.s:313 *ABS*:40012c44 TIM1_BDTR
+ G431_addr.s:314 *ABS*:40012c48 TIM1_CCR5
+ G431_addr.s:315 *ABS*:40012c4c TIM1_CCR6
+ G431_addr.s:316 *ABS*:40012c50 TIM1_CCMR3
+ G431_addr.s:317 *ABS*:40012c54 TIM1_DTR2
+ G431_addr.s:318 *ABS*:40012c58 TIM1_ECR
+ G431_addr.s:319 *ABS*:40012c5c TIM1_TISEL
+ G431_addr.s:320 *ABS*:40012c60 TIM1_AF1
+ G431_addr.s:321 *ABS*:40012c64 TIM1_AF2
+ G431_addr.s:323 *ABS*:40012fdc TIM1_DCR
+ G431_addr.s:324 *ABS*:40012fe0 TIM1_DMAR
+ G431_addr.s:328 *ABS*:40013400 TIM8_BASE
+ G431_addr.s:330 *ABS*:40013400 TIM8_CR1
+ G431_addr.s:331 *ABS*:40013404 TIM8_CR2
+ G431_addr.s:332 *ABS*:40013408 TIM8_SMCR
+ G431_addr.s:333 *ABS*:4001340c TIM8_DIER
+ G431_addr.s:334 *ABS*:40013410 TIM8_SR
+ G431_addr.s:335 *ABS*:40013414 TIM8_EGR
+ G431_addr.s:336 *ABS*:40013418 TIM8_CCMR1
+ G431_addr.s:337 *ABS*:4001341c TIM8_CCMR2
+ G431_addr.s:338 *ABS*:40013420 TIM8_CCER
+ G431_addr.s:339 *ABS*:40013424 TIM8_CNT
+ G431_addr.s:340 *ABS*:40013428 TIM8_PSC
+ G431_addr.s:341 *ABS*:4001342c TIM8_ARR
+ G431_addr.s:342 *ABS*:40013430 TIM8_RCR
+ G431_addr.s:343 *ABS*:40013434 TIM8_CCR1
+ G431_addr.s:344 *ABS*:40013438 TIM8_CCR2
+ G431_addr.s:345 *ABS*:4001343c TIM8_CCR3
+ G431_addr.s:346 *ABS*:40013440 TIM8_CCR4
+ G431_addr.s:347 *ABS*:40013444 TIM8_BDTR
+ G431_addr.s:348 *ABS*:40013448 TIM8_CCR5
+ G431_addr.s:349 *ABS*:4001344c TIM8_CCR6
+ G431_addr.s:350 *ABS*:40013450 TIM8_CCMR3
+ G431_addr.s:351 *ABS*:40013454 TIM8_DTR2
+ G431_addr.s:352 *ABS*:40013458 TIM8_ECR
+ G431_addr.s:353 *ABS*:4001345c TIM8_TISEL
+ G431_addr.s:354 *ABS*:40013460 TIM8_AF1
+ G431_addr.s:355 *ABS*:40013464 TIM8_AF2
+ G431_addr.s:357 *ABS*:400137dc TIM8_DCR
+ G431_addr.s:358 *ABS*:400137e0 TIM8_DMAR
+ G431_addr.s:362 *ABS*:40015000 TIM20_BASE
+ G431_addr.s:364 *ABS*:40015000 TIM20_CR1
+ G431_addr.s:365 *ABS*:40015004 TIM20_CR2
+ G431_addr.s:366 *ABS*:40015008 TIM20_SMCR
+ G431_addr.s:367 *ABS*:4001500c TIM20_DIER
+ G431_addr.s:368 *ABS*:40015010 TIM20_SR
+ G431_addr.s:369 *ABS*:40015014 TIM20_EGR
+ G431_addr.s:370 *ABS*:40015018 TIM20_CCMR1
+ G431_addr.s:371 *ABS*:4001501c TIM20_CCMR2
+ G431_addr.s:372 *ABS*:40015020 TIM20_CCER
+ G431_addr.s:373 *ABS*:40015024 TIM20_CNT
+ G431_addr.s:374 *ABS*:40015028 TIM20_PSC
+ G431_addr.s:375 *ABS*:4001502c TIM20_ARR
+ G431_addr.s:376 *ABS*:40015030 TIM20_RCR
+ G431_addr.s:377 *ABS*:40015034 TIM20_CCR1
+ G431_addr.s:378 *ABS*:40015038 TIM20_CCR2
+ G431_addr.s:379 *ABS*:4001503c TIM20_CCR3
+ G431_addr.s:380 *ABS*:40015040 TIM20_CCR4
+ G431_addr.s:381 *ABS*:40015044 TIM20_BDTR
+ G431_addr.s:382 *ABS*:40015048 TIM20_CCR5
+ G431_addr.s:383 *ABS*:4001504c TIM20_CCR6
+ G431_addr.s:384 *ABS*:40015050 TIM20_CCMR3
+ G431_addr.s:385 *ABS*:40015054 TIM20_DTR2
+ G431_addr.s:386 *ABS*:40015058 TIM20_ECR
+ G431_addr.s:387 *ABS*:4001505c TIM20_TISEL
+ G431_addr.s:388 *ABS*:40015060 TIM20_AF1
+ G431_addr.s:389 *ABS*:40015064 TIM20_AF2
+ G431_addr.s:391 *ABS*:400153dc TIM20_DCR
+ G431_addr.s:392 *ABS*:400153e0 TIM20_DMAR
+ G431_addr.s:396 *ABS*:40014000 TIM15_BASE
+ G431_addr.s:398 *ABS*:40014000 TIM15_CR1
+ G431_addr.s:399 *ABS*:40014004 TIM15_CR2
+ G431_addr.s:400 *ABS*:40014008 TIM15_SMCR
+ G431_addr.s:401 *ABS*:4001400c TIM15_DIER
+ G431_addr.s:402 *ABS*:40014010 TIM15_SR
+ G431_addr.s:403 *ABS*:40014014 TIM15_EGR
+ G431_addr.s:404 *ABS*:40014018 TIM15_CCMR1
+ G431_addr.s:406 *ABS*:40014020 TIM15_CCER
+ G431_addr.s:407 *ABS*:40014024 TIM15_CNT
+ G431_addr.s:408 *ABS*:40014028 TIM15_PSC
+ G431_addr.s:409 *ABS*:4001402c TIM15_ARR
+ G431_addr.s:410 *ABS*:40014030 TIM15_RCR
+ G431_addr.s:411 *ABS*:40014034 TIM15_CCR1
+ G431_addr.s:412 *ABS*:40014038 TIM15_CCR2
+ G431_addr.s:414 *ABS*:40014044 TIM15_BDTR
+ G431_addr.s:416 *ABS*:40014054 TIM15_DTR2
+ G431_addr.s:418 *ABS*:4001405c TIM15_TISEL
+ G431_addr.s:419 *ABS*:40014060 TIM15_AF1
+ G431_addr.s:420 *ABS*:40014064 TIM15_AF2
+ G431_addr.s:422 *ABS*:400143dc TIM15_DCR
+ G431_addr.s:423 *ABS*:400143e0 TIM15_DMAR
+ G431_addr.s:427 *ABS*:40014400 TIM16_BASE
+ G431_addr.s:429 *ABS*:40014400 TIM16_CR1
+ G431_addr.s:430 *ABS*:40014404 TIM16_CR2
+ G431_addr.s:432 *ABS*:4001440c TIM16_DIER
+ G431_addr.s:433 *ABS*:40014410 TIM16_SR
+ G431_addr.s:434 *ABS*:40014414 TIM16_EGR
+ G431_addr.s:435 *ABS*:40014418 TIM16_CCMR1
+ G431_addr.s:437 *ABS*:40014420 TIM16_CCER
+ G431_addr.s:438 *ABS*:40014424 TIM16_CNT
+ G431_addr.s:439 *ABS*:40014428 TIM16_PSC
+ G431_addr.s:440 *ABS*:4001442c TIM16_ARR
+ G431_addr.s:441 *ABS*:40014430 TIM16_RCR
+ G431_addr.s:442 *ABS*:40014434 TIM16_CCR1
+ G431_addr.s:444 *ABS*:40014444 TIM16_BDTR
+ G431_addr.s:446 *ABS*:40014454 TIM16_DTR2
+ G431_addr.s:448 *ABS*:4001445c TIM16_TISEL
+ G431_addr.s:449 *ABS*:40014460 TIM16_AF1
+ G431_addr.s:450 *ABS*:40014464 TIM16_AF2
+ G431_addr.s:451 *ABS*:40014468 TIM16_OR1
+ G431_addr.s:453 *ABS*:400147dc TIM16_DCR
+ G431_addr.s:454 *ABS*:400147e0 TIM16_DMAR
+ G431_addr.s:458 *ABS*:40014800 TIM17_BASE
+ G431_addr.s:460 *ABS*:40014800 TIM17_CR1
+ G431_addr.s:461 *ABS*:40014804 TIM17_CR2
+ G431_addr.s:463 *ABS*:4001480c TIM17_DIER
+ G431_addr.s:464 *ABS*:40014810 TIM17_SR
+ G431_addr.s:465 *ABS*:40014814 TIM17_EGR
+ G431_addr.s:466 *ABS*:40014818 TIM17_CCMR1
+ G431_addr.s:468 *ABS*:40014820 TIM17_CCER
+ G431_addr.s:469 *ABS*:40014824 TIM17_CNT
+ G431_addr.s:470 *ABS*:40014828 TIM17_PSC
+ G431_addr.s:471 *ABS*:4001482c TIM17_ARR
+ G431_addr.s:472 *ABS*:40014830 TIM17_RCR
+ G431_addr.s:473 *ABS*:40014834 TIM17_CCR1
+ G431_addr.s:475 *ABS*:40014844 TIM17_BDTR
+ G431_addr.s:477 *ABS*:40014854 TIM17_DTR2
+ G431_addr.s:479 *ABS*:4001485c TIM17_TISEL
+ G431_addr.s:480 *ABS*:40014860 TIM17_AF1
+ G431_addr.s:481 *ABS*:40014864 TIM17_AF2
+ G431_addr.s:482 *ABS*:40014868 TIM17_OR1
+ G431_addr.s:484 *ABS*:40014bdc TIM17_DCR
+ G431_addr.s:485 *ABS*:40014be0 TIM17_DMAR
+ G431_addr.s:493 *ABS*:40021000 RCC_BASE
+ G431_addr.s:495 *ABS*:40021000 RCC_CR
+ G431_addr.s:496 *ABS*:40021004 RCC_ICSCR
+ G431_addr.s:497 *ABS*:40021008 RCC_CFGR
+ G431_addr.s:498 *ABS*:4002100c RCC_PLLCFGR
+ G431_addr.s:500 *ABS*:40021018 RCC_CIER
+ G431_addr.s:501 *ABS*:4002101c RCC_CIFR
+ G431_addr.s:502 *ABS*:40021020 RCC_CICR
+ G431_addr.s:504 *ABS*:40021028 RCC_AHB1RSTR
+ G431_addr.s:505 *ABS*:4002102c RCC_AHB2RSTR
+ G431_addr.s:506 *ABS*:40021030 RCC_AHB3RSTR
+ G431_addr.s:508 *ABS*:40021038 RCC_APB1RSTR1
+ G431_addr.s:509 *ABS*:4002103c RCC_APB1RSTR2
+ G431_addr.s:510 *ABS*:40021040 RCC_APB2RSTR
+ G431_addr.s:512 *ABS*:40021048 RCC_AHB1ENR
+ G431_addr.s:513 *ABS*:4002104c RCC_AHB2ENR
+ G431_addr.s:514 *ABS*:40021050 RCC_AHB3ENR
+ G431_addr.s:516 *ABS*:40021058 RCC_APB1ENR1
+ G431_addr.s:517 *ABS*:4002105c RCC_APB1ENR2
+ G431_addr.s:518 *ABS*:40021060 RCC_APB2ENR
+ G431_addr.s:520 *ABS*:40021068 RCC_AHB1SMENR
+ G431_addr.s:521 *ABS*:4002106c RCC_AHB2SMENR
+ G431_addr.s:522 *ABS*:40021070 RCC_AHB3SMENR
+ G431_addr.s:524 *ABS*:40021078 RCC_APB1SMENR1
+ G431_addr.s:525 *ABS*:4002107c RCC_APB1SMENR2
+ G431_addr.s:526 *ABS*:40021080 RCC_APB2SMENR
+ G431_addr.s:528 *ABS*:40021088 RCC_CCIPR
+ G431_addr.s:530 *ABS*:40021090 RCC_BDCR
+ G431_addr.s:531 *ABS*:40021094 RCC_CSR
+ G431_addr.s:532 *ABS*:40021098 RCC_CRRCR
+ G431_addr.s:533 *ABS*:4002109c RCC_CCIPR2
+ G431_addr.s:541 *ABS*:48000000 GPIO_BASE
+ G431_addr.s:543 *ABS*:00000000 GPIO_MODER_OFFSET
+ G431_addr.s:544 *ABS*:00000004 GPIO_OTYPER_OFFSET
+ G431_addr.s:545 *ABS*:00000008 GPIO_OSPEEDR_OFFSET
+ G431_addr.s:546 *ABS*:0000000c GPIO_PUPDR_OFFSET
+ G431_addr.s:547 *ABS*:00000010 GPIO_IDR_OFFSET
+ G431_addr.s:548 *ABS*:00000014 GPIO_ODR_OFFSET
+ G431_addr.s:549 *ABS*:00000018 GPIO_BSRR_OFFSET
+ G431_addr.s:550 *ABS*:0000001c GPIO_LCKR_OFFSET
+ G431_addr.s:551 *ABS*:00000020 GPIO_AFRL_OFFSET
+ G431_addr.s:552 *ABS*:00000024 GPIO_AFRH_OFFSET
+ G431_addr.s:553 *ABS*:00000028 GPIO_BRR_OFFSET
+ G431_addr.s:559 *ABS*:48000000 GPIOA_BASE
+ G431_addr.s:561 *ABS*:48000000 GPIOA_MODER
+ G431_addr.s:562 *ABS*:48000004 GPIOA_OTYPER
+ G431_addr.s:563 *ABS*:48000008 GPIOA_OSPEEDR
+ G431_addr.s:564 *ABS*:4800000c GPIOA_PUPDR
+ G431_addr.s:565 *ABS*:48000010 GPIOA_IDR
+ G431_addr.s:566 *ABS*:48000014 GPIOA_ODR
+ G431_addr.s:567 *ABS*:48000018 GPIOA_BSRR
+ G431_addr.s:568 *ABS*:4800001c GPIOA_LCKR
+ G431_addr.s:569 *ABS*:48000020 GPIOA_AFRL
+ G431_addr.s:570 *ABS*:48000024 GPIOA_AFRH
+ G431_addr.s:571 *ABS*:48000028 GPIOA_BRR
+ G431_addr.s:575 *ABS*:48000400 GPIOB_BASE
+ G431_addr.s:577 *ABS*:48000400 GPIOB_MODER
+ G431_addr.s:578 *ABS*:48000404 GPIOB_OTYPER
+ G431_addr.s:579 *ABS*:48000408 GPIOB_OSPEEDR
+ G431_addr.s:580 *ABS*:4800040c GPIOB_PUPDR
+ G431_addr.s:581 *ABS*:48000410 GPIOB_IDR
+ G431_addr.s:582 *ABS*:48000414 GPIOB_ODR
+ G431_addr.s:583 *ABS*:48000418 GPIOB_BSRR
+ G431_addr.s:584 *ABS*:4800041c GPIOB_LCKR
+ G431_addr.s:585 *ABS*:48000420 GPIOB_AFRL
+ G431_addr.s:586 *ABS*:48000424 GPIOB_AFRH
+ G431_addr.s:587 *ABS*:48000428 GPIOB_BRR
+ G431_addr.s:591 *ABS*:48000800 GPIOC_BASE
+ G431_addr.s:593 *ABS*:48000800 GPIOC_MODER
+ G431_addr.s:594 *ABS*:48000804 GPIOC_OTYPER
+ G431_addr.s:595 *ABS*:48000808 GPIOC_OSPEEDR
+ G431_addr.s:596 *ABS*:4800080c GPIOC_PUPDR
+ G431_addr.s:597 *ABS*:48000810 GPIOC_IDR
+ G431_addr.s:598 *ABS*:48000814 GPIOC_ODR
+ G431_addr.s:599 *ABS*:48000818 GPIOC_BSRR
+ G431_addr.s:600 *ABS*:4800081c GPIOC_LCKR
+ G431_addr.s:601 *ABS*:48000820 GPIOC_AFRL
+ G431_addr.s:602 *ABS*:48000824 GPIOC_AFRH
+ G431_addr.s:603 *ABS*:48000828 GPIOC_BRR
+ G431_addr.s:607 *ABS*:48000c00 GPIOD_BASE
+ G431_addr.s:609 *ABS*:48000c00 GPIOD_MODER
+ G431_addr.s:610 *ABS*:48000c04 GPIOD_OTYPER
+ G431_addr.s:611 *ABS*:48000c08 GPIOD_OSPEEDR
+ G431_addr.s:612 *ABS*:48000c0c GPIOD_PUPDR
+ G431_addr.s:613 *ABS*:48000c10 GPIOD_IDR
+ G431_addr.s:614 *ABS*:48000c14 GPIOD_ODR
+ G431_addr.s:615 *ABS*:48000c18 GPIOD_BSRR
+ G431_addr.s:616 *ABS*:48000c1c GPIOD_LCKR
+ G431_addr.s:617 *ABS*:48000c20 GPIOD_AFRL
+ G431_addr.s:618 *ABS*:48000c24 GPIOD_AFRH
+ G431_addr.s:619 *ABS*:48000c28 GPIOD_BRR
+ G431_addr.s:623 *ABS*:48001000 GPIOE_BASE
+ G431_addr.s:625 *ABS*:48001000 GPIOE_MODER
+ G431_addr.s:626 *ABS*:48001004 GPIOE_OTYPER
+ G431_addr.s:627 *ABS*:48001008 GPIOE_OSPEEDR
+ G431_addr.s:628 *ABS*:4800100c GPIOE_PUPDR
+ G431_addr.s:629 *ABS*:48001010 GPIOE_IDR
+ G431_addr.s:630 *ABS*:48001014 GPIOE_ODR
+ G431_addr.s:631 *ABS*:48001018 GPIOE_BSRR
+ G431_addr.s:632 *ABS*:4800101c GPIOE_LCKR
+ G431_addr.s:633 *ABS*:48001020 GPIOE_AFRL
+ G431_addr.s:634 *ABS*:48001024 GPIOE_AFRH
+ G431_addr.s:635 *ABS*:48001028 GPIOE_BRR
+ G431_addr.s:639 *ABS*:48001400 GPIOF_BASE
+ G431_addr.s:641 *ABS*:48001400 GPIOF_MODER
+ G431_addr.s:642 *ABS*:48001404 GPIOF_OTYPER
+ G431_addr.s:643 *ABS*:48001408 GPIOF_OSPEEDR
+ G431_addr.s:644 *ABS*:4800140c GPIOF_PUPDR
+ G431_addr.s:645 *ABS*:48001410 GPIOF_IDR
+ G431_addr.s:646 *ABS*:48001414 GPIOF_ODR
+ G431_addr.s:647 *ABS*:48001418 GPIOF_BSRR
+ G431_addr.s:648 *ABS*:4800141c GPIOF_LCKR
+ G431_addr.s:649 *ABS*:48001420 GPIOF_AFRL
+ G431_addr.s:650 *ABS*:48001424 GPIOF_AFRH
+ G431_addr.s:651 *ABS*:48001428 GPIOF_BRR
+ G431_addr.s:655 *ABS*:48001800 GPIOG_BASE
+ G431_addr.s:657 *ABS*:48001800 GPIOG_MODER
+ G431_addr.s:658 *ABS*:48001804 GPIOG_OTYPER
+ G431_addr.s:659 *ABS*:48001808 GPIOG_OSPEEDR
+ G431_addr.s:660 *ABS*:4800180c GPIOG_PUPDR
+ G431_addr.s:661 *ABS*:48001810 GPIOG_IDR
+ G431_addr.s:662 *ABS*:48001814 GPIOG_ODR
+ G431_addr.s:663 *ABS*:48001818 GPIOG_BSRR
+ G431_addr.s:664 *ABS*:4800181c GPIOG_LCKR
+ G431_addr.s:665 *ABS*:48001820 GPIOG_AFRL
+ G431_addr.s:666 *ABS*:48001824 GPIOG_AFRH
+ G431_addr.s:667 *ABS*:48001828 GPIOG_BRR
+ G431_addr.s:675 *ABS*:e000e000 SCS_BASE
+ G431_addr.s:683 *ABS*:e000e00a STK_BASE
+ G431_addr.s:685 *ABS*:e000e000 STK_CTRL
+ G431_addr.s:686 *ABS*:e000e004 STK_LOAD
+ G431_addr.s:687 *ABS*:e000e008 STK_VAL
+ G431_addr.s:688 *ABS*:e000e00c STK_CALIB
+ G431_addr.s:696 *ABS*:e000e100 NVIC_BASE
+ G431_addr.s:698 *ABS*:e000e100 NVIC_ISER0
+ G431_addr.s:699 *ABS*:e000e104 NVIC_ISER1
+ G431_addr.s:700 *ABS*:e000e108 NVIC_ISER2
+ G431_addr.s:701 *ABS*:e000e10c NVIC_ISER3
+ G431_addr.s:703 *ABS*:e000e180 NVIC_ICER0
+ G431_addr.s:704 *ABS*:e000e184 NVIC_ICER1
+ G431_addr.s:705 *ABS*:e000e188 NVIC_ICER2
+ G431_addr.s:706 *ABS*:e000e18c NVIC_ICER3
+ G431_addr.s:708 *ABS*:e000e200 NVIC_ISPR0
+ G431_addr.s:709 *ABS*:e000e204 NVIC_ISPR1
+ G431_addr.s:710 *ABS*:e000e208 NVIC_ISPR2
+ G431_addr.s:711 *ABS*:e000e20c NVIC_ISPR3
+ G431_addr.s:713 *ABS*:e000e280 NVIC_ICPR0
+ G431_addr.s:714 *ABS*:e000e284 NVIC_ICPR1
+ G431_addr.s:715 *ABS*:e000e288 NVIC_ICPR2
+ G431_addr.s:716 *ABS*:e000e28c NVIC_ICPR3
+ G431_addr.s:718 *ABS*:e000e300 NVIC_IABR0
+ G431_addr.s:719 *ABS*:e000e304 NVIC_IABR1
+ G431_addr.s:720 *ABS*:e000e308 NVIC_IABR2
+ G431_addr.s:721 *ABS*:e000e30c NVIC_IABR3
+ G431_addr.s:723 *ABS*:e000e400 NVIC_IPR0
+ G431_addr.s:724 *ABS*:e000e404 NVIC_IPR1
+ G431_addr.s:725 *ABS*:e000e408 NVIC_IPR2
+ G431_addr.s:726 *ABS*:e000e40c NVIC_IPR3
+ G431_addr.s:727 *ABS*:e000e410 NVIC_IPR4
+ G431_addr.s:728 *ABS*:e000e414 NVIC_IPR5
+ G431_addr.s:729 *ABS*:e000e418 NVIC_IPR6
+ G431_addr.s:730 *ABS*:e000e41c NVIC_IPR7
+ G431_addr.s:731 *ABS*:e000e420 NVIC_IPR8
+ G431_addr.s:732 *ABS*:e000e424 NVIC_IPR9
+ G431_addr.s:733 *ABS*:e000e428 NVIC_IPR10
+ G431_addr.s:734 *ABS*:e000e42c NVIC_IPR11
+ G431_addr.s:735 *ABS*:e000e430 NVIC_IPR12
+ G431_addr.s:736 *ABS*:e000e434 NVIC_IPR13
+ G431_addr.s:737 *ABS*:e000e438 NVIC_IPR14
+ G431_addr.s:738 *ABS*:e000e43c NVIC_IPR15
+ G431_addr.s:739 *ABS*:e000e440 NVIC_IPR16
+ G431_addr.s:740 *ABS*:e000e444 NVIC_IPR17
+ G431_addr.s:741 *ABS*:e000e448 NVIC_IPR18
+ G431_addr.s:742 *ABS*:e000e44c NVIC_IPR19
+ G431_addr.s:743 *ABS*:e000e450 NVIC_IPR20
+ G431_addr.s:744 *ABS*:e000e454 NVIC_IPR21
+ G431_addr.s:745 *ABS*:e000e458 NVIC_IPR22
+ G431_addr.s:746 *ABS*:e000e45c NVIC_IPR23
+ G431_addr.s:747 *ABS*:e000e460 NVIC_IPR24
+ G431_addr.s:748 *ABS*:e000e464 NVIC_IPR25
+ G431_addr.s:750 *ABS*:e000ef00 STIR
+ G431_addr.s:758 *ABS*:e0042000 DBGMCU_BASE
+ G431_addr.s:760 *ABS*:e0042000 DBGMCU_IDCODE
+ G431_addr.s:761 *ABS*:e0042004 DBGMCU_CR
+ G431_addr.s:762 *ABS*:e0042008 DBGMCU_APB1FZR1
+ G431_addr.s:763 *ABS*:e004200c DBGMCU_APB1FZR2
+ G431_addr.s:764 *ABS*:e0042010 DBGMCU_APB2DZR
+ task2.s:48 .vectortable:00000000 $d
+ task2.s:215 .exhand:00000000 _ISR_NMI
+ task2.s:248 .exhand:00000028 _ISR_HARDF
+ task2.s:281 .exhand:00000050 _ISR_S0
+ task2.s:69 .text:00000000 $t
+ task2.s:75 .text:00000000 init
+ task2.s:160 .text:00000044 main
+ task2.s:182 .text:00000054 delay
+ task2.s:196 .text:00000060 stop
+ task2.s:202 .text:00000066 .lp1
+ task2.s:203 .text:00000066 $d
+ task2.s:203 .text:00000068 $d
+ task2.s:211 .exhand:00000000 $t
+ task2.s:301 .exhand:00000058 _ISR_S1
+ task2.s:319 .exhand:0000005e .lp2
+ task2.s:320 .exhand:0000005e $d
+ task2.s:320 .exhand:00000060 $d
+
+NO UNDEFINED SYMBOLS
diff --git a/task2/task2.elf b/task2/task2.elf
new file mode 100755
index 0000000..a008f0b
Binary files /dev/null and b/task2/task2.elf differ
diff --git a/task2/task2.launch b/task2/task2.launch
index 114d818..0fdc2be 100644
--- a/task2/task2.launch
+++ b/task2/task2.launch
@@ -37,7 +37,7 @@
-
+
diff --git a/task2/task2.lst b/task2/task2.lst
new file mode 100644
index 0000000..e83ec7d
--- /dev/null
+++ b/task2/task2.lst
@@ -0,0 +1,156 @@
+
+task2.elf: file format elf32-littlearm
+
+Sections:
+Idx Name Size VMA LMA File off Algn
+ 0 .vectortable 00000014 08000000 08000000 00001000 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 1 .text 00000074 08000400 08000400 00001400 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 2 .exhand 00000068 08001000 08001000 00002000 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, CODE
+SYMBOL TABLE:
+08000000 l d .vectortable 00000000 .vectortable
+08000400 l d .text 00000000 .text
+08001000 l d .exhand 00000000 .exhand
+08001000 l F .exhand 00000000 _ISR_NMI
+08001028 l F .exhand 00000000 _ISR_HARDF
+08001050 l F .exhand 00000000 _ISR_S0
+08000466 l .text 00000000 .lp1
+08001058 l F .exhand 00000000 _ISR_S1
+0800105e l .exhand 00000000 .lp2
+08000400 g F .text 00000000 init
+08000444 g F .text 00000000 main
+08000454 g F .text 00000000 delay
+08000460 g .text 00000000 stop
+
+
+
+Disassembly of section .vectortable:
+
+08000000 <.vectortable>:
+ 8000000: 20004000 .word 0x20004000
+ 8000004: 08000401 .word 0x08000401
+ 8000008: 08001001 .word 0x08001001
+ 800000c: 08001029 .word 0x08001029
+ 8000010: 08001051 .word 0x08001051
+
+Disassembly of section .text:
+
+08000400 :
+ 8000400: b672 cpsid i
+ 8000402: 2000 movs r0, #0
+ 8000404: 2100 movs r1, #0
+ 8000406: 2200 movs r2, #0
+ 8000408: 2300 movs r3, #0
+ 800040a: 2400 movs r4, #0
+ 800040c: 2500 movs r5, #0
+ 800040e: 2600 movs r6, #0
+ 8000410: 2700 movs r7, #0
+ 8000412: 4680 mov r8, r0
+ 8000414: 4681 mov r9, r0
+ 8000416: 4682 mov sl, r0
+ 8000418: 4683 mov fp, r0
+ 800041a: 4684 mov ip, r0
+ 800041c: 4912 ldr r1, [pc, #72] @ (8000468 <.lp1+0x2>)
+ 800041e: f04f 0201 mov.w r2, #1
+ 8000422: 6808 ldr r0, [r1, #0]
+ 8000424: 4310 orrs r0, r2
+ 8000426: 6008 str r0, [r1, #0]
+ 8000428: f04f 4190 mov.w r1, #1207959552 @ 0x48000000
+ 800042c: 2203 movs r2, #3
+ 800042e: 6808 ldr r0, [r1, #0]
+ 8000430: 4390 bics r0, r2
+ 8000432: 2201 movs r2, #1
+ 8000434: 4310 orrs r0, r2
+ 8000436: 6008 str r0, [r1, #0]
+ 8000438: 490c ldr r1, [pc, #48] @ (800046c <.lp1+0x6>)
+ 800043a: 2201 movs r2, #1
+ 800043c: 6808 ldr r0, [r1, #0]
+ 800043e: 4310 orrs r0, r2
+ 8000440: 6008 str r0, [r1, #0]
+ 8000442: b662 cpsie i
+
+08000444 :
+ 8000444: 4909 ldr r1, [pc, #36] @ (800046c <.lp1+0x6>)
+ 8000446: 4050 eors r0, r2
+ 8000448: 6008 str r0, [r1, #0]
+ 800044a: f000 f803 bl 8000454
+ 800044e: f7ff bff9 b.w 8000444
+ 8000452: bf00 nop
+
+08000454 :
+ 8000454: 2600 movs r6, #0
+ 8000456: 4f06 ldr r7, [pc, #24] @ (8000470 <.lp1+0xa>)
+ 8000458: 3601 adds r6, #1
+ 800045a: 42be cmp r6, r7
+ 800045c: d1fc bne.n 8000458
+ 800045e: 4770 bx lr
+
+08000460 :
+ 8000460: bf00 nop
+ 8000462: f7ff bffd b.w 8000460
+
+08000466 <.lp1>:
+ 8000466: 0000 .short 0x0000
+ 8000468: 4002104c .word 0x4002104c
+ 800046c: 48000014 .word 0x48000014
+ 8000470: 001e8480 .word 0x001e8480
+
+Disassembly of section .exhand:
+
+08001000 <_ISR_NMI>:
+ 8001000: 4917 ldr r1, [pc, #92] @ (8001060 <.lp2+0x2>)
+ 8001002: f04f 0201 mov.w r2, #1
+ 8001006: 6808 ldr r0, [r1, #0]
+ 8001008: 4310 orrs r0, r2
+ 800100a: 6008 str r0, [r1, #0]
+ 800100c: f04f 4190 mov.w r1, #1207959552 @ 0x48000000
+ 8001010: 22ff movs r2, #255 @ 0xff
+ 8001012: 6808 ldr r0, [r1, #0]
+ 8001014: 4390 bics r0, r2
+ 8001016: 2244 movs r2, #68 @ 0x44
+ 8001018: 4310 orrs r0, r2
+ 800101a: 6008 str r0, [r1, #0]
+ 800101c: 4911 ldr r1, [pc, #68] @ (8001064 <.lp2+0x6>)
+ 800101e: 220a movs r2, #10
+ 8001020: 6808 ldr r0, [r1, #0]
+ 8001022: 4390 bics r0, r2
+ 8001024: 6008 str r0, [r1, #0]
+ 8001026: e7eb b.n 8001000 <_ISR_NMI>
+
+08001028 <_ISR_HARDF>:
+ 8001028: 490d ldr r1, [pc, #52] @ (8001060 <.lp2+0x2>)
+ 800102a: f04f 0201 mov.w r2, #1
+ 800102e: 6808 ldr r0, [r1, #0]
+ 8001030: 4310 orrs r0, r2
+ 8001032: 6008 str r0, [r1, #0]
+ 8001034: f04f 4190 mov.w r1, #1207959552 @ 0x48000000
+ 8001038: 22ff movs r2, #255 @ 0xff
+ 800103a: 6808 ldr r0, [r1, #0]
+ 800103c: 4390 bics r0, r2
+ 800103e: 2211 movs r2, #17
+ 8001040: 4310 orrs r0, r2
+ 8001042: 6008 str r0, [r1, #0]
+ 8001044: 4907 ldr r1, [pc, #28] @ (8001064 <.lp2+0x6>)
+ 8001046: 2205 movs r2, #5
+ 8001048: 6808 ldr r0, [r1, #0]
+ 800104a: 4390 bics r0, r2
+ 800104c: 6008 str r0, [r1, #0]
+ 800104e: e7eb b.n 8001028 <_ISR_HARDF>
+
+08001050 <_ISR_S0>:
+ 8001050: b500 push {lr}
+ 8001052: bc02 pop {r1}
+ 8001054: 4708 bx r1
+ 8001056: bf00 nop
+
+08001058 <_ISR_S1>:
+ 8001058: b500 push {lr}
+ 800105a: bc02 pop {r1}
+ 800105c: 4708 bx r1
+
+0800105e <.lp2>:
+ 800105e: 0000 .short 0x0000
+ 8001060: 4002104c .word 0x4002104c
+ 8001064: 48000014 .word 0x48000014
diff --git a/task2/task2.map b/task2/task2.map
new file mode 100644
index 0000000..0f272fa
--- /dev/null
+++ b/task2/task2.map
@@ -0,0 +1,92 @@
+
+Memory Configuration
+
+Name Origin Length Attributes
+IVECS 0x08000000 0x000001d8 r
+PGM 0x08000400 0x00000c00 xr
+EXHANDS 0x08001000 0x00000400 xr
+RAM 0x20000000 0x00001800 rw
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+
+.vectortable 0x08000000 0x14
+ 0x08000000 . = ALIGN (0x4)
+ *(.vectortable)
+ .vectortable 0x08000000 0x14 task2.o
+ 0x08000014 . = ALIGN (0x4)
+
+.text 0x08000400 0x74
+ *(.text)
+ .text 0x08000400 0x74 task2.o
+ 0x08000400 init
+ 0x08000444 main
+ 0x08000454 delay
+ 0x08000460 stop
+
+.glue_7 0x08000474 0x0
+ .glue_7 0x08000474 0x0 linker stubs
+
+.glue_7t 0x08000474 0x0
+ .glue_7t 0x08000474 0x0 linker stubs
+
+.vfp11_veneer 0x08000474 0x0
+ .vfp11_veneer 0x08000474 0x0 linker stubs
+
+.v4_bx 0x08000474 0x0
+ .v4_bx 0x08000474 0x0 linker stubs
+
+.iplt 0x08000474 0x0
+ .iplt 0x08000474 0x0 task2.o
+
+.exhand 0x08001000 0x68
+ *(.exhand)
+ .exhand 0x08001000 0x68 task2.o
+LOAD task2.o
+OUTPUT(task2.elf elf32-littlearm)
+LOAD linker stubs
+
+.rel.dyn 0x08001068 0x0
+ .rel.iplt 0x08001068 0x0 task2.o
+
+.data 0x08001068 0x0
+ .data 0x08001068 0x0 task2.o
+
+.igot.plt 0x08001068 0x0
+ .igot.plt 0x08001068 0x0 task2.o
+
+.bss 0x08001068 0x0
+ .bss 0x08001068 0x0 task2.o
+
+.ARM.attributes
+ 0x00000000 0x21
+ .ARM.attributes
+ 0x00000000 0x21 task2.o
+
+.debug_line 0x00000000 0xc1
+ .debug_line 0x00000000 0xc1 task2.o
+
+.debug_info 0x00000000 0x22
+ .debug_info 0x00000000 0x22 task2.o
+
+.debug_abbrev 0x00000000 0x12
+ .debug_abbrev 0x00000000 0x12 task2.o
+
+.debug_aranges 0x00000000 0x28
+ .debug_aranges
+ 0x00000000 0x28 task2.o
+
+.debug_str 0x00000000 0x68
+ .debug_str 0x00000000 0x68 task2.o
+
+.debug_ranges 0x00000000 0x20
+ .debug_ranges 0x00000000 0x20 task2.o
+
+Cross Reference Table
+
+Symbol File
+delay task2.o
+init task2.o
+main task2.o
+stop task2.o
diff --git a/task2/task2.o b/task2/task2.o
new file mode 100644
index 0000000..e2ae9de
Binary files /dev/null and b/task2/task2.o differ
diff --git a/task2/task2.s b/task2/task2.s
index fa2ba02..66920da 100644
--- a/task2/task2.s
+++ b/task2/task2.s
@@ -1,45 +1,32 @@
#****************************************************************************************#
# Project: task2 - ASM: Interrupts
# File: task2.s
-#
-# Language: ASM
-#
# Hardware: STefi Light v1.1
# Processor: STM32G431KBT6U
-#
-# Author: Manuel Lederhofer
-# Datum: 31.10.2014
-#
-# Version: 6.0
-# History:
-# 31.10.2014 ML create file
-# 27.09.2018 ML edit comments, extend vector table
-# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
-# 27.02.2019 ML move section of exception handlers to bottom of file
-# 25.09.2019 ML minor changes for a better code and comment understanding
-# 04.09.2020 HL port from STM32L476RG to STM32F411xE
-# 21.09.2020 ML tidy up, comments and formatting
-# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
-# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
-# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
-# 24.06.2025 TK remove /* ... place your code here ... */
-#
-# Status: working
-#
-# Description:
-# See the description and requirements of the requested application
-# in the lab exercise guide.
-#
-# Notes:
-# - MCU speed at startup is 16 MHz
-#
-# ToDo:
-# - Change the example code to match the description and requirements
-# of the requested application in the lab exercise guide.
#****************************************************************************************#
.include "G431_addr.s"
+ // Zusätzliche und benötigte Adressen
+ .equ RCC_AHB2ENR, 0x4002104C
+ .equ RCC_APB2ENR, 0x40021060
+
+ .equ GPIOA_MODER, 0x48000000
+ .equ GPIOA_ODR, 0x48000014
+
+ .equ GPIOC_MODER, 0x48000800
+ .equ GPIOC_PUPDR, 0x4800080C
+ .equ GPIOC_IDR, 0x48000810
+
+ .equ SYSCFG_BASE, 0x40010000
+ .equ SYSCFG_EXTICR4, (SYSCFG_BASE + 0x14)
+
+ .equ EXTI_BASE, 0x40010400
+ .equ EXTI_IMR1, (EXTI_BASE + 0x00)
+ .equ EXTI_FTSR1, (EXTI_BASE + 0x0C)
+ .equ EXTI_PR1, (EXTI_BASE + 0x14)
+
+ .equ NVIC_ISER1, 0xE000E104
#----------------------------------------------------------------------------------------#
.section .vectortable,"a" // vector table at begin of ROM
@@ -47,20 +34,13 @@
.align 2
- .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x20004000 // initial Stack Pointer
.word 0x08000401 // initial Program Counter
.word _ISR_NMI // non-masking interrupt
.word _ISR_HARDF // hard fault interrupt
-
-
- /* N.B.
- Look at the .space or the .org assembler directive to insert the address of the
- ISRs at the right place in the vector table. Verify your settings by the help of
- the list file. */
-
- .word _ISR_S0
-
+ .space 0xD0 // padding 208 Bytes bis Offset 0xE0 (EXTI15_10 IRQ 40)
+ .word _ISR_S0_S1 // gemeinsamer Interrupt für PC13 (S0) und PC14 (S1)
#----------------------------------------------------------------------------------------#
.text // section .text (default section for program code)
@@ -90,57 +70,85 @@ init:
MOV r12, r0
#--- enable port clocking
- LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
- MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
- LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
- ORRS r0, r0, r2 // configure clock gating for ports
- STR r0, [r1, #0] // apply settings
+ LDR r1, =RCC_AHB2ENR
+ MOVS r2, #0x05 // Bit 0 (GPIOA) und Bit 2 (GPIOC)
+ LDR r0, [r1, #0]
+ ORRS r0, r2
+ STR r0, [r1, #0]
#--- port init
-#- LEDs
- LDR r1, =GPIOA_MODER // load port A mode register address
- MOVS r2, #0x03 // prepare mask
- LDR r0, [r1, #0] // get current value of port A mode register
- BICS r0, r2 // delete bits
- MOVS r2, #0x01 // load configuration mask
- ORRS r0, r0, r2 // apply mask
- STR r0, [r1, #0] // apply result to port A mode register
+#- LEDs (PA0-PA3)
+ LDR r1, =GPIOA_MODER
+ LDR r2, =0x000000FF // Maske PA0-PA3
+ LDR r0, [r1, #0]
+ BICS r0, r2
+ LDR r2, =0x00000055 // Maske Output 0101 0101
+ ORRS r0, r2
+ STR r0, [r1, #0]
#- switch LED off
- LDR r1, =GPIOA_ODR // load port A output data register
- MOVS r2, #0x01 // load mask for LED
- LDR r0, [r1, #0] // get current value of GPIOA
- ORRS r0, r0, r2 // configure pin state
- STR r0, [r1, #0] // apply settings
+ LDR r1, =GPIOA_ODR
+ MOVS r2, #0x0F // Maske LED0-3
+ LDR r0, [r1, #0]
+ ORRS r0, r2
+ STR r0, [r1, #0]
-#- buttons
-
- /* ... place your code here ... */
+#- buttons (PC13, PC14 als Input)
+ LDR r1, =GPIOC_MODER
+ LDR r2, =0x3C000000 // Maske Bits 26-29
+ LDR r0, [r1, #0]
+ BICS r0, r2
+ STR r0, [r1, #0]
+#- Pull-Up für PC13, PC14
+ LDR r1, =GPIOC_PUPDR
+ LDR r2, =0x3C000000
+ LDR r0, [r1, #0]
+ BICS r0, r2
+ LDR r2, =0x14000000 // 01 = Pull-Up für PC13 (Bits 27:26) und PC14 (Bits 29:28)
+ ORRS r0, r2
+ STR r0, [r1, #0]
#--- button interrupt config
#- enable clock for SYSCFG module
-
+ LDR r1, =RCC_APB2ENR
+ MOVS r2, #0x01
+ LDR r0, [r1, #0]
+ ORRS r0, r2
+ STR r0, [r1, #0]
#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
-# in SYSCFG module (SYSCFG_* registers)
-
-
-
+ LDR r1, =SYSCFG_EXTICR4
+ LDR r2, =0x00000FF0 // Maske für EXTI13 (Bits 7:4) und EXTI14 (Bits 11:8)
+ LDR r0, [r1, #0]
+ BICS r0, r2
+ LDR r2, =0x00000220 // Port C (0010) für EXTI13 und EXTI14
+ ORRS r0, r2
+ STR r0, [r1, #0]
#- configure lines in EXTI module (EXTI_* registers)
+ LDR r1, =EXTI_FTSR1 // Fallende Flanke
+ LDR r2, =0x00006000 // Bits 13 und 14
+ LDR r0, [r1, #0]
+ ORRS r0, r2
+ STR r0, [r1, #0]
-
+ LDR r1, =EXTI_IMR1 // Maskierung aufheben
+ LDR r2, =0x00006000
+ LDR r0, [r1, #0]
+ ORRS r0, r2
+ STR r0, [r1, #0]
#- NVIC: set interrupt priority, clear pending bits
-# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
-
-
+ LDR r1, =NVIC_ISER1
+ LDR r2, =0x00000100 // Bit 8 für IRQ 40 (EXTI15_10)
+ LDR r0, [r1, #0]
+ ORRS r0, r2
+ STR r0, [r1, #0]
CPSIE i // enable interrupts globally
-
#----------------------------------------------------------------------------------------#
.align 2
@@ -150,16 +158,9 @@ init:
.global main
.type main, %function
main:
- LDR r1, =GPIOA_ODR
- EORS r0, r0, r2
- STR r0, [r1, #0]
-
- BL delay
-
-
+ WFI
B main
-
#----------------------------------------------------------------------------------------#
.align 2
@@ -169,30 +170,25 @@ main:
.global delay
.type delay, %function
delay:
- MOVS r6, #0 // ...
- LDR r7, =2000000 // ...
+ LDR r0, =106000 // Entprell-Zeit ~20ms
.L1:
- ADDS r6, r6, #1 // ...
- CMP r6, r7 // ...
- BNE .L1 // ...
- BX lr // ...
-
+ SUBS r0, r0, #1
+ BNE .L1
+ BX lr
#----------------------------------------------------------------------------------------#
.align 2
.global stop
stop:
- NOP // do nothing (NOP is here to avoid a debugger crash, only)
- B stop // if this line is reached, something went wrong
-
+ NOP
+ B stop
#----------------------------------------------------------------------------------------#
-.lp1: // this label is only to nicify the line up in the .lst file
+.lp1:
.ltorg
#----------------------------------------------------------------------------------------#
-
#----------------------------------------------------------------------------------------#
.section .exhand,"ax" // section for exception handlers
#----------------------------------------------------------------------------------------#
@@ -202,32 +198,28 @@ stop:
.thumb
.type _ISR_NMI, %function
_ISR_NMI:
-#--- enable clock
- LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
- MOV r2, #0x01 // load mask
- LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
- ORRS r0, r0, r2 // configure clock gating for port
- STR r0, [r1, #0] // apply settings
-
-#--- init pins
- LDR r1, =GPIOA_MODER // load port A mode register address
- MOVS r2, #0xFF // prepare mask
- LDR r0, [r1, #0] // get current value of port A mode register
- BICS r0, r0, r2 // delete bits
- MOVS r2, #0x44 // load configuration mask
- ORRS r0, r0, r2 // configure pins
- STR r0, [r1, #0] // apply settings to port A mode register
-
-#--- switch some LEDs on
- LDR r1, =GPIOA_ODR // load port A data output register address
- MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r1, =RCC_AHB2ENR
+ MOV r2, #0x01
LDR r0, [r1, #0]
- BICS r0, r0, r2
- STR r0, [r1, #0] // switch LEDs on
+ ORRS r0, r2
+ STR r0, [r1, #0]
+
+ LDR r1, =GPIOA_MODER
+ MOVS r2, #0xFF
+ LDR r0, [r1, #0]
+ BICS r0, r2
+ MOVS r2, #0x44
+ ORRS r0, r2
+ STR r0, [r1, #0]
+
+ LDR r1, =GPIOA_ODR
+ MOVS r2, #0x0A
+ LDR r0, [r1, #0]
+ BICS r0, r2
+ STR r0, [r1, #0]
B _ISR_NMI
-
#----------------------------------------------------------------------------------------#
.align 2
@@ -235,77 +227,99 @@ _ISR_NMI:
.thumb
.type _ISR_HARDF, %function
_ISR_HARDF:
-#--- enable clock
- LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
- MOV r2, #0x01 // load mask
- LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
- ORRS r0, r0, r2 // configure clock gating for port
- STR r0, [r1, #0] // apply settings
-
-#--- init pins
- LDR r1, =GPIOA_MODER // load port A mode register address
- MOVS r2, #0xFF // prepare mask
- LDR r0, [r1, #0] // get current value of port A mode register
- BICS r0, r0, r2 // delete bits
- MOVS r2, #0x11 // load configuration mask
- ORRS r0, r0, r2 // configure pins
- STR r0, [r1, #0] // apply settings to port A mode register
-
-#--- switch some LEDs on
- LDR r1, =GPIOA_ODR // load port A data output register address
- MOVS r2, #0x05 // load mask for red and green LED
+ LDR r1, =RCC_AHB2ENR
+ MOV r2, #0x01
LDR r0, [r1, #0]
- BICS r0, r0, r2
- STR r0, [r1, #0] // switch LEDs on
+ ORRS r0, r2
+ STR r0, [r1, #0]
+
+ LDR r1, =GPIOA_MODER
+ MOVS r2, #0xFF
+ LDR r0, [r1, #0]
+ BICS r0, r2
+ MOVS r2, #0x11
+ ORRS r0, r2
+ STR r0, [r1, #0]
+
+ LDR r1, =GPIOA_ODR
+ MOVS r2, #0x05
+ LDR r0, [r1, #0]
+ BICS r0, r2
+ STR r0, [r1, #0]
B _ISR_HARDF
-
#----------------------------------------------------------------------------------------#
.align 2
.syntax unified
.thumb
- .type _ISR_S0, %function
-_ISR_S0:
- PUSH {lr} // save special content
+ .type _ISR_S0_S1, %function
+_ISR_S0_S1:
+ PUSH {r4, r5, lr} // Wichtig: Register sichern gemäß AAPCS
-#--- do the work
+_check_S0:
+ LDR r4, =EXTI_PR1
+ LDR r5, [r4, #0]
+ LDR r2, =0x2000 // Maske für S0 (PC13 / Bit 13)
+ TST r5, r2
+ BEQ _check_S1 // Wenn Bit 13 nicht gesetzt, überspringen
+#--- do the work S0
+ BL delay // Entprellen
-#--- clear interrupt flag
+ LDR r0, =GPIOC_IDR
+ LDR r1, [r0, #0]
+ LDR r2, =0x2000
+ TST r1, r2
+ BNE _clear_S0 // Abbruch, wenn High (Taster prellt / schon losgelassen)
+ LDR r0, =GPIOA_ODR
+ LDR r1, [r0, #0]
+ MOVS r2, #0x09 // LED0 & LED3 toggeln (1001)
+ EORS r1, r2
+ STR r1, [r0, #0]
+_clear_S0:
+#--- clear interrupt flag S0
+ LDR r4, =EXTI_PR1
+ LDR r5, =0x2000
+ STR r5, [r4, #0]
+
+_check_S1:
+ LDR r4, =EXTI_PR1
+ LDR r5, [r4, #0]
+ LDR r2, =0x4000 // Maske für S1 (PC14 / Bit 14)
+ TST r5, r2
+ BEQ _leave_ISR // Wenn Bit 14 nicht gesetzt, Ende
+
+#--- do the work S1
+ BL delay
+
+ LDR r0, =GPIOC_IDR
+ LDR r1, [r0, #0]
+ LDR r2, =0x4000
+ TST r1, r2
+ BNE _clear_S1 // Abbruch, wenn High
+
+ LDR r0, =GPIOA_ODR
+ LDR r1, [r0, #0]
+ MOVS r2, #0x06 // LED1 & LED2 toggeln (0110)
+ EORS r1, r2
+ STR r1, [r0, #0]
+
+_clear_S1:
+#--- clear interrupt flag S1
+ LDR r4, =EXTI_PR1
+ LDR r5, =0x4000
+ STR r5, [r4, #0]
+
+_leave_ISR:
#--- leave ISR
- POP {r1} // get special content back
- BX r1 // go back to where we came from
-
+ POP {r4, r5, pc} // Register wiederherstellen und zurückkehren
#----------------------------------------------------------------------------------------#
-
- .align 2
- .syntax unified
- .thumb
- .type _ISR_S1, %function
-_ISR_S1:
- PUSH {lr} // save special content
-
-#--- do the work
-
-
-
-
-#--- clear interrupt flag
-
-
-
-#--- leave ISR
- POP {r1} // get special content back
- BX r1 // go back to where we came from
-
-
-#----------------------------------------------------------------------------------------#
-.lp2: // this label is only to nicify the line up in the .lst file
+.lp2:
.ltorg
#----------------------------------------------------------------------------------------#
diff --git a/task2/task2_tobi.s b/task2/task2_tobi.s
new file mode 100644
index 0000000..52617cb
--- /dev/null
+++ b/task2/task2_tobi.s
@@ -0,0 +1,325 @@
+#****************************************************************************************#
+# Project: task2 - ASM: Interrupts
+# File: task2.s
+#
+# Language: ASM
+#
+# Hardware: STefi Light v1.1
+# Processor: STM32G431KBT6U
+#
+# Author: Manuel Lederhofer
+# Datum: 31.10.2014
+#
+# Version: 6.0
+# History:
+# 31.10.2014 ML create file
+# 27.09.2018 ML edit comments, extend vector table
+# 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
+# 27.02.2019 ML move section of exception handlers to bottom of file
+# 25.09.2019 ML minor changes for a better code and comment understanding
+# 04.09.2020 HL port from STM32L476RG to STM32F411xE
+# 21.09.2020 ML tidy up, comments and formatting
+# 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
+# 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
+# 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
+# 24.06.2025 TK remove /* ... place your code here ... */
+#
+# Status: working
+#
+# Description:
+# See the description and requirements of the requested application
+# in the lab exercise guide.
+#
+# Notes:
+# - MCU speed at startup is 16 MHz
+#
+# ToDo:
+# - Change the example code to match the description and requirements
+# of the requested application in the lab exercise guide.
+#****************************************************************************************#
+
+ .include "G431_addr.s"
+
+
+#----------------------------------------------------------------------------------------#
+ .section .vectortable,"a" // vector table at begin of ROM
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+
+ .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRAM1 length)
+ .word 0x08000401 // initial Program Counter
+ .word _ISR_NMI // non-masking interrupt
+ .word _ISR_HARDF // hard fault interrupt
+
+
+
+ /* N.B.
+ Look at the .space or the .org assembler directive to insert the address of the
+ ISRs at the right place in the vector table. Verify your settings by the help of
+ the list file. */
+
+ .word _ISR_S0
+
+
+#----------------------------------------------------------------------------------------#
+ .text // section .text (default section for program code)
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global init
+ .type init, %function
+init:
+ CPSID i // disable interrupts globally
+
+ MOVS r0, #0 // safely initialize the GPRs
+ MOVS r1, #0
+ MOVS r2, #0
+ MOVS r3, #0
+ MOVS r4, #0
+ MOVS r5, #0
+ MOVS r6, #0
+ MOVS r7, #0
+ MOV r8, r0
+ MOV r9, r0
+ MOV r10, r0
+ MOV r11, r0
+ MOV r12, r0
+
+#--- enable port clocking
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for ports
+ STR r0, [r1, #0] // apply settings
+
+#--- port init
+#- LEDs
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0x03 // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r2 // delete bits
+ MOVS r2, #0x01 // load configuration mask
+ ORRS r0, r0, r2 // apply mask
+ STR r0, [r1, #0] // apply result to port A mode register
+
+# LDR r1, =GPIOB_MODER
+# MOVS r3, #0x03
+# LDR r0, [r1, #1]
+# BICS r0, r3
+# MOVS r3, #0x01
+# ORRS r0, r0, r3
+# STR r0, [r1, #1]
+
+#- switch LED off
+ LDR r1, =GPIOA_ODR // load port A output data register
+ MOVS r2, #0x01 // load mask for LED
+ LDR r0, [r1, #0] // get current value of GPIOA
+ ORRS r0, r0, r2 // configure pin state
+ STR r0, [r1, #0] // apply settings
+
+#- buttons
+
+ /* ... place your code here ... */
+
+
+#--- button interrupt config
+
+#- enable clock for SYSCFG module
+
+
+#- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
+# in SYSCFG module (SYSCFG_* registers)
+
+
+
+
+#- configure lines in EXTI module (EXTI_* registers)
+
+
+
+#- NVIC: set interrupt priority, clear pending bits
+# and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
+
+
+
+ CPSIE i // enable interrupts globally
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global main
+ .type main, %function
+main:
+ LDR r1, =GPIOA_ODR
+ EORS r0, r0, r2
+
+ STR r0, [r1, #0]
+
+
+
+ BL delay
+
+
+ B main
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .thumb_func
+ .global delay
+ .type delay, %function
+delay:
+ MOVS r6, #0 // ...
+ LDR r7, =2000000 // ...
+.L1:
+ ADDS r6, r6, #1 // ...
+ CMP r6, r7 // ...
+ BNE .L1 // ...
+ BX lr // ...
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .global stop
+stop:
+ NOP // do nothing (NOP is here to avoid a debugger crash, only)
+ B stop // if this line is reached, something went wrong
+
+
+#----------------------------------------------------------------------------------------#
+.lp1: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+
+#----------------------------------------------------------------------------------------#
+ .section .exhand,"ax" // section for exception handlers
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_NMI, %function
+_ISR_NMI:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x44 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x0A // load mask for blue and yellow LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_NMI
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_HARDF, %function
+_ISR_HARDF:
+#--- enable clock
+ LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
+ MOV r2, #0x01 // load mask
+ LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
+ ORRS r0, r0, r2 // configure clock gating for port
+ STR r0, [r1, #0] // apply settings
+
+#--- init pins
+ LDR r1, =GPIOA_MODER // load port A mode register address
+ MOVS r2, #0xFF // prepare mask
+ LDR r0, [r1, #0] // get current value of port A mode register
+ BICS r0, r0, r2 // delete bits
+ MOVS r2, #0x11 // load configuration mask
+ ORRS r0, r0, r2 // configure pins
+ STR r0, [r1, #0] // apply settings to port A mode register
+
+#--- switch some LEDs on
+ LDR r1, =GPIOA_ODR // load port A data output register address
+ MOVS r2, #0x05 // load mask for red and green LED
+ LDR r0, [r1, #0]
+ BICS r0, r0, r2
+ STR r0, [r1, #0] // switch LEDs on
+
+ B _ISR_HARDF
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S0, %function
+_ISR_S0:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+#--- clear interrupt flag
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+
+ .align 2
+ .syntax unified
+ .thumb
+ .type _ISR_S1, %function
+_ISR_S1:
+ PUSH {lr} // save special content
+
+#--- do the work
+
+
+
+
+#--- clear interrupt flag
+
+
+
+#--- leave ISR
+ POP {r1} // get special content back
+ BX r1 // go back to where we came from
+
+
+#----------------------------------------------------------------------------------------#
+.lp2: // this label is only to nicify the line up in the .lst file
+ .ltorg
+#----------------------------------------------------------------------------------------#
+
+ .end
+
+#************************************** E O F *******************************************#