1621 lines
93 KiB
Alloy
1621 lines
93 KiB
Alloy
GNU assembler version 2.40.0 (arm-none-eabi)
|
|
using BFD version (GNU Tools for STM32 12.3.rel1.20240612-1315) 2.40.0.20230627.
|
|
options passed : -march=armv7-m -mcpu=cortex-m4 -adglns -g -mthumb --warn
|
|
input file : task2.s
|
|
output file : task2.o
|
|
target : arm-none-eabi
|
|
time stamp : 2026-03-24T14:14:11.000+0100
|
|
|
|
1 #****************************************************************************************#
|
|
2 # Project: task2 - ASM: Interrupts
|
|
3 # File: task2.s
|
|
4 #
|
|
5 # Language: ASM
|
|
6 #
|
|
7 # Hardware: STefi Light v1.1
|
|
8 # Processor: STM32G431KBT6U
|
|
9 #
|
|
10 # Author: Manuel Lederhofer
|
|
11 # Datum: 31.10.2014
|
|
12 #
|
|
13 # Version: 6.0
|
|
14 # History:
|
|
15 # 31.10.2014 ML create file
|
|
16 # 27.09.2018 ML edit comments, extend vector table
|
|
17 # 18.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
|
|
18 # 27.02.2019 ML move section of exception handlers to bottom of file
|
|
19 # 25.09.2019 ML minor changes for a better code and comment understanding
|
|
20 # 04.09.2020 HL port from STM32L476RG to STM32F411xE
|
|
21 # 21.09.2020 ML tidy up, comments and formatting
|
|
22 # 29.09.2021 ML port from STM32F411xE to STM32F042K6T6
|
|
23 # 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
|
|
24 # 10.02.2025 TK remove ASM:Polling,move ASM:Interrupts to task2
|
|
25 # 24.06.2025 TK remove /* ... place your code here ... */
|
|
26 #
|
|
27 # Status: working
|
|
28 #
|
|
29 # Description:
|
|
30 # See the description and requirements of the requested application
|
|
31 # in the lab exercise guide.
|
|
32 #
|
|
33 # Notes:
|
|
34 # - MCU speed at startup is 16 MHz
|
|
35 #
|
|
36 # ToDo:
|
|
37 # - Change the example code to match the description and requirements
|
|
38 # of the requested application in the lab exercise guide.
|
|
39 #****************************************************************************************#
|
|
40
|
|
41 .include "G431_addr.s"
|
|
1 #*****************************************************************************************
|
|
2 # Project: task2 - switch triggered LEDs
|
|
3 # File: G431_addr.s
|
|
4 #
|
|
5 # Language: ASM
|
|
6 #
|
|
7 # Hardware: STefi v1.1
|
|
8 # Processor: STM32G431KBT6U
|
|
9 #
|
|
10 # Author: Manuel Lederhofer
|
|
11 # Datum: 20.08.2015
|
|
12 #
|
|
13 # Version: 3.0
|
|
14 # History:
|
|
15 # 20.08.2015 ML create file
|
|
16 # 07.12.2018 ML port from MKL05Z32VLC4 to STM32L476RG
|
|
17 # 27.02.2019 ML change from absolute addresses to BASE + OFFSET notation and
|
|
18 # add more timer modules
|
|
19 # 09.03.2022 ML port from STM32F042K6T6 to STM32G431KBT6U
|
|
20 #
|
|
21 # Status: working
|
|
22 #
|
|
23 # Description:
|
|
24 # Connects assembly addresses for STM32G431 MCU to symbolic register names
|
|
25 # used in the datasheets.
|
|
26 #
|
|
27 # Notes:
|
|
28 # - default MCU speed at startup is 16 MHz.
|
|
29 #
|
|
30 # ToDo:
|
|
31 # - none -
|
|
32 #*****************************************************************************************
|
|
33
|
|
34
|
|
35 #----------------------------------------------------------------------------------------#
|
|
36 # MCU Bus Base Addresses
|
|
37 #----------------------------------------------------------------------------------------#
|
|
38
|
|
39 .equ APB1_BASE, 0x40000000
|
|
40 .equ APB2_BASE, 0x40010000
|
|
41 .equ AHB1_BASE, 0x40020000
|
|
42 .equ AHB2_BASE, 0x48000000
|
|
43 .equ AHB3_BASE, 0xA0000000 //!!! FSMC + QSPI registers = AHB3 ?
|
|
44 .equ PPB_BASE, 0xE0000000 /* Cortex M4 with FPU Internal Peripherals */
|
|
45
|
|
46 #----------------------------------------------------------------------------------------#
|
|
47 # System Configuration Controller
|
|
48 #
|
|
49 # address space: 0x4001_0000 .. 0x4001_0029
|
|
50 #----------------------------------------------------------------------------------------#
|
|
51
|
|
52 .equ SYSCFG_BASE, APB2_BASE
|
|
53
|
|
54 .equ SYSCFG_MEMRMP, SYSCFG_BASE + 0x00
|
|
55 .equ SYSCFG_CFGR1, SYSCFG_BASE + 0x04
|
|
56 .equ SYSCFG_EXTICR1, SYSCFG_BASE + 0x08
|
|
57 .equ SYSCFG_EXTICR2, SYSCFG_BASE + 0x0C
|
|
58 .equ SYSCFG_EXTICR3, SYSCFG_BASE + 0x10
|
|
59 .equ SYSCFG_EXTICR4, SYSCFG_BASE + 0x14
|
|
60 .equ SYSCFG_SCSR, SYSCFG_BASE + 0x18
|
|
61 .equ SYSCFG_CFGR2, SYSCFG_BASE + 0x1C
|
|
62 .equ SYSCFG_SWPR, SYSCFG_BASE + 0x20
|
|
63 .equ SYSCFG_SKR, SYSCFG_BASE + 0x24
|
|
64
|
|
65 #----------------------------------------------------------------------------------------#
|
|
66 # Extended Interrupts And Events Controller
|
|
67 #
|
|
68 # address space: 0x4001_0400 .. 0x4001_07FF
|
|
69 #----------------------------------------------------------------------------------------#
|
|
70
|
|
71 .equ EXTI_BASE, APB2_BASE + 0x400
|
|
72
|
|
73 .equ EXTI_IMR1, EXTI_BASE + 0x00
|
|
74 .equ EXTI_EMR1, EXTI_BASE + 0x04
|
|
75 .equ EXTI_RTSR1, EXTI_BASE + 0x08
|
|
76 .equ EXTI_FTSR1, EXTI_BASE + 0x0C
|
|
77 .equ EXTI_SWIER1, EXTI_BASE + 0x10
|
|
78 .equ EXTI_PR1, EXTI_BASE + 0x14
|
|
79
|
|
80 .equ EXTI_IMR2, EXTI_BASE + 0x20
|
|
81 .equ EXTI_EMR2, EXTI_BASE + 0x24
|
|
82 .equ EXTI_RTSR2, EXTI_BASE + 0x28
|
|
83 .equ EXTI_FTSR2, EXTI_BASE + 0x2C
|
|
84 .equ EXTI_SWIER2, EXTI_BASE + 0x30
|
|
85 .equ EXTI_PR2, EXTI_BASE + 0x34
|
|
86
|
|
87 #----------------------------------------------------------------------------------------#
|
|
88 # TIM module common configuration
|
|
89 #
|
|
90 # Every timer has 1 KB address space:
|
|
91 #
|
|
92 # TIM2 .. TIM7: 0x4000_0000 .. 0x4000_17FF (APB1)
|
|
93 # TIM1: 0x4001_2C00 .. 0x4001_2FFF (APB2)
|
|
94 # TIM8: 0x4001_3400 .. 0x4001_37FF (APB2)
|
|
95 # TIM15 .. TIM17: 0x4001_4000 .. 0x4001_4BFF (APB2)
|
|
96 # TIM20: 0x4001_5000 .. 0x4001_53FF (APB2)
|
|
97 #
|
|
98 # note:
|
|
99 # TIM2 + TIM5 are 32 bit timers. All others have a width of 16 bit.
|
|
100 # Below, the timers on one line share a common register set description.
|
|
101 #
|
|
102 # TIM 1, 8, 20 advances control timers
|
|
103 # TIM 2, 3, 4, 5 general purpose timers (TIM2/5 = 32 bit)
|
|
104 # TIM 15 general purpose timers
|
|
105 # TIM 16, 17 general purpose timers
|
|
106 # TIM 6, 7 basic timers
|
|
107 #----------------------------------------------------------------------------------------#
|
|
108
|
|
109 .equ TIM_CR1_OFFSET, 0x00
|
|
110 .equ TIM_CR2_OFFSET, 0x04
|
|
111 .equ TIM_SMCR_OFFSET, 0x08
|
|
112 .equ TIM_DIER_OFFSET, 0x0C
|
|
113 .equ TIM_SR_OFFSET, 0x10
|
|
114 .equ TIM_EGR_OFFSET, 0x14
|
|
115 .equ TIM_CCMR1_OFFSET, 0x18
|
|
116 .equ TIM_CCMR2_OFFSET, 0x1C
|
|
117 .equ TIM_CCER_OFFSET, 0x20
|
|
118 .equ TIM_CNT_OFFSET, 0x24
|
|
119 .equ TIM_PSC_OFFSET, 0x28
|
|
120 .equ TIM_ARR_OFFSET, 0x2C
|
|
121 .equ TIM_RCR_OFFSET, 0x30
|
|
122 .equ TIM_CCR1_OFFSET, 0x34
|
|
123 .equ TIM_CCR2_OFFSET, 0x38
|
|
124 .equ TIM_CCR3_OFFSET, 0x3C
|
|
125 .equ TIM_CCR4_OFFSET, 0x40
|
|
126 .equ TIM_BDTR_OFFSET, 0x44
|
|
127 .equ TIM_CCR5_OFFSET, 0x48
|
|
128 .equ TIM_CCR6_OFFSET, 0x4C
|
|
129 .equ TIM_CCMR3_OFFSET, 0x50
|
|
130 .equ TIM_DTR2_OFFSET, 0x54
|
|
131 .equ TIM_ECR_OFFSET, 0x58
|
|
132 .equ TIM_TISEL_OFFSET, 0x5C
|
|
133 .equ TIM_AF1_OFFSET, 0x60
|
|
134 .equ TIM_AF2_OFFSET, 0x64
|
|
135 .equ TIM_OR1_OFFSET, 0x68
|
|
136
|
|
137 .equ TIM_DCR_OFFSET, 0x3DC
|
|
138 .equ TIM_DMAR_OFFSET, 0x3E0
|
|
139
|
|
140 #- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
|
|
141
|
|
142 #--- Genral Purpose Timer - TIM2 / address space: 0x4000_0000 .. 0x4000_03FF
|
|
143
|
|
144 .equ TIM2_BASE, APB1_BASE
|
|
145
|
|
146 .equ TIM2_CR1, TIM2_BASE + TIM_CR1_OFFSET
|
|
147 .equ TIM2_CR2, TIM2_BASE + TIM_CR2_OFFSET
|
|
148 .equ TIM2_SMCR, TIM2_BASE + TIM_SMCR_OFFSET
|
|
149 .equ TIM2_DIER, TIM2_BASE + TIM_DIER_OFFSET
|
|
150 .equ TIM2_SR, TIM2_BASE + TIM_SR_OFFSET
|
|
151 .equ TIM2_EGR, TIM2_BASE + TIM_EGR_OFFSET
|
|
152 .equ TIM2_CCMR1, TIM2_BASE + TIM_CCMR1_OFFSET
|
|
153 .equ TIM2_CCMR2, TIM2_BASE + TIM_CCMR2_OFFSET
|
|
154 .equ TIM2_CCER, TIM2_BASE + TIM_CCER_OFFSET
|
|
155 .equ TIM2_CNT, TIM2_BASE + TIM_CNT_OFFSET
|
|
156 .equ TIM2_PSC, TIM2_BASE + TIM_PSC_OFFSET
|
|
157 .equ TIM2_ARR, TIM2_BASE + TIM_ARR_OFFSET
|
|
158
|
|
159 .equ TIM2_CCR1, TIM2_BASE + TIM_CCR1_OFFSET
|
|
160 .equ TIM2_CCR2, TIM2_BASE + TIM_CCR2_OFFSET
|
|
161 .equ TIM2_CCR3, TIM2_BASE + TIM_CCR3_OFFSET
|
|
162 .equ TIM2_CCR4, TIM2_BASE + TIM_CCR4_OFFSET
|
|
163
|
|
164 .equ TIM2_ECR, TIM2_BASE + TIM_ECR_OFFSET
|
|
165 .equ TIM2_TISEL, TIM2_BASE + TIM_TISEL_OFFSET
|
|
166 .equ TIM2_AF1, TIM2_BASE + TIM_ECR_OFFSET
|
|
167 .equ TIM2_AF2, TIM2_BASE + TIM_ECR_OFFSET
|
|
168
|
|
169 .equ TIM2_DCR, TIM2_BASE + TIM_DCR_OFFSET
|
|
170 .equ TIM2_DMAR, TIM2_BASE + TIM_DMAR_OFFSET
|
|
171
|
|
172 #--- Genral Purpose Timer - TIM3 / address space: 0x4000_0400 .. 0x4000_07FF
|
|
173
|
|
174 .equ TIM3_BASE, APB1_BASE + 0x400
|
|
175
|
|
176 .equ TIM3_CR1, TIM3_BASE + TIM_CR1_OFFSET
|
|
177 .equ TIM3_CR2, TIM3_BASE + TIM_CR2_OFFSET
|
|
178 .equ TIM3_SMCR, TIM3_BASE + TIM_SMCR_OFFSET
|
|
179 .equ TIM3_DIER, TIM3_BASE + TIM_DIER_OFFSET
|
|
180 .equ TIM3_SR, TIM3_BASE + TIM_SR_OFFSET
|
|
181 .equ TIM3_EGR, TIM3_BASE + TIM_EGR_OFFSET
|
|
182 .equ TIM3_CCMR1, TIM3_BASE + TIM_CCMR1_OFFSET
|
|
183 .equ TIM3_CCMR2, TIM3_BASE + TIM_CCMR2_OFFSET
|
|
184 .equ TIM3_CCER, TIM3_BASE + TIM_CCER_OFFSET
|
|
185 .equ TIM3_CNT, TIM3_BASE + TIM_CNT_OFFSET
|
|
186 .equ TIM3_PSC, TIM3_BASE + TIM_PSC_OFFSET
|
|
187 .equ TIM3_ARR, TIM3_BASE + TIM_ARR_OFFSET
|
|
188
|
|
189 .equ TIM3_CCR1, TIM3_BASE + TIM_CCR1_OFFSET
|
|
190 .equ TIM3_CCR2, TIM3_BASE + TIM_CCR2_OFFSET
|
|
191 .equ TIM3_CCR3, TIM3_BASE + TIM_CCR3_OFFSET
|
|
192 .equ TIM3_CCR4, TIM3_BASE + TIM_CCR4_OFFSET
|
|
193
|
|
194 .equ TIM3_ECR, TIM3_BASE + TIM_ECR_OFFSET
|
|
195 .equ TIM3_TISEL, TIM3_BASE + TIM_TISEL_OFFSET
|
|
196 .equ TIM3_AF1, TIM3_BASE + TIM_ECR_OFFSET
|
|
197 .equ TIM3_AF2, TIM3_BASE + TIM_ECR_OFFSET
|
|
198
|
|
199 .equ TIM3_DCR, TIM3_BASE + TIM_DCR_OFFSET
|
|
200 .equ TIM3_DMAR, TIM3_BASE + TIM_DMAR_OFFSET
|
|
201
|
|
202 #--- Genral Purpose Timer - TIM4 / address space: 0x4000_0800 .. 0x4000_0BFF
|
|
203
|
|
204 .equ TIM4_BASE, APB1_BASE + 0x800
|
|
205
|
|
206 .equ TIM4_CR1, TIM4_BASE + TIM_CR1_OFFSET
|
|
207 .equ TIM4_CR2, TIM4_BASE + TIM_CR2_OFFSET
|
|
208 .equ TIM4_SMCR, TIM4_BASE + TIM_SMCR_OFFSET
|
|
209 .equ TIM4_DIER, TIM4_BASE + TIM_DIER_OFFSET
|
|
210 .equ TIM4_SR, TIM4_BASE + TIM_SR_OFFSET
|
|
211 .equ TIM4_EGR, TIM4_BASE + TIM_EGR_OFFSET
|
|
212 .equ TIM4_CCMR1, TIM4_BASE + TIM_CCMR1_OFFSET
|
|
213 .equ TIM4_CCMR2, TIM4_BASE + TIM_CCMR2_OFFSET
|
|
214 .equ TIM4_CCER, TIM4_BASE + TIM_CCER_OFFSET
|
|
215 .equ TIM4_CNT, TIM4_BASE + TIM_CNT_OFFSET
|
|
216 .equ TIM4_PSC, TIM4_BASE + TIM_PSC_OFFSET
|
|
217 .equ TIM4_ARR, TIM4_BASE + TIM_ARR_OFFSET
|
|
218
|
|
219 .equ TIM4_CCR1, TIM4_BASE + TIM_CCR1_OFFSET
|
|
220 .equ TIM4_CCR2, TIM4_BASE + TIM_CCR2_OFFSET
|
|
221 .equ TIM4_CCR3, TIM4_BASE + TIM_CCR3_OFFSET
|
|
222 .equ TIM4_CCR4, TIM4_BASE + TIM_CCR4_OFFSET
|
|
223
|
|
224 .equ TIM4_ECR, TIM4_BASE + TIM_ECR_OFFSET
|
|
225 .equ TIM4_TISEL, TIM4_BASE + TIM_TISEL_OFFSET
|
|
226 .equ TIM4_AF1, TIM4_BASE + TIM_ECR_OFFSET
|
|
227 .equ TIM4_AF2, TIM4_BASE + TIM_ECR_OFFSET
|
|
228
|
|
229 .equ TIM4_DCR, TIM4_BASE + TIM_DCR_OFFSET
|
|
230 .equ TIM4_DMAR, TIM4_BASE + TIM_DMAR_OFFSET
|
|
231
|
|
232 #--- Genral Purpose Timer - TIM5 / address space: 0x4000_0C00 .. 0x4000_0FFF
|
|
233
|
|
234 .equ TIM5_BASE, APB1_BASE + 0xC00
|
|
235
|
|
236 .equ TIM5_CR1, TIM5_BASE + TIM_CR1_OFFSET
|
|
237 .equ TIM5_CR2, TIM5_BASE + TIM_CR2_OFFSET
|
|
238 .equ TIM5_SMCR, TIM5_BASE + TIM_SMCR_OFFSET
|
|
239 .equ TIM5_DIER, TIM5_BASE + TIM_DIER_OFFSET
|
|
240 .equ TIM5_SR, TIM5_BASE + TIM_SR_OFFSET
|
|
241 .equ TIM5_EGR, TIM5_BASE + TIM_EGR_OFFSET
|
|
242 .equ TIM5_CCMR1, TIM5_BASE + TIM_CCMR1_OFFSET
|
|
243 .equ TIM5_CCMR2, TIM5_BASE + TIM_CCMR2_OFFSET
|
|
244 .equ TIM5_CCER, TIM5_BASE + TIM_CCER_OFFSET
|
|
245 .equ TIM5_CNT, TIM5_BASE + TIM_CNT_OFFSET
|
|
246 .equ TIM5_PSC, TIM5_BASE + TIM_PSC_OFFSET
|
|
247 .equ TIM5_ARR, TIM5_BASE + TIM_ARR_OFFSET
|
|
248
|
|
249 .equ TIM5_CCR1, TIM5_BASE + TIM_CCR1_OFFSET
|
|
250 .equ TIM5_CCR2, TIM5_BASE + TIM_CCR2_OFFSET
|
|
251 .equ TIM5_CCR3, TIM5_BASE + TIM_CCR3_OFFSET
|
|
252 .equ TIM5_CCR4, TIM5_BASE + TIM_CCR4_OFFSET
|
|
253
|
|
254 .equ TIM5_ECR, TIM5_BASE + TIM_ECR_OFFSET
|
|
255 .equ TIM5_TISEL, TIM5_BASE + TIM_TISEL_OFFSET
|
|
256 .equ TIM5_AF1, TIM5_BASE + TIM_ECR_OFFSET
|
|
257 .equ TIM5_AF2, TIM5_BASE + TIM_ECR_OFFSET
|
|
258
|
|
259 .equ TIM5_DCR, TIM5_BASE + TIM_DCR_OFFSET
|
|
260 .equ TIM5_DMAR, TIM5_BASE + TIM_DMAR_OFFSET
|
|
261
|
|
262 #--- Basic Timer - TIM6 / address space: 0x4000_1000 .. 0x4000_13FF
|
|
263
|
|
264 .equ TIM6_BASE, APB1_BASE + 0x1000
|
|
265
|
|
266 .equ TIM6_CR1, TIM6_BASE + TIM_CR1_OFFSET
|
|
267 .equ TIM6_CR2, TIM6_BASE + TIM_CR2_OFFSET
|
|
268
|
|
269 .equ TIM6_DIER, TIM6_BASE + TIM_DIER_OFFSET
|
|
270 .equ TIM6_SR, TIM6_BASE + TIM_SR_OFFSET
|
|
271 .equ TIM6_EGR, TIM6_BASE + TIM_EGR_OFFSET
|
|
272
|
|
273 .equ TIM6_CNT, TIM6_BASE + TIM_CNT_OFFSET
|
|
274 .equ TIM6_PSC, TIM6_BASE + TIM_PSC_OFFSET
|
|
275 .equ TIM6_ARR, TIM6_BASE + TIM_ARR_OFFSET
|
|
276
|
|
277 #--- Basic Timer - TIM7 / address space: 0x4000_1400 .. 0x4000_17FF
|
|
278
|
|
279 .equ TIM7_BASE, APB1_BASE + 0x1400
|
|
280
|
|
281 .equ TIM7_CR1, TIM7_BASE + TIM_CR1_OFFSET
|
|
282 .equ TIM7_CR2, TIM7_BASE + TIM_CR2_OFFSET
|
|
283
|
|
284 .equ TIM7_DIER, TIM7_BASE + TIM_DIER_OFFSET
|
|
285 .equ TIM7_SR, TIM7_BASE + TIM_SR_OFFSET
|
|
286 .equ TIM7_EGR, TIM7_BASE + TIM_EGR_OFFSET
|
|
287
|
|
288 .equ TIM7_CNT, TIM7_BASE + TIM_CNT_OFFSET
|
|
289 .equ TIM7_PSC, TIM7_BASE + TIM_PSC_OFFSET
|
|
290 .equ TIM7_ARR, TIM7_BASE + TIM_ARR_OFFSET
|
|
291
|
|
292 #--- Advanced Control Timer - TIM1 / address space: 0x4001_2C00 .. 0x4001_2FFF
|
|
293
|
|
294 .equ TIM1_BASE, APB2_BASE + 0x2C00
|
|
295
|
|
296 .equ TIM1_CR1, TIM1_BASE + TIM_CR1_OFFSET
|
|
297 .equ TIM1_CR2, TIM1_BASE + TIM_CR2_OFFSET
|
|
298 .equ TIM1_SMCR, TIM1_BASE + TIM_SMCR_OFFSET
|
|
299 .equ TIM1_DIER, TIM1_BASE + TIM_DIER_OFFSET
|
|
300 .equ TIM1_SR, TIM1_BASE + TIM_SR_OFFSET
|
|
301 .equ TIM1_EGR, TIM1_BASE + TIM_EGR_OFFSET
|
|
302 .equ TIM1_CCMR1, TIM1_BASE + TIM_CCMR1_OFFSET
|
|
303 .equ TIM1_CCMR2, TIM1_BASE + TIM_CCMR2_OFFSET
|
|
304 .equ TIM1_CCER, TIM1_BASE + TIM_CCER_OFFSET
|
|
305 .equ TIM1_CNT, TIM1_BASE + TIM_CNT_OFFSET
|
|
306 .equ TIM1_PSC, TIM1_BASE + TIM_PSC_OFFSET
|
|
307 .equ TIM1_ARR, TIM1_BASE + TIM_ARR_OFFSET
|
|
308 .equ TIM1_RCR, TIM1_BASE + TIM_RCR_OFFSET
|
|
309 .equ TIM1_CCR1, TIM1_BASE + TIM_CCR1_OFFSET
|
|
310 .equ TIM1_CCR2, TIM1_BASE + TIM_CCR2_OFFSET
|
|
311 .equ TIM1_CCR3, TIM1_BASE + TIM_CCR3_OFFSET
|
|
312 .equ TIM1_CCR4, TIM1_BASE + TIM_CCR4_OFFSET
|
|
313 .equ TIM1_BDTR, TIM1_BASE + TIM_BDTR_OFFSET
|
|
314 .equ TIM1_CCR5, TIM1_BASE + TIM_CCR5_OFFSET
|
|
315 .equ TIM1_CCR6, TIM1_BASE + TIM_CCR6_OFFSET
|
|
316 .equ TIM1_CCMR3, TIM1_BASE + TIM_CCMR3_OFFSET
|
|
317 .equ TIM1_DTR2, TIM1_BASE + TIM_DTR2_OFFSET
|
|
318 .equ TIM1_ECR, TIM1_BASE + TIM_ECR_OFFSET
|
|
319 .equ TIM1_TISEL, TIM1_BASE + TIM_TISEL_OFFSET
|
|
320 .equ TIM1_AF1, TIM1_BASE + TIM_AF1_OFFSET
|
|
321 .equ TIM1_AF2, TIM1_BASE + TIM_AF2_OFFSET
|
|
322
|
|
323 .equ TIM1_DCR, TIM1_BASE + TIM_DCR_OFFSET
|
|
324 .equ TIM1_DMAR, TIM1_BASE + TIM_DMAR_OFFSET
|
|
325
|
|
326 #--- Advanced Control Timer - TIM8 / address space: 0x4001_3400 .. 0x4001_37FF
|
|
327
|
|
328 .equ TIM8_BASE, APB2_BASE + 0x3400
|
|
329
|
|
330 .equ TIM8_CR1, TIM8_BASE + TIM_CR1_OFFSET
|
|
331 .equ TIM8_CR2, TIM8_BASE + TIM_CR2_OFFSET
|
|
332 .equ TIM8_SMCR, TIM8_BASE + TIM_SMCR_OFFSET
|
|
333 .equ TIM8_DIER, TIM8_BASE + TIM_DIER_OFFSET
|
|
334 .equ TIM8_SR, TIM8_BASE + TIM_SR_OFFSET
|
|
335 .equ TIM8_EGR, TIM8_BASE + TIM_EGR_OFFSET
|
|
336 .equ TIM8_CCMR1, TIM8_BASE + TIM_CCMR1_OFFSET
|
|
337 .equ TIM8_CCMR2, TIM8_BASE + TIM_CCMR2_OFFSET
|
|
338 .equ TIM8_CCER, TIM8_BASE + TIM_CCER_OFFSET
|
|
339 .equ TIM8_CNT, TIM8_BASE + TIM_CNT_OFFSET
|
|
340 .equ TIM8_PSC, TIM8_BASE + TIM_PSC_OFFSET
|
|
341 .equ TIM8_ARR, TIM8_BASE + TIM_ARR_OFFSET
|
|
342 .equ TIM8_RCR, TIM8_BASE + TIM_RCR_OFFSET
|
|
343 .equ TIM8_CCR1, TIM8_BASE + TIM_CCR1_OFFSET
|
|
344 .equ TIM8_CCR2, TIM8_BASE + TIM_CCR2_OFFSET
|
|
345 .equ TIM8_CCR3, TIM8_BASE + TIM_CCR3_OFFSET
|
|
346 .equ TIM8_CCR4, TIM8_BASE + TIM_CCR4_OFFSET
|
|
347 .equ TIM8_BDTR, TIM8_BASE + TIM_BDTR_OFFSET
|
|
348 .equ TIM8_CCR5, TIM8_BASE + TIM_CCR5_OFFSET
|
|
349 .equ TIM8_CCR6, TIM8_BASE + TIM_CCR6_OFFSET
|
|
350 .equ TIM8_CCMR3, TIM8_BASE + TIM_CCMR3_OFFSET
|
|
351 .equ TIM8_DTR2, TIM8_BASE + TIM_DTR2_OFFSET
|
|
352 .equ TIM8_ECR, TIM8_BASE + TIM_ECR_OFFSET
|
|
353 .equ TIM8_TISEL, TIM8_BASE + TIM_TISEL_OFFSET
|
|
354 .equ TIM8_AF1, TIM8_BASE + TIM_AF1_OFFSET
|
|
355 .equ TIM8_AF2, TIM8_BASE + TIM_AF2_OFFSET
|
|
356
|
|
357 .equ TIM8_DCR, TIM8_BASE + TIM_DCR_OFFSET
|
|
358 .equ TIM8_DMAR, TIM8_BASE + TIM_DMAR_OFFSET
|
|
359
|
|
360 #--- Advanced Control Timer - TIM20 / address space: 0x4001_5000 .. 0x4001_53FF
|
|
361
|
|
362 .equ TIM20_BASE, APB2_BASE + 0x5000
|
|
363
|
|
364 .equ TIM20_CR1, TIM20_BASE + TIM_CR1_OFFSET
|
|
365 .equ TIM20_CR2, TIM20_BASE + TIM_CR2_OFFSET
|
|
366 .equ TIM20_SMCR, TIM20_BASE + TIM_SMCR_OFFSET
|
|
367 .equ TIM20_DIER, TIM20_BASE + TIM_DIER_OFFSET
|
|
368 .equ TIM20_SR, TIM20_BASE + TIM_SR_OFFSET
|
|
369 .equ TIM20_EGR, TIM20_BASE + TIM_EGR_OFFSET
|
|
370 .equ TIM20_CCMR1, TIM20_BASE + TIM_CCMR1_OFFSET
|
|
371 .equ TIM20_CCMR2, TIM20_BASE + TIM_CCMR2_OFFSET
|
|
372 .equ TIM20_CCER, TIM20_BASE + TIM_CCER_OFFSET
|
|
373 .equ TIM20_CNT, TIM20_BASE + TIM_CNT_OFFSET
|
|
374 .equ TIM20_PSC, TIM20_BASE + TIM_PSC_OFFSET
|
|
375 .equ TIM20_ARR, TIM20_BASE + TIM_ARR_OFFSET
|
|
376 .equ TIM20_RCR, TIM20_BASE + TIM_RCR_OFFSET
|
|
377 .equ TIM20_CCR1, TIM20_BASE + TIM_CCR1_OFFSET
|
|
378 .equ TIM20_CCR2, TIM20_BASE + TIM_CCR2_OFFSET
|
|
379 .equ TIM20_CCR3, TIM20_BASE + TIM_CCR3_OFFSET
|
|
380 .equ TIM20_CCR4, TIM20_BASE + TIM_CCR4_OFFSET
|
|
381 .equ TIM20_BDTR, TIM20_BASE + TIM_BDTR_OFFSET
|
|
382 .equ TIM20_CCR5, TIM20_BASE + TIM_CCR5_OFFSET
|
|
383 .equ TIM20_CCR6, TIM20_BASE + TIM_CCR6_OFFSET
|
|
384 .equ TIM20_CCMR3, TIM20_BASE + TIM_CCMR3_OFFSET
|
|
385 .equ TIM20_DTR2, TIM20_BASE + TIM_DTR2_OFFSET
|
|
386 .equ TIM20_ECR, TIM20_BASE + TIM_ECR_OFFSET
|
|
387 .equ TIM20_TISEL, TIM20_BASE + TIM_TISEL_OFFSET
|
|
388 .equ TIM20_AF1, TIM20_BASE + TIM_AF1_OFFSET
|
|
389 .equ TIM20_AF2, TIM20_BASE + TIM_AF2_OFFSET
|
|
390
|
|
391 .equ TIM20_DCR, TIM20_BASE + TIM_DCR_OFFSET
|
|
392 .equ TIM20_DMAR, TIM20_BASE + TIM_DMAR_OFFSET
|
|
393
|
|
394 #--- Genral Purpose Timer - TIM15 / address space: 0x4001_4000 .. 0x4001_43FF
|
|
395
|
|
396 .equ TIM15_BASE, APB2_BASE + 0x4000
|
|
397
|
|
398 .equ TIM15_CR1, TIM15_BASE + TIM_CR1_OFFSET
|
|
399 .equ TIM15_CR2, TIM15_BASE + TIM_CR2_OFFSET
|
|
400 .equ TIM15_SMCR, TIM15_BASE + TIM_SMCR_OFFSET
|
|
401 .equ TIM15_DIER, TIM15_BASE + TIM_DIER_OFFSET
|
|
402 .equ TIM15_SR, TIM15_BASE + TIM_SR_OFFSET
|
|
403 .equ TIM15_EGR, TIM15_BASE + TIM_EGR_OFFSET
|
|
404 .equ TIM15_CCMR1, TIM15_BASE + TIM_CCMR1_OFFSET
|
|
405
|
|
406 .equ TIM15_CCER, TIM15_BASE + TIM_CCER_OFFSET
|
|
407 .equ TIM15_CNT, TIM15_BASE + TIM_CNT_OFFSET
|
|
408 .equ TIM15_PSC, TIM15_BASE + TIM_PSC_OFFSET
|
|
409 .equ TIM15_ARR, TIM15_BASE + TIM_ARR_OFFSET
|
|
410 .equ TIM15_RCR, TIM15_BASE + TIM_RCR_OFFSET
|
|
411 .equ TIM15_CCR1, TIM15_BASE + TIM_CCR1_OFFSET
|
|
412 .equ TIM15_CCR2, TIM15_BASE + TIM_CCR2_OFFSET
|
|
413
|
|
414 .equ TIM15_BDTR, TIM15_BASE + TIM_BDTR_OFFSET
|
|
415
|
|
416 .equ TIM15_DTR2, TIM15_BASE + TIM_DTR2_OFFSET
|
|
417
|
|
418 .equ TIM15_TISEL, TIM15_BASE + TIM_TISEL_OFFSET
|
|
419 .equ TIM15_AF1, TIM15_BASE + TIM_AF1_OFFSET
|
|
420 .equ TIM15_AF2, TIM15_BASE + TIM_AF2_OFFSET
|
|
421
|
|
422 .equ TIM15_DCR, TIM15_BASE + TIM_DCR_OFFSET
|
|
423 .equ TIM15_DMAR, TIM15_BASE + TIM_DMAR_OFFSET
|
|
424
|
|
425 #--- Genral Purpose Timer - TIM16 / address space: 0x4001_4400 .. 0x4001_47FF
|
|
426
|
|
427 .equ TIM16_BASE, APB2_BASE + 0x4400
|
|
428
|
|
429 .equ TIM16_CR1, TIM16_BASE + TIM_CR1_OFFSET
|
|
430 .equ TIM16_CR2, TIM16_BASE + TIM_CR2_OFFSET
|
|
431
|
|
432 .equ TIM16_DIER, TIM16_BASE + TIM_DIER_OFFSET
|
|
433 .equ TIM16_SR, TIM16_BASE + TIM_SR_OFFSET
|
|
434 .equ TIM16_EGR, TIM16_BASE + TIM_EGR_OFFSET
|
|
435 .equ TIM16_CCMR1, TIM16_BASE + TIM_CCMR1_OFFSET
|
|
436
|
|
437 .equ TIM16_CCER, TIM16_BASE + TIM_CCER_OFFSET
|
|
438 .equ TIM16_CNT, TIM16_BASE + TIM_CNT_OFFSET
|
|
439 .equ TIM16_PSC, TIM16_BASE + TIM_PSC_OFFSET
|
|
440 .equ TIM16_ARR, TIM16_BASE + TIM_ARR_OFFSET
|
|
441 .equ TIM16_RCR, TIM16_BASE + TIM_RCR_OFFSET
|
|
442 .equ TIM16_CCR1, TIM16_BASE + TIM_CCR1_OFFSET
|
|
443
|
|
444 .equ TIM16_BDTR, TIM16_BASE + TIM_BDTR_OFFSET
|
|
445
|
|
446 .equ TIM16_DTR2, TIM16_BASE + TIM_DTR2_OFFSET
|
|
447
|
|
448 .equ TIM16_TISEL, TIM16_BASE + TIM_TISEL_OFFSET
|
|
449 .equ TIM16_AF1, TIM16_BASE + TIM_AF1_OFFSET
|
|
450 .equ TIM16_AF2, TIM16_BASE + TIM_AF2_OFFSET
|
|
451 .equ TIM16_OR1, TIM16_BASE + TIM_OR1_OFFSET
|
|
452
|
|
453 .equ TIM16_DCR, TIM16_BASE + TIM_DCR_OFFSET
|
|
454 .equ TIM16_DMAR, TIM16_BASE + TIM_DMAR_OFFSET
|
|
455
|
|
456 #--- Genral Purpose Timer - TIM17 / address space: 0x4001_4800 .. 0x4001_4BFF
|
|
457
|
|
458 .equ TIM17_BASE, APB2_BASE + 0x4800
|
|
459
|
|
460 .equ TIM17_CR1, TIM17_BASE + TIM_CR1_OFFSET
|
|
461 .equ TIM17_CR2, TIM17_BASE + TIM_CR2_OFFSET
|
|
462
|
|
463 .equ TIM17_DIER, TIM17_BASE + TIM_DIER_OFFSET
|
|
464 .equ TIM17_SR, TIM17_BASE + TIM_SR_OFFSET
|
|
465 .equ TIM17_EGR, TIM17_BASE + TIM_EGR_OFFSET
|
|
466 .equ TIM17_CCMR1, TIM17_BASE + TIM_CCMR1_OFFSET
|
|
467
|
|
468 .equ TIM17_CCER, TIM17_BASE + TIM_CCER_OFFSET
|
|
469 .equ TIM17_CNT, TIM17_BASE + TIM_CNT_OFFSET
|
|
470 .equ TIM17_PSC, TIM17_BASE + TIM_PSC_OFFSET
|
|
471 .equ TIM17_ARR, TIM17_BASE + TIM_ARR_OFFSET
|
|
472 .equ TIM17_RCR, TIM17_BASE + TIM_RCR_OFFSET
|
|
473 .equ TIM17_CCR1, TIM17_BASE + TIM_CCR1_OFFSET
|
|
474
|
|
475 .equ TIM17_BDTR, TIM17_BASE + TIM_BDTR_OFFSET
|
|
476
|
|
477 .equ TIM17_DTR2, TIM17_BASE + TIM_DTR2_OFFSET
|
|
478
|
|
479 .equ TIM17_TISEL, TIM17_BASE + TIM_TISEL_OFFSET
|
|
480 .equ TIM17_AF1, TIM17_BASE + TIM_AF1_OFFSET
|
|
481 .equ TIM17_AF2, TIM17_BASE + TIM_AF2_OFFSET
|
|
482 .equ TIM17_OR1, TIM17_BASE + TIM_OR1_OFFSET
|
|
483
|
|
484 .equ TIM17_DCR, TIM17_BASE + TIM_DCR_OFFSET
|
|
485 .equ TIM17_DMAR, TIM17_BASE + TIM_DMAR_OFFSET
|
|
486
|
|
487 #----------------------------------------------------------------------------------------#
|
|
488 # Reset and Clock Control
|
|
489 #
|
|
490 # address space: 0x4002_1000 .. 0x4002_13FF
|
|
491 #----------------------------------------------------------------------------------------#
|
|
492
|
|
493 .equ RCC_BASE, AHB1_BASE + 0x1000
|
|
494
|
|
495 .equ RCC_CR, RCC_BASE + 0x00
|
|
496 .equ RCC_ICSCR, RCC_BASE + 0x04
|
|
497 .equ RCC_CFGR, RCC_BASE + 0x08
|
|
498 .equ RCC_PLLCFGR, RCC_BASE + 0x0C
|
|
499
|
|
500 .equ RCC_CIER, RCC_BASE + 0x18
|
|
501 .equ RCC_CIFR, RCC_BASE + 0x1C
|
|
502 .equ RCC_CICR, RCC_BASE + 0x20
|
|
503
|
|
504 .equ RCC_AHB1RSTR, RCC_BASE + 0x28
|
|
505 .equ RCC_AHB2RSTR, RCC_BASE + 0x2C
|
|
506 .equ RCC_AHB3RSTR, RCC_BASE + 0x30
|
|
507
|
|
508 .equ RCC_APB1RSTR1, RCC_BASE + 0x38
|
|
509 .equ RCC_APB1RSTR2, RCC_BASE + 0x3C
|
|
510 .equ RCC_APB2RSTR, RCC_BASE + 0x40
|
|
511
|
|
512 .equ RCC_AHB1ENR, RCC_BASE + 0x48
|
|
513 .equ RCC_AHB2ENR, RCC_BASE + 0x4C
|
|
514 .equ RCC_AHB3ENR, RCC_BASE + 0x50
|
|
515
|
|
516 .equ RCC_APB1ENR1, RCC_BASE + 0x58
|
|
517 .equ RCC_APB1ENR2, RCC_BASE + 0x5C
|
|
518 .equ RCC_APB2ENR, RCC_BASE + 0x60
|
|
519
|
|
520 .equ RCC_AHB1SMENR, RCC_BASE + 0x68
|
|
521 .equ RCC_AHB2SMENR, RCC_BASE + 0x6C
|
|
522 .equ RCC_AHB3SMENR, RCC_BASE + 0x70
|
|
523
|
|
524 .equ RCC_APB1SMENR1, RCC_BASE + 0x78
|
|
525 .equ RCC_APB1SMENR2, RCC_BASE + 0x7C
|
|
526 .equ RCC_APB2SMENR, RCC_BASE + 0x80
|
|
527
|
|
528 .equ RCC_CCIPR, RCC_BASE + 0x88
|
|
529
|
|
530 .equ RCC_BDCR, RCC_BASE + 0x90
|
|
531 .equ RCC_CSR, RCC_BASE + 0x94
|
|
532 .equ RCC_CRRCR, RCC_BASE + 0x98
|
|
533 .equ RCC_CCIPR2, RCC_BASE + 0x9C
|
|
534
|
|
535 #----------------------------------------------------------------------------------------#
|
|
536 # GPIO module common configuration
|
|
537 #
|
|
538 # address space: 0x4800_0000 .. 0x4800_1FFF
|
|
539 #----------------------------------------------------------------------------------------#
|
|
540
|
|
541 .equ GPIO_BASE, AHB2_BASE
|
|
542
|
|
543 .equ GPIO_MODER_OFFSET, 0x00
|
|
544 .equ GPIO_OTYPER_OFFSET, 0x04
|
|
545 .equ GPIO_OSPEEDR_OFFSET, 0x08
|
|
546 .equ GPIO_PUPDR_OFFSET, 0x0C
|
|
547 .equ GPIO_IDR_OFFSET, 0x10
|
|
548 .equ GPIO_ODR_OFFSET, 0x14
|
|
549 .equ GPIO_BSRR_OFFSET, 0x18
|
|
550 .equ GPIO_LCKR_OFFSET, 0x1C
|
|
551 .equ GPIO_AFRL_OFFSET, 0x20
|
|
552 .equ GPIO_AFRH_OFFSET, 0x24
|
|
553 .equ GPIO_BRR_OFFSET, 0x28
|
|
554
|
|
555 #- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
|
|
556
|
|
557 #--- Port A GPIO configuration / address space: 0x4800_0000 .. 0x4800_03FF
|
|
558
|
|
559 .equ GPIOA_BASE, GPIO_BASE
|
|
560
|
|
561 .equ GPIOA_MODER, GPIOA_BASE + GPIO_MODER_OFFSET
|
|
562 .equ GPIOA_OTYPER, GPIOA_BASE + GPIO_OTYPER_OFFSET
|
|
563 .equ GPIOA_OSPEEDR, GPIOA_BASE + GPIO_OSPEEDR_OFFSET
|
|
564 .equ GPIOA_PUPDR, GPIOA_BASE + GPIO_PUPDR_OFFSET
|
|
565 .equ GPIOA_IDR, GPIOA_BASE + GPIO_IDR_OFFSET
|
|
566 .equ GPIOA_ODR, GPIOA_BASE + GPIO_ODR_OFFSET
|
|
567 .equ GPIOA_BSRR, GPIOA_BASE + GPIO_BSRR_OFFSET
|
|
568 .equ GPIOA_LCKR, GPIOA_BASE + GPIO_LCKR_OFFSET
|
|
569 .equ GPIOA_AFRL, GPIOA_BASE + GPIO_AFRL_OFFSET
|
|
570 .equ GPIOA_AFRH, GPIOA_BASE + GPIO_AFRH_OFFSET
|
|
571 .equ GPIOA_BRR, GPIOA_BASE + GPIO_BRR_OFFSET
|
|
572
|
|
573 #--- Port B GPIO configuration / address space: 0x4800_0400 .. 0x4800_07FF
|
|
574
|
|
575 .equ GPIOB_BASE, GPIO_BASE + 0x400
|
|
576
|
|
577 .equ GPIOB_MODER, GPIOB_BASE + GPIO_MODER_OFFSET
|
|
578 .equ GPIOB_OTYPER, GPIOB_BASE + GPIO_OTYPER_OFFSET
|
|
579 .equ GPIOB_OSPEEDR, GPIOB_BASE + GPIO_OSPEEDR_OFFSET
|
|
580 .equ GPIOB_PUPDR, GPIOB_BASE + GPIO_PUPDR_OFFSET
|
|
581 .equ GPIOB_IDR, GPIOB_BASE + GPIO_IDR_OFFSET
|
|
582 .equ GPIOB_ODR, GPIOB_BASE + GPIO_ODR_OFFSET
|
|
583 .equ GPIOB_BSRR, GPIOB_BASE + GPIO_BSRR_OFFSET
|
|
584 .equ GPIOB_LCKR, GPIOB_BASE + GPIO_LCKR_OFFSET
|
|
585 .equ GPIOB_AFRL, GPIOB_BASE + GPIO_AFRL_OFFSET
|
|
586 .equ GPIOB_AFRH, GPIOB_BASE + GPIO_AFRH_OFFSET
|
|
587 .equ GPIOB_BRR, GPIOB_BASE + GPIO_BRR_OFFSET
|
|
588
|
|
589 #--- Port C GPIO configuration / address space: 0x4800_0800 .. 0x4800_0BFF
|
|
590
|
|
591 .equ GPIOC_BASE, GPIO_BASE + 0x800
|
|
592
|
|
593 .equ GPIOC_MODER, GPIOC_BASE + GPIO_MODER_OFFSET
|
|
594 .equ GPIOC_OTYPER, GPIOC_BASE + GPIO_OTYPER_OFFSET
|
|
595 .equ GPIOC_OSPEEDR, GPIOC_BASE + GPIO_OSPEEDR_OFFSET
|
|
596 .equ GPIOC_PUPDR, GPIOC_BASE + GPIO_PUPDR_OFFSET
|
|
597 .equ GPIOC_IDR, GPIOC_BASE + GPIO_IDR_OFFSET
|
|
598 .equ GPIOC_ODR, GPIOC_BASE + GPIO_ODR_OFFSET
|
|
599 .equ GPIOC_BSRR, GPIOC_BASE + GPIO_BSRR_OFFSET
|
|
600 .equ GPIOC_LCKR, GPIOC_BASE + GPIO_LCKR_OFFSET
|
|
601 .equ GPIOC_AFRL, GPIOC_BASE + GPIO_AFRL_OFFSET
|
|
602 .equ GPIOC_AFRH, GPIOC_BASE + GPIO_AFRH_OFFSET
|
|
603 .equ GPIOC_BRR, GPIOC_BASE + GPIO_BRR_OFFSET
|
|
604
|
|
605 #--- Port D GPIO configuration / address space: 0x4800_0C00 .. 0x4800_0FFF
|
|
606
|
|
607 .equ GPIOD_BASE, GPIO_BASE + 0xC00
|
|
608
|
|
609 .equ GPIOD_MODER, GPIOD_BASE + GPIO_MODER_OFFSET
|
|
610 .equ GPIOD_OTYPER, GPIOD_BASE + GPIO_OTYPER_OFFSET
|
|
611 .equ GPIOD_OSPEEDR, GPIOD_BASE + GPIO_OSPEEDR_OFFSET
|
|
612 .equ GPIOD_PUPDR, GPIOD_BASE + GPIO_PUPDR_OFFSET
|
|
613 .equ GPIOD_IDR, GPIOD_BASE + GPIO_IDR_OFFSET
|
|
614 .equ GPIOD_ODR, GPIOD_BASE + GPIO_ODR_OFFSET
|
|
615 .equ GPIOD_BSRR, GPIOD_BASE + GPIO_BSRR_OFFSET
|
|
616 .equ GPIOD_LCKR, GPIOD_BASE + GPIO_LCKR_OFFSET
|
|
617 .equ GPIOD_AFRL, GPIOD_BASE + GPIO_AFRL_OFFSET
|
|
618 .equ GPIOD_AFRH, GPIOD_BASE + GPIO_AFRH_OFFSET
|
|
619 .equ GPIOD_BRR, GPIOD_BASE + GPIO_BRR_OFFSET
|
|
620
|
|
621 #--- Port E GPIO configuration / address space: 0x4800_1000 .. 0x4800_13FF
|
|
622
|
|
623 .equ GPIOE_BASE, GPIO_BASE + 0x1000
|
|
624
|
|
625 .equ GPIOE_MODER, GPIOE_BASE + GPIO_MODER_OFFSET
|
|
626 .equ GPIOE_OTYPER, GPIOE_BASE + GPIO_OTYPER_OFFSET
|
|
627 .equ GPIOE_OSPEEDR, GPIOE_BASE + GPIO_OSPEEDR_OFFSET
|
|
628 .equ GPIOE_PUPDR, GPIOE_BASE + GPIO_PUPDR_OFFSET
|
|
629 .equ GPIOE_IDR, GPIOE_BASE + GPIO_IDR_OFFSET
|
|
630 .equ GPIOE_ODR, GPIOE_BASE + GPIO_ODR_OFFSET
|
|
631 .equ GPIOE_BSRR, GPIOE_BASE + GPIO_BSRR_OFFSET
|
|
632 .equ GPIOE_LCKR, GPIOE_BASE + GPIO_LCKR_OFFSET
|
|
633 .equ GPIOE_AFRL, GPIOE_BASE + GPIO_AFRL_OFFSET
|
|
634 .equ GPIOE_AFRH, GPIOE_BASE + GPIO_AFRH_OFFSET
|
|
635 .equ GPIOE_BRR, GPIOE_BASE + GPIO_BRR_OFFSET
|
|
636
|
|
637 #--- Port F GPIO configuration / address space: 0x4800_1400 .. 0x4800_17FF
|
|
638
|
|
639 .equ GPIOF_BASE, GPIO_BASE + 0x1400
|
|
640
|
|
641 .equ GPIOF_MODER, GPIOF_BASE + GPIO_MODER_OFFSET
|
|
642 .equ GPIOF_OTYPER, GPIOF_BASE + GPIO_OTYPER_OFFSET
|
|
643 .equ GPIOF_OSPEEDR, GPIOF_BASE + GPIO_OSPEEDR_OFFSET
|
|
644 .equ GPIOF_PUPDR, GPIOF_BASE + GPIO_PUPDR_OFFSET
|
|
645 .equ GPIOF_IDR, GPIOF_BASE + GPIO_IDR_OFFSET
|
|
646 .equ GPIOF_ODR, GPIOF_BASE + GPIO_ODR_OFFSET
|
|
647 .equ GPIOF_BSRR, GPIOF_BASE + GPIO_BSRR_OFFSET
|
|
648 .equ GPIOF_LCKR, GPIOF_BASE + GPIO_LCKR_OFFSET
|
|
649 .equ GPIOF_AFRL, GPIOF_BASE + GPIO_AFRL_OFFSET
|
|
650 .equ GPIOF_AFRH, GPIOF_BASE + GPIO_AFRH_OFFSET
|
|
651 .equ GPIOF_BRR, GPIOF_BASE + GPIO_BRR_OFFSET
|
|
652
|
|
653 #--- Port G GPIO configuration / address space: 0x4800_1800 .. 0x4800_1BFF
|
|
654
|
|
655 .equ GPIOG_BASE, GPIO_BASE + 0x1800
|
|
656
|
|
657 .equ GPIOG_MODER, GPIOG_BASE + GPIO_MODER_OFFSET
|
|
658 .equ GPIOG_OTYPER, GPIOG_BASE + GPIO_OTYPER_OFFSET
|
|
659 .equ GPIOG_OSPEEDR, GPIOG_BASE + GPIO_OSPEEDR_OFFSET
|
|
660 .equ GPIOG_PUPDR, GPIOG_BASE + GPIO_PUPDR_OFFSET
|
|
661 .equ GPIOG_IDR, GPIOG_BASE + GPIO_IDR_OFFSET
|
|
662 .equ GPIOG_ODR, GPIOG_BASE + GPIO_ODR_OFFSET
|
|
663 .equ GPIOG_BSRR, GPIOG_BASE + GPIO_BSRR_OFFSET
|
|
664 .equ GPIOG_LCKR, GPIOG_BASE + GPIO_LCKR_OFFSET
|
|
665 .equ GPIOG_AFRL, GPIOG_BASE + GPIO_AFRL_OFFSET
|
|
666 .equ GPIOG_AFRH, GPIOG_BASE + GPIO_AFRH_OFFSET
|
|
667 .equ GPIOG_BRR, GPIOG_BASE + GPIO_BRR_OFFSET
|
|
668
|
|
669 #----------------------------------------------------------------------------------------#
|
|
670 # System Control Space
|
|
671 #
|
|
672 # address space: 0xE000_E000 .. 0xE000_EFFF
|
|
673 #----------------------------------------------------------------------------------------#
|
|
674
|
|
675 .equ SCS_BASE, PPB_BASE + 0xE000
|
|
676
|
|
677 #----------------------------------------------------------------------------------------#
|
|
678 # System Timer (SysTick)
|
|
679 #
|
|
680 # address space: 0xE000_E010 .. 0xE000_E01F
|
|
681 #----------------------------------------------------------------------------------------#
|
|
682
|
|
683 .equ STK_BASE, SCS_BASE + 10 // 0xE000_E010
|
|
684
|
|
685 .equ STK_CTRL, SCS_BASE + 0x00
|
|
686 .equ STK_LOAD, SCS_BASE + 0x04
|
|
687 .equ STK_VAL, SCS_BASE + 0x08
|
|
688 .equ STK_CALIB, SCS_BASE + 0x0C
|
|
689
|
|
690 #----------------------------------------------------------------------------------------#
|
|
691 # Nested Vector Interrupt Controller
|
|
692 #
|
|
693 # address space: 0xE000_E100 .. 0xE000_E4EF
|
|
694 #----------------------------------------------------------------------------------------#
|
|
695
|
|
696 .equ NVIC_BASE, SCS_BASE + 0x100 // 0xE000_E100
|
|
697
|
|
698 .equ NVIC_ISER0, NVIC_BASE + 0x00
|
|
699 .equ NVIC_ISER1, NVIC_BASE + 0x04
|
|
700 .equ NVIC_ISER2, NVIC_BASE + 0x08
|
|
701 .equ NVIC_ISER3, NVIC_BASE + 0x0C
|
|
702
|
|
703 .equ NVIC_ICER0, NVIC_BASE + 0x80
|
|
704 .equ NVIC_ICER1, NVIC_BASE + 0x84
|
|
705 .equ NVIC_ICER2, NVIC_BASE + 0x88
|
|
706 .equ NVIC_ICER3, NVIC_BASE + 0x8C
|
|
707
|
|
708 .equ NVIC_ISPR0, NVIC_BASE + 0x100
|
|
709 .equ NVIC_ISPR1, NVIC_BASE + 0x104
|
|
710 .equ NVIC_ISPR2, NVIC_BASE + 0x108
|
|
711 .equ NVIC_ISPR3, NVIC_BASE + 0x10C
|
|
712
|
|
713 .equ NVIC_ICPR0, NVIC_BASE + 0x180
|
|
714 .equ NVIC_ICPR1, NVIC_BASE + 0x184
|
|
715 .equ NVIC_ICPR2, NVIC_BASE + 0x188
|
|
716 .equ NVIC_ICPR3, NVIC_BASE + 0x18C
|
|
717
|
|
718 .equ NVIC_IABR0, NVIC_BASE + 0x200
|
|
719 .equ NVIC_IABR1, NVIC_BASE + 0x204
|
|
720 .equ NVIC_IABR2, NVIC_BASE + 0x208
|
|
721 .equ NVIC_IABR3, NVIC_BASE + 0x20C
|
|
722
|
|
723 .equ NVIC_IPR0, NVIC_BASE + 0x300
|
|
724 .equ NVIC_IPR1, NVIC_BASE + 0x304
|
|
725 .equ NVIC_IPR2, NVIC_BASE + 0x308
|
|
726 .equ NVIC_IPR3, NVIC_BASE + 0x30C
|
|
727 .equ NVIC_IPR4, NVIC_BASE + 0x310
|
|
728 .equ NVIC_IPR5, NVIC_BASE + 0x314
|
|
729 .equ NVIC_IPR6, NVIC_BASE + 0x318
|
|
730 .equ NVIC_IPR7, NVIC_BASE + 0x31C
|
|
731 .equ NVIC_IPR8, NVIC_BASE + 0x320
|
|
732 .equ NVIC_IPR9, NVIC_BASE + 0x324
|
|
733 .equ NVIC_IPR10, NVIC_BASE + 0x328
|
|
734 .equ NVIC_IPR11, NVIC_BASE + 0x32C
|
|
735 .equ NVIC_IPR12, NVIC_BASE + 0x330
|
|
736 .equ NVIC_IPR13, NVIC_BASE + 0x334
|
|
737 .equ NVIC_IPR14, NVIC_BASE + 0x338
|
|
738 .equ NVIC_IPR15, NVIC_BASE + 0x33C
|
|
739 .equ NVIC_IPR16, NVIC_BASE + 0x340
|
|
740 .equ NVIC_IPR17, NVIC_BASE + 0x344
|
|
741 .equ NVIC_IPR18, NVIC_BASE + 0x348
|
|
742 .equ NVIC_IPR19, NVIC_BASE + 0x34C
|
|
743 .equ NVIC_IPR20, NVIC_BASE + 0x350
|
|
744 .equ NVIC_IPR21, NVIC_BASE + 0x354
|
|
745 .equ NVIC_IPR22, NVIC_BASE + 0x358
|
|
746 .equ NVIC_IPR23, NVIC_BASE + 0x35C
|
|
747 .equ NVIC_IPR24, NVIC_BASE + 0x360
|
|
748 .equ NVIC_IPR25, NVIC_BASE + 0x364
|
|
749
|
|
750 .equ STIR, NVIC_BASE + 0xE00
|
|
751
|
|
752 #----------------------------------------------------------------------------------------#
|
|
753 # MCU Debug Component
|
|
754 #
|
|
755 # address space: 0xE004_2000 .. 0xE004_2013
|
|
756 #----------------------------------------------------------------------------------------#
|
|
757
|
|
758 .equ DBGMCU_BASE, PPB_BASE + 0x42000
|
|
759
|
|
760 .equ DBGMCU_IDCODE, DBGMCU_BASE + 0x00
|
|
761 .equ DBGMCU_CR, DBGMCU_BASE + 0x04
|
|
762 .equ DBGMCU_APB1FZR1, DBGMCU_BASE + 0x08
|
|
763 .equ DBGMCU_APB1FZR2, DBGMCU_BASE + 0x0C
|
|
764 .equ DBGMCU_APB2DZR, DBGMCU_BASE + 0x10
|
|
42
|
|
43
|
|
44 #----------------------------------------------------------------------------------------#
|
|
45 .section .vectortable,"a" // vector table at begin of ROM
|
|
46 #----------------------------------------------------------------------------------------#
|
|
47
|
|
48 .align 2
|
|
49
|
|
50 0000 00400020 .word 0x20004000 // initial Stack Pointer: 0x20000000 (RAM base) + 0x4000 (16K SRA
|
|
51 0004 01040008 .word 0x08000401 // initial Program Counter
|
|
52 0008 00000000 .word _ISR_NMI // non-masking interrupt
|
|
53 000c 00000000 .word _ISR_HARDF // hard fault interrupt
|
|
54
|
|
55
|
|
56
|
|
57 /* N.B.
|
|
58 Look at the .space or the .org assembler directive to insert the address of the
|
|
59 ISRs at the right place in the vector table. Verify your settings by the help of
|
|
60 the list file. */
|
|
61
|
|
62 0010 00000000 .word _ISR_S0
|
|
63
|
|
64
|
|
65 #----------------------------------------------------------------------------------------#
|
|
66 .text // section .text (default section for program code)
|
|
67 #----------------------------------------------------------------------------------------#
|
|
68
|
|
69 .align 2
|
|
70 .syntax unified
|
|
71 .thumb
|
|
72 .thumb_func
|
|
73 .global init
|
|
75 init:
|
|
76 0000 72B6 CPSID i // disable interrupts globally
|
|
77
|
|
78 0002 0020 MOVS r0, #0 // safely initialize the GPRs
|
|
79 0004 0021 MOVS r1, #0
|
|
80 0006 0022 MOVS r2, #0
|
|
81 0008 0023 MOVS r3, #0
|
|
82 000a 0024 MOVS r4, #0
|
|
83 000c 0025 MOVS r5, #0
|
|
84 000e 0026 MOVS r6, #0
|
|
85 0010 0027 MOVS r7, #0
|
|
86 0012 8046 MOV r8, r0
|
|
87 0014 8146 MOV r9, r0
|
|
88 0016 8246 MOV r10, r0
|
|
89 0018 8346 MOV r11, r0
|
|
90 001a 8446 MOV r12, r0
|
|
91
|
|
92 #--- enable port clocking
|
|
93 001c 1249 LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
|
|
94 001e 4FF00102 MOV r2, #0x01 // load mask for adjusting port clock gating (A: LEDs)
|
|
95 0022 0868 LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
|
|
96 0024 1043 ORRS r0, r0, r2 // configure clock gating for ports
|
|
97 0026 0860 STR r0, [r1, #0] // apply settings
|
|
98
|
|
99 #--- port init
|
|
100 #- LEDs
|
|
101 0028 4FF09041 LDR r1, =GPIOA_MODER // load port A mode register address
|
|
102 002c 0322 MOVS r2, #0x03 // prepare mask
|
|
103 002e 0868 LDR r0, [r1, #0] // get current value of port A mode register
|
|
104 0030 9043 BICS r0, r2 // delete bits
|
|
105 0032 0122 MOVS r2, #0x01 // load configuration mask
|
|
106 0034 1043 ORRS r0, r0, r2 // apply mask
|
|
107 0036 0860 STR r0, [r1, #0] // apply result to port A mode register
|
|
108
|
|
109 # LDR r1, =GPIOB_MODER
|
|
110 # MOVS r3, #0x03
|
|
111 # LDR r0, [r1, #1]
|
|
112 # BICS r0, r3
|
|
113 # MOVS r3, #0x01
|
|
114 # ORRS r0, r0, r3
|
|
115 # STR r0, [r1, #1]
|
|
116
|
|
117 #- switch LED off
|
|
118 0038 0C49 LDR r1, =GPIOA_ODR // load port A output data register
|
|
119 003a 0122 MOVS r2, #0x01 // load mask for LED
|
|
120 003c 0868 LDR r0, [r1, #0] // get current value of GPIOA
|
|
121 003e 1043 ORRS r0, r0, r2 // configure pin state
|
|
122 0040 0860 STR r0, [r1, #0] // apply settings
|
|
123
|
|
124 #- buttons
|
|
125
|
|
126 /* ... place your code here ... */
|
|
127
|
|
128
|
|
129 #--- button interrupt config
|
|
130
|
|
131 #- enable clock for SYSCFG module
|
|
132
|
|
133
|
|
134 #- connect GPIO pins of the buttons to EXTended Interrupt controller lines (EXTI)
|
|
135 # in SYSCFG module (SYSCFG_* registers)
|
|
136
|
|
137
|
|
138
|
|
139
|
|
140 #- configure lines in EXTI module (EXTI_* registers)
|
|
141
|
|
142
|
|
143
|
|
144 #- NVIC: set interrupt priority, clear pending bits
|
|
145 # and enable interrupts for buttons (see: PM, ch. 4.3, NVIC)
|
|
146
|
|
147
|
|
148
|
|
149 0042 62B6 CPSIE i // enable interrupts globally
|
|
150
|
|
151
|
|
152 #----------------------------------------------------------------------------------------#
|
|
153
|
|
154 .align 2
|
|
155 .syntax unified
|
|
156 .thumb
|
|
157 .thumb_func
|
|
158 .global main
|
|
160 main:
|
|
161 0044 0949 LDR r1, =GPIOA_ODR
|
|
162 0046 5040 EORS r0, r0, r2
|
|
163
|
|
164 0048 0860 STR r0, [r1, #0]
|
|
165
|
|
166
|
|
167
|
|
168 004a FFF7FEFF BL delay
|
|
169
|
|
170
|
|
171 004e FFF7FEBF B main
|
|
172
|
|
173
|
|
174 #----------------------------------------------------------------------------------------#
|
|
175
|
|
176 0052 00BF .align 2
|
|
177 .syntax unified
|
|
178 .thumb
|
|
179 .thumb_func
|
|
180 .global delay
|
|
182 delay:
|
|
183 0054 0026 MOVS r6, #0 // ...
|
|
184 0056 064F LDR r7, =2000000 // ...
|
|
185 .L1:
|
|
186 0058 0136 ADDS r6, r6, #1 // ...
|
|
187 005a BE42 CMP r6, r7 // ...
|
|
188 005c FCD1 BNE .L1 // ...
|
|
189 005e 7047 BX lr // ...
|
|
190
|
|
191
|
|
192 #----------------------------------------------------------------------------------------#
|
|
193
|
|
194 .align 2
|
|
195 .global stop
|
|
196 stop:
|
|
197 0060 00BF NOP // do nothing (NOP is here to avoid a debugger crash, only)
|
|
198 0062 FFF7FEBF B stop // if this line is reached, something went wrong
|
|
199
|
|
200
|
|
201 #----------------------------------------------------------------------------------------#
|
|
202 .lp1: // this label is only to nicify the line up in the .lst file
|
|
203 0066 00004C10 .ltorg
|
|
203 02401400
|
|
203 00488084
|
|
203 1E00
|
|
204 #----------------------------------------------------------------------------------------#
|
|
205
|
|
206
|
|
207 #----------------------------------------------------------------------------------------#
|
|
208 .section .exhand,"ax" // section for exception handlers
|
|
209 #----------------------------------------------------------------------------------------#
|
|
210
|
|
211 .align 2
|
|
212 .syntax unified
|
|
213 .thumb
|
|
215 _ISR_NMI:
|
|
216 #--- enable clock
|
|
217 0000 1749 LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
|
|
218 0002 4FF00102 MOV r2, #0x01 // load mask
|
|
219 0006 0868 LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
|
|
220 0008 1043 ORRS r0, r0, r2 // configure clock gating for port
|
|
221 000a 0860 STR r0, [r1, #0] // apply settings
|
|
222
|
|
223 #--- init pins
|
|
224 000c 4FF09041 LDR r1, =GPIOA_MODER // load port A mode register address
|
|
225 0010 FF22 MOVS r2, #0xFF // prepare mask
|
|
226 0012 0868 LDR r0, [r1, #0] // get current value of port A mode register
|
|
227 0014 9043 BICS r0, r0, r2 // delete bits
|
|
228 0016 4422 MOVS r2, #0x44 // load configuration mask
|
|
229 0018 1043 ORRS r0, r0, r2 // configure pins
|
|
230 001a 0860 STR r0, [r1, #0] // apply settings to port A mode register
|
|
231
|
|
232 #--- switch some LEDs on
|
|
233 001c 1149 LDR r1, =GPIOA_ODR // load port A data output register address
|
|
234 001e 0A22 MOVS r2, #0x0A // load mask for blue and yellow LED
|
|
235 0020 0868 LDR r0, [r1, #0]
|
|
236 0022 9043 BICS r0, r0, r2
|
|
237 0024 0860 STR r0, [r1, #0] // switch LEDs on
|
|
238
|
|
239 0026 EBE7 B _ISR_NMI
|
|
240
|
|
241
|
|
242 #----------------------------------------------------------------------------------------#
|
|
243
|
|
244 .align 2
|
|
245 .syntax unified
|
|
246 .thumb
|
|
248 _ISR_HARDF:
|
|
249 #--- enable clock
|
|
250 0028 0D49 LDR r1, =RCC_AHB2ENR // load address of RCC_AHB2ENR
|
|
251 002a 4FF00102 MOV r2, #0x01 // load mask
|
|
252 002e 0868 LDR r0, [r1, #0] // get current value of RCC_AHB2ENR
|
|
253 0030 1043 ORRS r0, r0, r2 // configure clock gating for port
|
|
254 0032 0860 STR r0, [r1, #0] // apply settings
|
|
255
|
|
256 #--- init pins
|
|
257 0034 4FF09041 LDR r1, =GPIOA_MODER // load port A mode register address
|
|
258 0038 FF22 MOVS r2, #0xFF // prepare mask
|
|
259 003a 0868 LDR r0, [r1, #0] // get current value of port A mode register
|
|
260 003c 9043 BICS r0, r0, r2 // delete bits
|
|
261 003e 1122 MOVS r2, #0x11 // load configuration mask
|
|
262 0040 1043 ORRS r0, r0, r2 // configure pins
|
|
263 0042 0860 STR r0, [r1, #0] // apply settings to port A mode register
|
|
264
|
|
265 #--- switch some LEDs on
|
|
266 0044 0749 LDR r1, =GPIOA_ODR // load port A data output register address
|
|
267 0046 0522 MOVS r2, #0x05 // load mask for red and green LED
|
|
268 0048 0868 LDR r0, [r1, #0]
|
|
269 004a 9043 BICS r0, r0, r2
|
|
270 004c 0860 STR r0, [r1, #0] // switch LEDs on
|
|
271
|
|
272 004e EBE7 B _ISR_HARDF
|
|
273
|
|
274
|
|
275 #----------------------------------------------------------------------------------------#
|
|
276
|
|
277 .align 2
|
|
278 .syntax unified
|
|
279 .thumb
|
|
281 _ISR_S0:
|
|
282 0050 00B5 PUSH {lr} // save special content
|
|
283
|
|
284 #--- do the work
|
|
285
|
|
286
|
|
287 #--- clear interrupt flag
|
|
288
|
|
289
|
|
290 #--- leave ISR
|
|
291 0052 02BC POP {r1} // get special content back
|
|
292 0054 0847 BX r1 // go back to where we came from
|
|
293
|
|
294
|
|
295 #----------------------------------------------------------------------------------------#
|
|
296
|
|
297 0056 00BF .align 2
|
|
298 .syntax unified
|
|
299 .thumb
|
|
301 _ISR_S1:
|
|
302 0058 00B5 PUSH {lr} // save special content
|
|
303
|
|
304 #--- do the work
|
|
305
|
|
306
|
|
307
|
|
308
|
|
309 #--- clear interrupt flag
|
|
310
|
|
311
|
|
312
|
|
313 #--- leave ISR
|
|
314 005a 02BC POP {r1} // get special content back
|
|
315 005c 0847 BX r1 // go back to where we came from
|
|
316
|
|
317
|
|
318 #----------------------------------------------------------------------------------------#
|
|
319 .lp2: // this label is only to nicify the line up in the .lst file
|
|
320 005e 00004C10 .ltorg
|
|
320 02401400
|
|
320 0048
|
|
321 #----------------------------------------------------------------------------------------#
|
|
322
|
|
323 .end
|
|
DEFINED SYMBOLS
|
|
G431_addr.s:39 *ABS*:40000000 APB1_BASE
|
|
G431_addr.s:40 *ABS*:40010000 APB2_BASE
|
|
G431_addr.s:41 *ABS*:40020000 AHB1_BASE
|
|
G431_addr.s:42 *ABS*:48000000 AHB2_BASE
|
|
G431_addr.s:43 *ABS*:a0000000 AHB3_BASE
|
|
G431_addr.s:44 *ABS*:e0000000 PPB_BASE
|
|
G431_addr.s:52 *ABS*:40010000 SYSCFG_BASE
|
|
G431_addr.s:54 *ABS*:40010000 SYSCFG_MEMRMP
|
|
G431_addr.s:55 *ABS*:40010004 SYSCFG_CFGR1
|
|
G431_addr.s:56 *ABS*:40010008 SYSCFG_EXTICR1
|
|
G431_addr.s:57 *ABS*:4001000c SYSCFG_EXTICR2
|
|
G431_addr.s:58 *ABS*:40010010 SYSCFG_EXTICR3
|
|
G431_addr.s:59 *ABS*:40010014 SYSCFG_EXTICR4
|
|
G431_addr.s:60 *ABS*:40010018 SYSCFG_SCSR
|
|
G431_addr.s:61 *ABS*:4001001c SYSCFG_CFGR2
|
|
G431_addr.s:62 *ABS*:40010020 SYSCFG_SWPR
|
|
G431_addr.s:63 *ABS*:40010024 SYSCFG_SKR
|
|
G431_addr.s:71 *ABS*:40010400 EXTI_BASE
|
|
G431_addr.s:73 *ABS*:40010400 EXTI_IMR1
|
|
G431_addr.s:74 *ABS*:40010404 EXTI_EMR1
|
|
G431_addr.s:75 *ABS*:40010408 EXTI_RTSR1
|
|
G431_addr.s:76 *ABS*:4001040c EXTI_FTSR1
|
|
G431_addr.s:77 *ABS*:40010410 EXTI_SWIER1
|
|
G431_addr.s:78 *ABS*:40010414 EXTI_PR1
|
|
G431_addr.s:80 *ABS*:40010420 EXTI_IMR2
|
|
G431_addr.s:81 *ABS*:40010424 EXTI_EMR2
|
|
G431_addr.s:82 *ABS*:40010428 EXTI_RTSR2
|
|
G431_addr.s:83 *ABS*:4001042c EXTI_FTSR2
|
|
G431_addr.s:84 *ABS*:40010430 EXTI_SWIER2
|
|
G431_addr.s:85 *ABS*:40010434 EXTI_PR2
|
|
G431_addr.s:109 *ABS*:00000000 TIM_CR1_OFFSET
|
|
G431_addr.s:110 *ABS*:00000004 TIM_CR2_OFFSET
|
|
G431_addr.s:111 *ABS*:00000008 TIM_SMCR_OFFSET
|
|
G431_addr.s:112 *ABS*:0000000c TIM_DIER_OFFSET
|
|
G431_addr.s:113 *ABS*:00000010 TIM_SR_OFFSET
|
|
G431_addr.s:114 *ABS*:00000014 TIM_EGR_OFFSET
|
|
G431_addr.s:115 *ABS*:00000018 TIM_CCMR1_OFFSET
|
|
G431_addr.s:116 *ABS*:0000001c TIM_CCMR2_OFFSET
|
|
G431_addr.s:117 *ABS*:00000020 TIM_CCER_OFFSET
|
|
G431_addr.s:118 *ABS*:00000024 TIM_CNT_OFFSET
|
|
G431_addr.s:119 *ABS*:00000028 TIM_PSC_OFFSET
|
|
G431_addr.s:120 *ABS*:0000002c TIM_ARR_OFFSET
|
|
G431_addr.s:121 *ABS*:00000030 TIM_RCR_OFFSET
|
|
G431_addr.s:122 *ABS*:00000034 TIM_CCR1_OFFSET
|
|
G431_addr.s:123 *ABS*:00000038 TIM_CCR2_OFFSET
|
|
G431_addr.s:124 *ABS*:0000003c TIM_CCR3_OFFSET
|
|
G431_addr.s:125 *ABS*:00000040 TIM_CCR4_OFFSET
|
|
G431_addr.s:126 *ABS*:00000044 TIM_BDTR_OFFSET
|
|
G431_addr.s:127 *ABS*:00000048 TIM_CCR5_OFFSET
|
|
G431_addr.s:128 *ABS*:0000004c TIM_CCR6_OFFSET
|
|
G431_addr.s:129 *ABS*:00000050 TIM_CCMR3_OFFSET
|
|
G431_addr.s:130 *ABS*:00000054 TIM_DTR2_OFFSET
|
|
G431_addr.s:131 *ABS*:00000058 TIM_ECR_OFFSET
|
|
G431_addr.s:132 *ABS*:0000005c TIM_TISEL_OFFSET
|
|
G431_addr.s:133 *ABS*:00000060 TIM_AF1_OFFSET
|
|
G431_addr.s:134 *ABS*:00000064 TIM_AF2_OFFSET
|
|
G431_addr.s:135 *ABS*:00000068 TIM_OR1_OFFSET
|
|
G431_addr.s:137 *ABS*:000003dc TIM_DCR_OFFSET
|
|
G431_addr.s:138 *ABS*:000003e0 TIM_DMAR_OFFSET
|
|
G431_addr.s:144 *ABS*:40000000 TIM2_BASE
|
|
G431_addr.s:146 *ABS*:40000000 TIM2_CR1
|
|
G431_addr.s:147 *ABS*:40000004 TIM2_CR2
|
|
G431_addr.s:148 *ABS*:40000008 TIM2_SMCR
|
|
G431_addr.s:149 *ABS*:4000000c TIM2_DIER
|
|
G431_addr.s:150 *ABS*:40000010 TIM2_SR
|
|
G431_addr.s:151 *ABS*:40000014 TIM2_EGR
|
|
G431_addr.s:152 *ABS*:40000018 TIM2_CCMR1
|
|
G431_addr.s:153 *ABS*:4000001c TIM2_CCMR2
|
|
G431_addr.s:154 *ABS*:40000020 TIM2_CCER
|
|
G431_addr.s:155 *ABS*:40000024 TIM2_CNT
|
|
G431_addr.s:156 *ABS*:40000028 TIM2_PSC
|
|
G431_addr.s:157 *ABS*:4000002c TIM2_ARR
|
|
G431_addr.s:159 *ABS*:40000034 TIM2_CCR1
|
|
G431_addr.s:160 *ABS*:40000038 TIM2_CCR2
|
|
G431_addr.s:161 *ABS*:4000003c TIM2_CCR3
|
|
G431_addr.s:162 *ABS*:40000040 TIM2_CCR4
|
|
G431_addr.s:164 *ABS*:40000058 TIM2_ECR
|
|
G431_addr.s:165 *ABS*:4000005c TIM2_TISEL
|
|
G431_addr.s:166 *ABS*:40000058 TIM2_AF1
|
|
G431_addr.s:167 *ABS*:40000058 TIM2_AF2
|
|
G431_addr.s:169 *ABS*:400003dc TIM2_DCR
|
|
G431_addr.s:170 *ABS*:400003e0 TIM2_DMAR
|
|
G431_addr.s:174 *ABS*:40000400 TIM3_BASE
|
|
G431_addr.s:176 *ABS*:40000400 TIM3_CR1
|
|
G431_addr.s:177 *ABS*:40000404 TIM3_CR2
|
|
G431_addr.s:178 *ABS*:40000408 TIM3_SMCR
|
|
G431_addr.s:179 *ABS*:4000040c TIM3_DIER
|
|
G431_addr.s:180 *ABS*:40000410 TIM3_SR
|
|
G431_addr.s:181 *ABS*:40000414 TIM3_EGR
|
|
G431_addr.s:182 *ABS*:40000418 TIM3_CCMR1
|
|
G431_addr.s:183 *ABS*:4000041c TIM3_CCMR2
|
|
G431_addr.s:184 *ABS*:40000420 TIM3_CCER
|
|
G431_addr.s:185 *ABS*:40000424 TIM3_CNT
|
|
G431_addr.s:186 *ABS*:40000428 TIM3_PSC
|
|
G431_addr.s:187 *ABS*:4000042c TIM3_ARR
|
|
G431_addr.s:189 *ABS*:40000434 TIM3_CCR1
|
|
G431_addr.s:190 *ABS*:40000438 TIM3_CCR2
|
|
G431_addr.s:191 *ABS*:4000043c TIM3_CCR3
|
|
G431_addr.s:192 *ABS*:40000440 TIM3_CCR4
|
|
G431_addr.s:194 *ABS*:40000458 TIM3_ECR
|
|
G431_addr.s:195 *ABS*:4000045c TIM3_TISEL
|
|
G431_addr.s:196 *ABS*:40000458 TIM3_AF1
|
|
G431_addr.s:197 *ABS*:40000458 TIM3_AF2
|
|
G431_addr.s:199 *ABS*:400007dc TIM3_DCR
|
|
G431_addr.s:200 *ABS*:400007e0 TIM3_DMAR
|
|
G431_addr.s:204 *ABS*:40000800 TIM4_BASE
|
|
G431_addr.s:206 *ABS*:40000800 TIM4_CR1
|
|
G431_addr.s:207 *ABS*:40000804 TIM4_CR2
|
|
G431_addr.s:208 *ABS*:40000808 TIM4_SMCR
|
|
G431_addr.s:209 *ABS*:4000080c TIM4_DIER
|
|
G431_addr.s:210 *ABS*:40000810 TIM4_SR
|
|
G431_addr.s:211 *ABS*:40000814 TIM4_EGR
|
|
G431_addr.s:212 *ABS*:40000818 TIM4_CCMR1
|
|
G431_addr.s:213 *ABS*:4000081c TIM4_CCMR2
|
|
G431_addr.s:214 *ABS*:40000820 TIM4_CCER
|
|
G431_addr.s:215 *ABS*:40000824 TIM4_CNT
|
|
G431_addr.s:216 *ABS*:40000828 TIM4_PSC
|
|
G431_addr.s:217 *ABS*:4000082c TIM4_ARR
|
|
G431_addr.s:219 *ABS*:40000834 TIM4_CCR1
|
|
G431_addr.s:220 *ABS*:40000838 TIM4_CCR2
|
|
G431_addr.s:221 *ABS*:4000083c TIM4_CCR3
|
|
G431_addr.s:222 *ABS*:40000840 TIM4_CCR4
|
|
G431_addr.s:224 *ABS*:40000858 TIM4_ECR
|
|
G431_addr.s:225 *ABS*:4000085c TIM4_TISEL
|
|
G431_addr.s:226 *ABS*:40000858 TIM4_AF1
|
|
G431_addr.s:227 *ABS*:40000858 TIM4_AF2
|
|
G431_addr.s:229 *ABS*:40000bdc TIM4_DCR
|
|
G431_addr.s:230 *ABS*:40000be0 TIM4_DMAR
|
|
G431_addr.s:234 *ABS*:40000c00 TIM5_BASE
|
|
G431_addr.s:236 *ABS*:40000c00 TIM5_CR1
|
|
G431_addr.s:237 *ABS*:40000c04 TIM5_CR2
|
|
G431_addr.s:238 *ABS*:40000c08 TIM5_SMCR
|
|
G431_addr.s:239 *ABS*:40000c0c TIM5_DIER
|
|
G431_addr.s:240 *ABS*:40000c10 TIM5_SR
|
|
G431_addr.s:241 *ABS*:40000c14 TIM5_EGR
|
|
G431_addr.s:242 *ABS*:40000c18 TIM5_CCMR1
|
|
G431_addr.s:243 *ABS*:40000c1c TIM5_CCMR2
|
|
G431_addr.s:244 *ABS*:40000c20 TIM5_CCER
|
|
G431_addr.s:245 *ABS*:40000c24 TIM5_CNT
|
|
G431_addr.s:246 *ABS*:40000c28 TIM5_PSC
|
|
G431_addr.s:247 *ABS*:40000c2c TIM5_ARR
|
|
G431_addr.s:249 *ABS*:40000c34 TIM5_CCR1
|
|
G431_addr.s:250 *ABS*:40000c38 TIM5_CCR2
|
|
G431_addr.s:251 *ABS*:40000c3c TIM5_CCR3
|
|
G431_addr.s:252 *ABS*:40000c40 TIM5_CCR4
|
|
G431_addr.s:254 *ABS*:40000c58 TIM5_ECR
|
|
G431_addr.s:255 *ABS*:40000c5c TIM5_TISEL
|
|
G431_addr.s:256 *ABS*:40000c58 TIM5_AF1
|
|
G431_addr.s:257 *ABS*:40000c58 TIM5_AF2
|
|
G431_addr.s:259 *ABS*:40000fdc TIM5_DCR
|
|
G431_addr.s:260 *ABS*:40000fe0 TIM5_DMAR
|
|
G431_addr.s:264 *ABS*:40001000 TIM6_BASE
|
|
G431_addr.s:266 *ABS*:40001000 TIM6_CR1
|
|
G431_addr.s:267 *ABS*:40001004 TIM6_CR2
|
|
G431_addr.s:269 *ABS*:4000100c TIM6_DIER
|
|
G431_addr.s:270 *ABS*:40001010 TIM6_SR
|
|
G431_addr.s:271 *ABS*:40001014 TIM6_EGR
|
|
G431_addr.s:273 *ABS*:40001024 TIM6_CNT
|
|
G431_addr.s:274 *ABS*:40001028 TIM6_PSC
|
|
G431_addr.s:275 *ABS*:4000102c TIM6_ARR
|
|
G431_addr.s:279 *ABS*:40001400 TIM7_BASE
|
|
G431_addr.s:281 *ABS*:40001400 TIM7_CR1
|
|
G431_addr.s:282 *ABS*:40001404 TIM7_CR2
|
|
G431_addr.s:284 *ABS*:4000140c TIM7_DIER
|
|
G431_addr.s:285 *ABS*:40001410 TIM7_SR
|
|
G431_addr.s:286 *ABS*:40001414 TIM7_EGR
|
|
G431_addr.s:288 *ABS*:40001424 TIM7_CNT
|
|
G431_addr.s:289 *ABS*:40001428 TIM7_PSC
|
|
G431_addr.s:290 *ABS*:4000142c TIM7_ARR
|
|
G431_addr.s:294 *ABS*:40012c00 TIM1_BASE
|
|
G431_addr.s:296 *ABS*:40012c00 TIM1_CR1
|
|
G431_addr.s:297 *ABS*:40012c04 TIM1_CR2
|
|
G431_addr.s:298 *ABS*:40012c08 TIM1_SMCR
|
|
G431_addr.s:299 *ABS*:40012c0c TIM1_DIER
|
|
G431_addr.s:300 *ABS*:40012c10 TIM1_SR
|
|
G431_addr.s:301 *ABS*:40012c14 TIM1_EGR
|
|
G431_addr.s:302 *ABS*:40012c18 TIM1_CCMR1
|
|
G431_addr.s:303 *ABS*:40012c1c TIM1_CCMR2
|
|
G431_addr.s:304 *ABS*:40012c20 TIM1_CCER
|
|
G431_addr.s:305 *ABS*:40012c24 TIM1_CNT
|
|
G431_addr.s:306 *ABS*:40012c28 TIM1_PSC
|
|
G431_addr.s:307 *ABS*:40012c2c TIM1_ARR
|
|
G431_addr.s:308 *ABS*:40012c30 TIM1_RCR
|
|
G431_addr.s:309 *ABS*:40012c34 TIM1_CCR1
|
|
G431_addr.s:310 *ABS*:40012c38 TIM1_CCR2
|
|
G431_addr.s:311 *ABS*:40012c3c TIM1_CCR3
|
|
G431_addr.s:312 *ABS*:40012c40 TIM1_CCR4
|
|
G431_addr.s:313 *ABS*:40012c44 TIM1_BDTR
|
|
G431_addr.s:314 *ABS*:40012c48 TIM1_CCR5
|
|
G431_addr.s:315 *ABS*:40012c4c TIM1_CCR6
|
|
G431_addr.s:316 *ABS*:40012c50 TIM1_CCMR3
|
|
G431_addr.s:317 *ABS*:40012c54 TIM1_DTR2
|
|
G431_addr.s:318 *ABS*:40012c58 TIM1_ECR
|
|
G431_addr.s:319 *ABS*:40012c5c TIM1_TISEL
|
|
G431_addr.s:320 *ABS*:40012c60 TIM1_AF1
|
|
G431_addr.s:321 *ABS*:40012c64 TIM1_AF2
|
|
G431_addr.s:323 *ABS*:40012fdc TIM1_DCR
|
|
G431_addr.s:324 *ABS*:40012fe0 TIM1_DMAR
|
|
G431_addr.s:328 *ABS*:40013400 TIM8_BASE
|
|
G431_addr.s:330 *ABS*:40013400 TIM8_CR1
|
|
G431_addr.s:331 *ABS*:40013404 TIM8_CR2
|
|
G431_addr.s:332 *ABS*:40013408 TIM8_SMCR
|
|
G431_addr.s:333 *ABS*:4001340c TIM8_DIER
|
|
G431_addr.s:334 *ABS*:40013410 TIM8_SR
|
|
G431_addr.s:335 *ABS*:40013414 TIM8_EGR
|
|
G431_addr.s:336 *ABS*:40013418 TIM8_CCMR1
|
|
G431_addr.s:337 *ABS*:4001341c TIM8_CCMR2
|
|
G431_addr.s:338 *ABS*:40013420 TIM8_CCER
|
|
G431_addr.s:339 *ABS*:40013424 TIM8_CNT
|
|
G431_addr.s:340 *ABS*:40013428 TIM8_PSC
|
|
G431_addr.s:341 *ABS*:4001342c TIM8_ARR
|
|
G431_addr.s:342 *ABS*:40013430 TIM8_RCR
|
|
G431_addr.s:343 *ABS*:40013434 TIM8_CCR1
|
|
G431_addr.s:344 *ABS*:40013438 TIM8_CCR2
|
|
G431_addr.s:345 *ABS*:4001343c TIM8_CCR3
|
|
G431_addr.s:346 *ABS*:40013440 TIM8_CCR4
|
|
G431_addr.s:347 *ABS*:40013444 TIM8_BDTR
|
|
G431_addr.s:348 *ABS*:40013448 TIM8_CCR5
|
|
G431_addr.s:349 *ABS*:4001344c TIM8_CCR6
|
|
G431_addr.s:350 *ABS*:40013450 TIM8_CCMR3
|
|
G431_addr.s:351 *ABS*:40013454 TIM8_DTR2
|
|
G431_addr.s:352 *ABS*:40013458 TIM8_ECR
|
|
G431_addr.s:353 *ABS*:4001345c TIM8_TISEL
|
|
G431_addr.s:354 *ABS*:40013460 TIM8_AF1
|
|
G431_addr.s:355 *ABS*:40013464 TIM8_AF2
|
|
G431_addr.s:357 *ABS*:400137dc TIM8_DCR
|
|
G431_addr.s:358 *ABS*:400137e0 TIM8_DMAR
|
|
G431_addr.s:362 *ABS*:40015000 TIM20_BASE
|
|
G431_addr.s:364 *ABS*:40015000 TIM20_CR1
|
|
G431_addr.s:365 *ABS*:40015004 TIM20_CR2
|
|
G431_addr.s:366 *ABS*:40015008 TIM20_SMCR
|
|
G431_addr.s:367 *ABS*:4001500c TIM20_DIER
|
|
G431_addr.s:368 *ABS*:40015010 TIM20_SR
|
|
G431_addr.s:369 *ABS*:40015014 TIM20_EGR
|
|
G431_addr.s:370 *ABS*:40015018 TIM20_CCMR1
|
|
G431_addr.s:371 *ABS*:4001501c TIM20_CCMR2
|
|
G431_addr.s:372 *ABS*:40015020 TIM20_CCER
|
|
G431_addr.s:373 *ABS*:40015024 TIM20_CNT
|
|
G431_addr.s:374 *ABS*:40015028 TIM20_PSC
|
|
G431_addr.s:375 *ABS*:4001502c TIM20_ARR
|
|
G431_addr.s:376 *ABS*:40015030 TIM20_RCR
|
|
G431_addr.s:377 *ABS*:40015034 TIM20_CCR1
|
|
G431_addr.s:378 *ABS*:40015038 TIM20_CCR2
|
|
G431_addr.s:379 *ABS*:4001503c TIM20_CCR3
|
|
G431_addr.s:380 *ABS*:40015040 TIM20_CCR4
|
|
G431_addr.s:381 *ABS*:40015044 TIM20_BDTR
|
|
G431_addr.s:382 *ABS*:40015048 TIM20_CCR5
|
|
G431_addr.s:383 *ABS*:4001504c TIM20_CCR6
|
|
G431_addr.s:384 *ABS*:40015050 TIM20_CCMR3
|
|
G431_addr.s:385 *ABS*:40015054 TIM20_DTR2
|
|
G431_addr.s:386 *ABS*:40015058 TIM20_ECR
|
|
G431_addr.s:387 *ABS*:4001505c TIM20_TISEL
|
|
G431_addr.s:388 *ABS*:40015060 TIM20_AF1
|
|
G431_addr.s:389 *ABS*:40015064 TIM20_AF2
|
|
G431_addr.s:391 *ABS*:400153dc TIM20_DCR
|
|
G431_addr.s:392 *ABS*:400153e0 TIM20_DMAR
|
|
G431_addr.s:396 *ABS*:40014000 TIM15_BASE
|
|
G431_addr.s:398 *ABS*:40014000 TIM15_CR1
|
|
G431_addr.s:399 *ABS*:40014004 TIM15_CR2
|
|
G431_addr.s:400 *ABS*:40014008 TIM15_SMCR
|
|
G431_addr.s:401 *ABS*:4001400c TIM15_DIER
|
|
G431_addr.s:402 *ABS*:40014010 TIM15_SR
|
|
G431_addr.s:403 *ABS*:40014014 TIM15_EGR
|
|
G431_addr.s:404 *ABS*:40014018 TIM15_CCMR1
|
|
G431_addr.s:406 *ABS*:40014020 TIM15_CCER
|
|
G431_addr.s:407 *ABS*:40014024 TIM15_CNT
|
|
G431_addr.s:408 *ABS*:40014028 TIM15_PSC
|
|
G431_addr.s:409 *ABS*:4001402c TIM15_ARR
|
|
G431_addr.s:410 *ABS*:40014030 TIM15_RCR
|
|
G431_addr.s:411 *ABS*:40014034 TIM15_CCR1
|
|
G431_addr.s:412 *ABS*:40014038 TIM15_CCR2
|
|
G431_addr.s:414 *ABS*:40014044 TIM15_BDTR
|
|
G431_addr.s:416 *ABS*:40014054 TIM15_DTR2
|
|
G431_addr.s:418 *ABS*:4001405c TIM15_TISEL
|
|
G431_addr.s:419 *ABS*:40014060 TIM15_AF1
|
|
G431_addr.s:420 *ABS*:40014064 TIM15_AF2
|
|
G431_addr.s:422 *ABS*:400143dc TIM15_DCR
|
|
G431_addr.s:423 *ABS*:400143e0 TIM15_DMAR
|
|
G431_addr.s:427 *ABS*:40014400 TIM16_BASE
|
|
G431_addr.s:429 *ABS*:40014400 TIM16_CR1
|
|
G431_addr.s:430 *ABS*:40014404 TIM16_CR2
|
|
G431_addr.s:432 *ABS*:4001440c TIM16_DIER
|
|
G431_addr.s:433 *ABS*:40014410 TIM16_SR
|
|
G431_addr.s:434 *ABS*:40014414 TIM16_EGR
|
|
G431_addr.s:435 *ABS*:40014418 TIM16_CCMR1
|
|
G431_addr.s:437 *ABS*:40014420 TIM16_CCER
|
|
G431_addr.s:438 *ABS*:40014424 TIM16_CNT
|
|
G431_addr.s:439 *ABS*:40014428 TIM16_PSC
|
|
G431_addr.s:440 *ABS*:4001442c TIM16_ARR
|
|
G431_addr.s:441 *ABS*:40014430 TIM16_RCR
|
|
G431_addr.s:442 *ABS*:40014434 TIM16_CCR1
|
|
G431_addr.s:444 *ABS*:40014444 TIM16_BDTR
|
|
G431_addr.s:446 *ABS*:40014454 TIM16_DTR2
|
|
G431_addr.s:448 *ABS*:4001445c TIM16_TISEL
|
|
G431_addr.s:449 *ABS*:40014460 TIM16_AF1
|
|
G431_addr.s:450 *ABS*:40014464 TIM16_AF2
|
|
G431_addr.s:451 *ABS*:40014468 TIM16_OR1
|
|
G431_addr.s:453 *ABS*:400147dc TIM16_DCR
|
|
G431_addr.s:454 *ABS*:400147e0 TIM16_DMAR
|
|
G431_addr.s:458 *ABS*:40014800 TIM17_BASE
|
|
G431_addr.s:460 *ABS*:40014800 TIM17_CR1
|
|
G431_addr.s:461 *ABS*:40014804 TIM17_CR2
|
|
G431_addr.s:463 *ABS*:4001480c TIM17_DIER
|
|
G431_addr.s:464 *ABS*:40014810 TIM17_SR
|
|
G431_addr.s:465 *ABS*:40014814 TIM17_EGR
|
|
G431_addr.s:466 *ABS*:40014818 TIM17_CCMR1
|
|
G431_addr.s:468 *ABS*:40014820 TIM17_CCER
|
|
G431_addr.s:469 *ABS*:40014824 TIM17_CNT
|
|
G431_addr.s:470 *ABS*:40014828 TIM17_PSC
|
|
G431_addr.s:471 *ABS*:4001482c TIM17_ARR
|
|
G431_addr.s:472 *ABS*:40014830 TIM17_RCR
|
|
G431_addr.s:473 *ABS*:40014834 TIM17_CCR1
|
|
G431_addr.s:475 *ABS*:40014844 TIM17_BDTR
|
|
G431_addr.s:477 *ABS*:40014854 TIM17_DTR2
|
|
G431_addr.s:479 *ABS*:4001485c TIM17_TISEL
|
|
G431_addr.s:480 *ABS*:40014860 TIM17_AF1
|
|
G431_addr.s:481 *ABS*:40014864 TIM17_AF2
|
|
G431_addr.s:482 *ABS*:40014868 TIM17_OR1
|
|
G431_addr.s:484 *ABS*:40014bdc TIM17_DCR
|
|
G431_addr.s:485 *ABS*:40014be0 TIM17_DMAR
|
|
G431_addr.s:493 *ABS*:40021000 RCC_BASE
|
|
G431_addr.s:495 *ABS*:40021000 RCC_CR
|
|
G431_addr.s:496 *ABS*:40021004 RCC_ICSCR
|
|
G431_addr.s:497 *ABS*:40021008 RCC_CFGR
|
|
G431_addr.s:498 *ABS*:4002100c RCC_PLLCFGR
|
|
G431_addr.s:500 *ABS*:40021018 RCC_CIER
|
|
G431_addr.s:501 *ABS*:4002101c RCC_CIFR
|
|
G431_addr.s:502 *ABS*:40021020 RCC_CICR
|
|
G431_addr.s:504 *ABS*:40021028 RCC_AHB1RSTR
|
|
G431_addr.s:505 *ABS*:4002102c RCC_AHB2RSTR
|
|
G431_addr.s:506 *ABS*:40021030 RCC_AHB3RSTR
|
|
G431_addr.s:508 *ABS*:40021038 RCC_APB1RSTR1
|
|
G431_addr.s:509 *ABS*:4002103c RCC_APB1RSTR2
|
|
G431_addr.s:510 *ABS*:40021040 RCC_APB2RSTR
|
|
G431_addr.s:512 *ABS*:40021048 RCC_AHB1ENR
|
|
G431_addr.s:513 *ABS*:4002104c RCC_AHB2ENR
|
|
G431_addr.s:514 *ABS*:40021050 RCC_AHB3ENR
|
|
G431_addr.s:516 *ABS*:40021058 RCC_APB1ENR1
|
|
G431_addr.s:517 *ABS*:4002105c RCC_APB1ENR2
|
|
G431_addr.s:518 *ABS*:40021060 RCC_APB2ENR
|
|
G431_addr.s:520 *ABS*:40021068 RCC_AHB1SMENR
|
|
G431_addr.s:521 *ABS*:4002106c RCC_AHB2SMENR
|
|
G431_addr.s:522 *ABS*:40021070 RCC_AHB3SMENR
|
|
G431_addr.s:524 *ABS*:40021078 RCC_APB1SMENR1
|
|
G431_addr.s:525 *ABS*:4002107c RCC_APB1SMENR2
|
|
G431_addr.s:526 *ABS*:40021080 RCC_APB2SMENR
|
|
G431_addr.s:528 *ABS*:40021088 RCC_CCIPR
|
|
G431_addr.s:530 *ABS*:40021090 RCC_BDCR
|
|
G431_addr.s:531 *ABS*:40021094 RCC_CSR
|
|
G431_addr.s:532 *ABS*:40021098 RCC_CRRCR
|
|
G431_addr.s:533 *ABS*:4002109c RCC_CCIPR2
|
|
G431_addr.s:541 *ABS*:48000000 GPIO_BASE
|
|
G431_addr.s:543 *ABS*:00000000 GPIO_MODER_OFFSET
|
|
G431_addr.s:544 *ABS*:00000004 GPIO_OTYPER_OFFSET
|
|
G431_addr.s:545 *ABS*:00000008 GPIO_OSPEEDR_OFFSET
|
|
G431_addr.s:546 *ABS*:0000000c GPIO_PUPDR_OFFSET
|
|
G431_addr.s:547 *ABS*:00000010 GPIO_IDR_OFFSET
|
|
G431_addr.s:548 *ABS*:00000014 GPIO_ODR_OFFSET
|
|
G431_addr.s:549 *ABS*:00000018 GPIO_BSRR_OFFSET
|
|
G431_addr.s:550 *ABS*:0000001c GPIO_LCKR_OFFSET
|
|
G431_addr.s:551 *ABS*:00000020 GPIO_AFRL_OFFSET
|
|
G431_addr.s:552 *ABS*:00000024 GPIO_AFRH_OFFSET
|
|
G431_addr.s:553 *ABS*:00000028 GPIO_BRR_OFFSET
|
|
G431_addr.s:559 *ABS*:48000000 GPIOA_BASE
|
|
G431_addr.s:561 *ABS*:48000000 GPIOA_MODER
|
|
G431_addr.s:562 *ABS*:48000004 GPIOA_OTYPER
|
|
G431_addr.s:563 *ABS*:48000008 GPIOA_OSPEEDR
|
|
G431_addr.s:564 *ABS*:4800000c GPIOA_PUPDR
|
|
G431_addr.s:565 *ABS*:48000010 GPIOA_IDR
|
|
G431_addr.s:566 *ABS*:48000014 GPIOA_ODR
|
|
G431_addr.s:567 *ABS*:48000018 GPIOA_BSRR
|
|
G431_addr.s:568 *ABS*:4800001c GPIOA_LCKR
|
|
G431_addr.s:569 *ABS*:48000020 GPIOA_AFRL
|
|
G431_addr.s:570 *ABS*:48000024 GPIOA_AFRH
|
|
G431_addr.s:571 *ABS*:48000028 GPIOA_BRR
|
|
G431_addr.s:575 *ABS*:48000400 GPIOB_BASE
|
|
G431_addr.s:577 *ABS*:48000400 GPIOB_MODER
|
|
G431_addr.s:578 *ABS*:48000404 GPIOB_OTYPER
|
|
G431_addr.s:579 *ABS*:48000408 GPIOB_OSPEEDR
|
|
G431_addr.s:580 *ABS*:4800040c GPIOB_PUPDR
|
|
G431_addr.s:581 *ABS*:48000410 GPIOB_IDR
|
|
G431_addr.s:582 *ABS*:48000414 GPIOB_ODR
|
|
G431_addr.s:583 *ABS*:48000418 GPIOB_BSRR
|
|
G431_addr.s:584 *ABS*:4800041c GPIOB_LCKR
|
|
G431_addr.s:585 *ABS*:48000420 GPIOB_AFRL
|
|
G431_addr.s:586 *ABS*:48000424 GPIOB_AFRH
|
|
G431_addr.s:587 *ABS*:48000428 GPIOB_BRR
|
|
G431_addr.s:591 *ABS*:48000800 GPIOC_BASE
|
|
G431_addr.s:593 *ABS*:48000800 GPIOC_MODER
|
|
G431_addr.s:594 *ABS*:48000804 GPIOC_OTYPER
|
|
G431_addr.s:595 *ABS*:48000808 GPIOC_OSPEEDR
|
|
G431_addr.s:596 *ABS*:4800080c GPIOC_PUPDR
|
|
G431_addr.s:597 *ABS*:48000810 GPIOC_IDR
|
|
G431_addr.s:598 *ABS*:48000814 GPIOC_ODR
|
|
G431_addr.s:599 *ABS*:48000818 GPIOC_BSRR
|
|
G431_addr.s:600 *ABS*:4800081c GPIOC_LCKR
|
|
G431_addr.s:601 *ABS*:48000820 GPIOC_AFRL
|
|
G431_addr.s:602 *ABS*:48000824 GPIOC_AFRH
|
|
G431_addr.s:603 *ABS*:48000828 GPIOC_BRR
|
|
G431_addr.s:607 *ABS*:48000c00 GPIOD_BASE
|
|
G431_addr.s:609 *ABS*:48000c00 GPIOD_MODER
|
|
G431_addr.s:610 *ABS*:48000c04 GPIOD_OTYPER
|
|
G431_addr.s:611 *ABS*:48000c08 GPIOD_OSPEEDR
|
|
G431_addr.s:612 *ABS*:48000c0c GPIOD_PUPDR
|
|
G431_addr.s:613 *ABS*:48000c10 GPIOD_IDR
|
|
G431_addr.s:614 *ABS*:48000c14 GPIOD_ODR
|
|
G431_addr.s:615 *ABS*:48000c18 GPIOD_BSRR
|
|
G431_addr.s:616 *ABS*:48000c1c GPIOD_LCKR
|
|
G431_addr.s:617 *ABS*:48000c20 GPIOD_AFRL
|
|
G431_addr.s:618 *ABS*:48000c24 GPIOD_AFRH
|
|
G431_addr.s:619 *ABS*:48000c28 GPIOD_BRR
|
|
G431_addr.s:623 *ABS*:48001000 GPIOE_BASE
|
|
G431_addr.s:625 *ABS*:48001000 GPIOE_MODER
|
|
G431_addr.s:626 *ABS*:48001004 GPIOE_OTYPER
|
|
G431_addr.s:627 *ABS*:48001008 GPIOE_OSPEEDR
|
|
G431_addr.s:628 *ABS*:4800100c GPIOE_PUPDR
|
|
G431_addr.s:629 *ABS*:48001010 GPIOE_IDR
|
|
G431_addr.s:630 *ABS*:48001014 GPIOE_ODR
|
|
G431_addr.s:631 *ABS*:48001018 GPIOE_BSRR
|
|
G431_addr.s:632 *ABS*:4800101c GPIOE_LCKR
|
|
G431_addr.s:633 *ABS*:48001020 GPIOE_AFRL
|
|
G431_addr.s:634 *ABS*:48001024 GPIOE_AFRH
|
|
G431_addr.s:635 *ABS*:48001028 GPIOE_BRR
|
|
G431_addr.s:639 *ABS*:48001400 GPIOF_BASE
|
|
G431_addr.s:641 *ABS*:48001400 GPIOF_MODER
|
|
G431_addr.s:642 *ABS*:48001404 GPIOF_OTYPER
|
|
G431_addr.s:643 *ABS*:48001408 GPIOF_OSPEEDR
|
|
G431_addr.s:644 *ABS*:4800140c GPIOF_PUPDR
|
|
G431_addr.s:645 *ABS*:48001410 GPIOF_IDR
|
|
G431_addr.s:646 *ABS*:48001414 GPIOF_ODR
|
|
G431_addr.s:647 *ABS*:48001418 GPIOF_BSRR
|
|
G431_addr.s:648 *ABS*:4800141c GPIOF_LCKR
|
|
G431_addr.s:649 *ABS*:48001420 GPIOF_AFRL
|
|
G431_addr.s:650 *ABS*:48001424 GPIOF_AFRH
|
|
G431_addr.s:651 *ABS*:48001428 GPIOF_BRR
|
|
G431_addr.s:655 *ABS*:48001800 GPIOG_BASE
|
|
G431_addr.s:657 *ABS*:48001800 GPIOG_MODER
|
|
G431_addr.s:658 *ABS*:48001804 GPIOG_OTYPER
|
|
G431_addr.s:659 *ABS*:48001808 GPIOG_OSPEEDR
|
|
G431_addr.s:660 *ABS*:4800180c GPIOG_PUPDR
|
|
G431_addr.s:661 *ABS*:48001810 GPIOG_IDR
|
|
G431_addr.s:662 *ABS*:48001814 GPIOG_ODR
|
|
G431_addr.s:663 *ABS*:48001818 GPIOG_BSRR
|
|
G431_addr.s:664 *ABS*:4800181c GPIOG_LCKR
|
|
G431_addr.s:665 *ABS*:48001820 GPIOG_AFRL
|
|
G431_addr.s:666 *ABS*:48001824 GPIOG_AFRH
|
|
G431_addr.s:667 *ABS*:48001828 GPIOG_BRR
|
|
G431_addr.s:675 *ABS*:e000e000 SCS_BASE
|
|
G431_addr.s:683 *ABS*:e000e00a STK_BASE
|
|
G431_addr.s:685 *ABS*:e000e000 STK_CTRL
|
|
G431_addr.s:686 *ABS*:e000e004 STK_LOAD
|
|
G431_addr.s:687 *ABS*:e000e008 STK_VAL
|
|
G431_addr.s:688 *ABS*:e000e00c STK_CALIB
|
|
G431_addr.s:696 *ABS*:e000e100 NVIC_BASE
|
|
G431_addr.s:698 *ABS*:e000e100 NVIC_ISER0
|
|
G431_addr.s:699 *ABS*:e000e104 NVIC_ISER1
|
|
G431_addr.s:700 *ABS*:e000e108 NVIC_ISER2
|
|
G431_addr.s:701 *ABS*:e000e10c NVIC_ISER3
|
|
G431_addr.s:703 *ABS*:e000e180 NVIC_ICER0
|
|
G431_addr.s:704 *ABS*:e000e184 NVIC_ICER1
|
|
G431_addr.s:705 *ABS*:e000e188 NVIC_ICER2
|
|
G431_addr.s:706 *ABS*:e000e18c NVIC_ICER3
|
|
G431_addr.s:708 *ABS*:e000e200 NVIC_ISPR0
|
|
G431_addr.s:709 *ABS*:e000e204 NVIC_ISPR1
|
|
G431_addr.s:710 *ABS*:e000e208 NVIC_ISPR2
|
|
G431_addr.s:711 *ABS*:e000e20c NVIC_ISPR3
|
|
G431_addr.s:713 *ABS*:e000e280 NVIC_ICPR0
|
|
G431_addr.s:714 *ABS*:e000e284 NVIC_ICPR1
|
|
G431_addr.s:715 *ABS*:e000e288 NVIC_ICPR2
|
|
G431_addr.s:716 *ABS*:e000e28c NVIC_ICPR3
|
|
G431_addr.s:718 *ABS*:e000e300 NVIC_IABR0
|
|
G431_addr.s:719 *ABS*:e000e304 NVIC_IABR1
|
|
G431_addr.s:720 *ABS*:e000e308 NVIC_IABR2
|
|
G431_addr.s:721 *ABS*:e000e30c NVIC_IABR3
|
|
G431_addr.s:723 *ABS*:e000e400 NVIC_IPR0
|
|
G431_addr.s:724 *ABS*:e000e404 NVIC_IPR1
|
|
G431_addr.s:725 *ABS*:e000e408 NVIC_IPR2
|
|
G431_addr.s:726 *ABS*:e000e40c NVIC_IPR3
|
|
G431_addr.s:727 *ABS*:e000e410 NVIC_IPR4
|
|
G431_addr.s:728 *ABS*:e000e414 NVIC_IPR5
|
|
G431_addr.s:729 *ABS*:e000e418 NVIC_IPR6
|
|
G431_addr.s:730 *ABS*:e000e41c NVIC_IPR7
|
|
G431_addr.s:731 *ABS*:e000e420 NVIC_IPR8
|
|
G431_addr.s:732 *ABS*:e000e424 NVIC_IPR9
|
|
G431_addr.s:733 *ABS*:e000e428 NVIC_IPR10
|
|
G431_addr.s:734 *ABS*:e000e42c NVIC_IPR11
|
|
G431_addr.s:735 *ABS*:e000e430 NVIC_IPR12
|
|
G431_addr.s:736 *ABS*:e000e434 NVIC_IPR13
|
|
G431_addr.s:737 *ABS*:e000e438 NVIC_IPR14
|
|
G431_addr.s:738 *ABS*:e000e43c NVIC_IPR15
|
|
G431_addr.s:739 *ABS*:e000e440 NVIC_IPR16
|
|
G431_addr.s:740 *ABS*:e000e444 NVIC_IPR17
|
|
G431_addr.s:741 *ABS*:e000e448 NVIC_IPR18
|
|
G431_addr.s:742 *ABS*:e000e44c NVIC_IPR19
|
|
G431_addr.s:743 *ABS*:e000e450 NVIC_IPR20
|
|
G431_addr.s:744 *ABS*:e000e454 NVIC_IPR21
|
|
G431_addr.s:745 *ABS*:e000e458 NVIC_IPR22
|
|
G431_addr.s:746 *ABS*:e000e45c NVIC_IPR23
|
|
G431_addr.s:747 *ABS*:e000e460 NVIC_IPR24
|
|
G431_addr.s:748 *ABS*:e000e464 NVIC_IPR25
|
|
G431_addr.s:750 *ABS*:e000ef00 STIR
|
|
G431_addr.s:758 *ABS*:e0042000 DBGMCU_BASE
|
|
G431_addr.s:760 *ABS*:e0042000 DBGMCU_IDCODE
|
|
G431_addr.s:761 *ABS*:e0042004 DBGMCU_CR
|
|
G431_addr.s:762 *ABS*:e0042008 DBGMCU_APB1FZR1
|
|
G431_addr.s:763 *ABS*:e004200c DBGMCU_APB1FZR2
|
|
G431_addr.s:764 *ABS*:e0042010 DBGMCU_APB2DZR
|
|
task2.s:48 .vectortable:00000000 $d
|
|
task2.s:215 .exhand:00000000 _ISR_NMI
|
|
task2.s:248 .exhand:00000028 _ISR_HARDF
|
|
task2.s:281 .exhand:00000050 _ISR_S0
|
|
task2.s:69 .text:00000000 $t
|
|
task2.s:75 .text:00000000 init
|
|
task2.s:160 .text:00000044 main
|
|
task2.s:182 .text:00000054 delay
|
|
task2.s:196 .text:00000060 stop
|
|
task2.s:202 .text:00000066 .lp1
|
|
task2.s:203 .text:00000066 $d
|
|
task2.s:203 .text:00000068 $d
|
|
task2.s:211 .exhand:00000000 $t
|
|
task2.s:301 .exhand:00000058 _ISR_S1
|
|
task2.s:319 .exhand:0000005e .lp2
|
|
task2.s:320 .exhand:0000005e $d
|
|
task2.s:320 .exhand:00000060 $d
|
|
|
|
NO UNDEFINED SYMBOLS
|