//  *********************************************************************************************
//  Project Version  : v1.0
//  Project          : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
//  -----
//  Copyright (c)    : 2025 Fraunhofer IIS, Department IDS
//  Created          : 12.Jun.2025  by Lund University [commit 5b1e415]
//  Last Modified    : 23.Oct.2025  by Bomin Kim       [commit 2f8f03d]
//  -----
//  HISTORY          : Date         By         Comments
//                     -----------  ---------  -------------------------------------------------
//                     15.Oct.2025  Bomin Kim  Added reset handling condition
//  *********************************************************************************************


module reg_file (
  input  logic[4:0]  Rs1,
  input  logic[4:0]  Rs2,
  input  logic[4:0]  Rd,
  output logic[31:0] RRs1,
  output logic[31:0] RRs2,
  input  logic[31:0] WRd,
  input  logic       WrReg,
  input  logic       reset,
  input  logic       clk
);

  // Define the registers array
  logic[31:0] registers[31:1];

  // Register file reading
  assign RRs1 = Rs1 == 0 ? '0 : registers[Rs1];
  assign RRs2 = Rs2 == 0 ? '0 : registers[Rs2];

  // Register file writing
  always_ff @(posedge clk) begin
    if (reset) begin
      for (int i=1; i<32; i++)
          registers[i] <= '0;
    end else begin
      if (WrReg & Rd != 0) registers[Rd] <= WRd;
    end
  end

endmodule
