module MemGen_32_11 #(
    parameter data_width	=	32,
    parameter addr_width	=	11,
    parameter mem_depth	 	=	2048
)(
    input                  chip_en,
    input                  clock,
    input  [addr_width-1:0]addr,
    output reg [data_width-1:0]rd_data,
    input                  rd_en,
      
    input                  wr_en,
    input  [data_width-1:0]wr_data    
);
// Bank selection: 1 bit selects one of 2 banks
      reg  [1:0] mem_sel ;
      wire [31:0] mem_data_out [1:0];

// Address decoder and output multiplexer
always @(*)
    begin
        if ( chip_en == 1'b1 )
            case (addr[10])
                1'b0 : begin mem_sel = 2'b01; rd_data = mem_data_out[0]; end
                1'b1 : begin mem_sel = 2'b10; rd_data = mem_data_out[1]; end
            endcase
        else
            begin
                mem_sel =  2'b00; 
                rd_data = 32'h00000000;   
            end
    end


genvar i;
// Instantiate 2 banks, each with 2 halves (low + high 16 bits)
generate
    for (i = 0; i < 2; i = i + 1) begin
        MemGen_16_10 U_lo (
		.chip_en(mem_sel[i]), 
		.clock(clock), 
		.addr(addr[9:0]), 
		.rd_en(rd_en), 
		.rd_data(mem_data_out[i][15:0]),  
		.wr_en(wr_en), 
		.wr_data(wr_data[15:0]) 
	);
        MemGen_16_10 U_hi (
		.chip_en(mem_sel[i]), 
		.clock(clock), 
		.addr(addr[9:0]), 
		.rd_en(rd_en), 
		.rd_data(mem_data_out[i][31:16]), 
		.wr_en(wr_en), 
		.wr_data(wr_data[31:16]) 
	);
    end
endgenerate

endmodule
