//  *********************************************************************************************
//  Project Version  : v1.0
//  Project          : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
//  -----
//  Copyright (c)    : 2025 Fraunhofer IIS, Department IDS
//  Created          : 12.Aug.2025  by Marcus Bednara
//  Last Modified    : 01.Nov.2025  by Hussein Elzomor
//  ------
//  Notes            : All ${}-variables must be provided by shell or Makefile {using export}
//  *********************************************************************************************



${PRJ_ROOT}/hw/rtl/pc.sv
${PRJ_ROOT}/hw/rtl/reg_file.sv
${PRJ_ROOT}/hw/rtl/alu.sv
${PRJ_ROOT}/hw/rtl/main_mem.sv
${PRJ_ROOT}/hw/rtl/decoder.sv
${PRJ_ROOT}/hw/rtl/cpu.sv
