RISC_V_LAB hinzugefügt
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muellerlu
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// *********************************************************************************************
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// Description : Verilator simulation harness
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 12.Aug.2025 by Marcus Bednara
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// Last Modified : 15.Oct.2025 by Hussein Elzomor [commit d0452cd]
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// 15.Oct.2025 H.Elzomor Renamed file and module from soc_harness to cpu_harness
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// 15.Oct.2025 H.Elzomor Added getMem function, setMem task and printMem task
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// *********************************************************************************************
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timeunit 1ps;
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timeprecision 1ps;
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module cpu_harness;
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// local signals
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logic clk,
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rst;
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logic [7:0] led;
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logic [6:0] btn;
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// toplevel instance (DUT)
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cpu u_cpu (
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.led (led),
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.btn ({btn[6:1], rst}),
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.clk_25mhz (clk)
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); // u_cpu
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`ifdef VERILATOR
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// Declare all functions with DPI-C interface to make them accessible from the C++ testbench
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export "DPI-C" task setClk;
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export "DPI-C" task enable;
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export "DPI-C" task loadRAM;
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// export "DPI-C" task dumpSRAM;
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export "DPI-C" task setInitial;
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export "DPI-C" function getLed;
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export "DPI-C" task setBtn;
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export "DPI-C" task setReset;
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export "DPI-C" function getMem;
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export "DPI-C" task setMem;
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export "DPI-C" task printMem;
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export "DPI-C" function getReg;
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export "DPI-C" task printReg;
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// Clocking is controlled from C++ testbench
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task setClk (input logic val);
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clk = val;
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endtask: setClk
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`else
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// If not using verilator, generate clock here
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const realtime clk_PERIOD = 1.0ns;
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initial begin: clock_driver
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clk = '1;
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forever begin
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#(clk_PERIOD/2.0);
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clk <= ~clk;
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end
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end: clock_driver
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task wait_clk_cycles(int unsigned n);
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repeat(n) @(posedge clk);
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endtask
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`endif
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// Remaining tasks are identical for Verilator and other simulators
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task loadRAM (input string fileName);
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$display ("Initializing SRAM memory from %s", fileName);
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$readmemh(fileName, u_cpu.theMem.RAM);
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endtask: loadRAM
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/* Some helper stuff */
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task enable(int val);
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// nothing to do, we have no fetch enable in this design
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endtask: enable
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task setInitial();
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btn = 7'b0;
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rst = 'b0;
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endtask: setInitial
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function int getLed;
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getLed = {24'b0, led};
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endfunction: getLed
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task setBtn(int val);
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btn[6:1] = val[5:0];
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endtask: setBtn
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task setReset (input int val);
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rst = (val==1);
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endtask: setReset
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function int getMem(int location);
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getMem = u_cpu.theMem.RAM[location];
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endfunction: getMem
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task setMem(int location, int value);
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u_cpu.theMem.RAM[location] = value;
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endtask: setMem
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task printMem (int location, string prog);
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case (prog)
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"fibonacci" :$display("Value at RAM[%0d]: 0x%h : %0d", location, getMem(location), getMem(location));
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"helloWorld" :$display("Value at RAM[%0d]: 0x%h : %s" , location, getMem(location), getMem(location));
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default :$display("Value at RAM[%0d]: 0x%h : %0d", location, getMem(location), getMem(location));
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endcase
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endtask: printMem
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function int getReg(int location);
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getReg = u_cpu.theRegisters.registers[location];
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endfunction: getReg
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task printReg (int location, string prog);
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case (prog)
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"primeNumber" :$display("Time =%5dns \t : Register [%0d] updated - Finding the prime factors of %0d", $time, location, getReg(location));
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"primeFactors":$display("Time =%5dns \t : Register [%0d] updated - %0d is a prime factor", $time, location, getReg(location));
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default :$display("Time =%5dns \t : Value at Reg[%0d]: 0x%h", $time, location, getReg(location));
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endcase
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endtask: printReg
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endmodule: cpu_harness
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@@ -0,0 +1,173 @@
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// *********************************************************************************************
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// Description : Verilator simulation harness
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 15.Oct.2025 by Hussein Elzomor
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// Last Modified : 15.Oct.2025 by Hussein Elzomor
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// *********************************************************************************************
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timeunit 1ps;
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timeprecision 1ps;
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module decoder_harness;
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// local Parameters
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localparam MEM_SIZE = 37;
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localparam REG_FILE_SIZE = 32;
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// local signals
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logic clk;
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int counter;
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logic[31:0] mem [MEM_SIZE-1:0];
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logic[31:0] regFile [REG_FILE_SIZE-1:0];
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// PC
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logic[31:0] CurrentPC;
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logic[31:0] JumpOrBranchPC;
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logic JumpOrBranch;
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logic[31:0] NextPC;
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// Memory
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logic[31:0] DAddr;
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logic[31:0] WData;
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logic[31:0] RData;
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logic[31:0] Instruction;
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logic WrMem;
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logic[1:0] DWidth;
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// Register File;
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logic[4:0] Rs1;
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logic[4:0] Rs2;
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logic[4:0] Rd;
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logic[31:0] RRs1;
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logic[31:0] RRs2;
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logic[31:0] WRd;
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logic WrReg;
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// Protection
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logic Illegal;
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// toplevel instance (DUT)
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decoder u_decoder (
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// PC
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.CurrentPC(CurrentPC),
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.JumpOrBranchPC(JumpOrBranchPC),
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.JumpOrBranch(JumpOrBranch),
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// Memory
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.DAddr(DAddr),
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.WData(WData),
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.RData(RData),
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.Instruction(Instruction),
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.WrMem(WrMem),
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.DWidth(DWidth),
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// Register File
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.Rs1(Rs1),
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.Rs2(Rs2),
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.Rd(Rd),
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.RRs1(RRs1),
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.RRs2(RRs2),
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.WRd(WRd),
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.WrReg(WrReg),
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// Protection
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.Illegal(Illegal)
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); // u_decoder
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// Special Verilator specific tasks
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`ifdef VERILATOR
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// Declare all functions with DPI-C interface to make them accessible from the C++ testbench
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// Setters
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export "DPI-C" task setClk;
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export "DPI-C" task enable;
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export "DPI-C" task loadRAM;
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export "DPI-C" task setInitial;
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export "DPI-C" task printInfo;
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// Clocking is controlled from C++ testbench
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task setClk (input logic val);
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clk = val;
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endtask: setClk
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`else
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// If not using verilator, generate clock here
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const realtime clk_PERIOD = 1.0ns;
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initial begin: clock_driver
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clk = '1;
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forever begin
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#(clk_PERIOD/2.0);
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clk <= ~clk;
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end
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end: clock_driver
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task wait_clk_cycles(int unsigned n);
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repeat(n) @(posedge clk);
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endtask
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`endif
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// Load a new instruction every cycle
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always_ff @(posedge clk) begin: increment_instruction_and_print_info
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if (counter < MEM_SIZE) begin
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if (counter > 0) printInfo();
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Instruction = mem[counter++];
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end
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end
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// Return the value of the RegFile
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always_comb begin: reg_file_assignment
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RRs1 = regFile[Rs1];
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RRs2 = regFile[Rs2];
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end
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// Remaining tasks are identical for Verilator and other simulators
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task enable(int val);
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// nothing to do, we have no fetch enable in this design
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endtask: enable
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// Load data into memory
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task loadRAM (input string fileName);
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$display ("Initializing SRAM memory from %s", fileName);
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$readmemh(fileName, mem);
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endtask: loadRAM
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// Set initial values
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task setInitial();
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Instruction = mem[0];
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counter = 0;
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CurrentPC = 32'hdeadbeef;
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RData = 32'hbeefdead;
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for(int i=0; i<REG_FILE_SIZE; i++) begin
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regFile[i] = i;
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end
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endtask: setInitial
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// Print decoder signals
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task printInfo();
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$displayh("(cycle %0d) Decoder (I/O) \tDecoder (Internal Signals) \tALU" , counter );
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$displayh(" -------------------------- \t--------------------------------------------- \t---------------------" , );
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$displayh(" CurrentPC : 0x%h OpCode : 0b%b aluOp : 0b%b" , CurrentPC , u_decoder.theOp , u_decoder.aluOp );
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$displayh(" JumpOrBranchPC: 0x%h theFunct3: 0b%b aluNegAr : 0b%b", JumpOrBranchPC, u_decoder.theFunct3, u_decoder.aluNegAr );
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$displayh(" JumpOrBranch : 0b%b \ttheFunct7: 0b%b aluBypass: 0b%b", JumpOrBranch , u_decoder.theFunct7, u_decoder.aluBypass);
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$displayh(" DAddr : 0x%h i_imm : 0b%b op1 : 0x%h" , DAddr , u_decoder.i_imm , u_decoder.op1 );
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$displayh(" WData : 0x%h s_imm : 0b%b op2 : 0x%h" , WData , u_decoder.s_imm , u_decoder.op2 );
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$displayh(" RData : 0x%h b_imm : 0b%b result : 0x%h" , RData , u_decoder.b_imm , u_decoder.result );
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$displayh(" Instruction : 0x%h u_imm : 0b%b eqFlag : 0b%b" , Instruction , u_decoder.u_imm , u_decoder.eqFlag );
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$displayh(" WrMem : 0b%b \tj_imm : 0b%b" , WrMem , u_decoder.j_imm );
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$displayh(" DWidth : 0b%b" , DWidth );
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$displayh(" Rs1 : %0d " , Rs1 );
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$displayh(" Rs2 : %0d " , Rs2 );
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$displayh(" Rd : 0x%h" , Rd );
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$displayh(" RRs1 : %0d " , RRs1 );
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$displayh(" RRs2 : %0d " , RRs2 );
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$displayh(" WRd : 0x%h" , WRd );
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$displayh(" WrReg : 0b%b" , WrReg );
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$displayh(" Illegal : 0b%b" , Illegal );
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$displayh("");
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endtask: printInfo
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endmodule: decoder_harness
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