RISC_V_LAB hinzugefügt

riscv_rtl/hw/file_lists/rtl_flist.f

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+//  *********************************************************************************************
+//  Project Version  : v1.0
+//  Project          : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
+//  -----
+//  Copyright (c)    : 2025 Fraunhofer IIS, Department IDS
+//  Created          : 12.Aug.2025  by Marcus Bednara
+//  Last Modified    : 01.Nov.2025  by Hussein Elzomor
+//  ------
+//  Notes            : All ${}-variables must be provided by shell or Makefile {using export}
+//  *********************************************************************************************
+
+
+
+${PRJ_ROOT}/hw/rtl/pc.sv
+${PRJ_ROOT}/hw/rtl/reg_file.sv
+${PRJ_ROOT}/hw/rtl/alu.sv
+${PRJ_ROOT}/hw/rtl/main_mem.sv
+${PRJ_ROOT}/hw/rtl/decoder.sv
+${PRJ_ROOT}/hw/rtl/cpu.sv

riscv_rtl/hw/file_lists/tb_flist.f

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+//  *********************************************************************************************
+//  Project Version  : v1.0
+//  Project          : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
+//  -----
+//  Copyright (c)    : 2025 Fraunhofer IIS, Department IDS
+//  Created          : 12.Aug.2025  by Marcus Bednara
+//  Last Modified    : 01.Nov.2025  by Hussein Elzomor
+//  ------
+//  Notes            : All ${}-variables must be provided by shell or Makefile {using export}
+//  *********************************************************************************************
+
+
+
+// Used with verilator
+${PRJ_ROOT}/hw/dv/verilator/rtl/decoder_harness.sv
+${PRJ_ROOT}/hw/dv/verilator/rtl/cpu_harness.sv
+
+// Used with other compilers and simulators (eg. Icarus)
+// ${PRJ_ROOT}/hw/dv/rtl/pc_tb.sv
+// ${PRJ_ROOT}/hw/dv/rtl/reg_file_tb.sv
+// ${PRJ_ROOT}/hw/dv/rtl/alu_tb.sv
+// ${PRJ_ROOT}/hw/dv/rtl/main_mem_tb.sv
+// ${PRJ_ROOT}/hw/dv/rtl/decoder_tb.sv
+// ${PRJ_ROOT}/hw/dv/rtl/cpu_tb.sv