RISC_V_LAB hinzugefügt

2026-06-09 08:33:18 +02:00
commit 3c0ec38544
233 changed files with 90271 additions and 0 deletions
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+
+#########################################################
+#                 1_load_design.tcl
+#
+# Description:  Load the design input files into
+#               Oasys-RTL and set design
+#               conditions. Must be run after the
+#               init_design.tcl script
+#
+# Usage:        source in Oasys-RTL Command prompt
+#
+# Dependencies: init_design.tcl
+#               Launched from Oasys-RTL shell
+#
+#########################################################
+
+#set script_dir [file dirname [info script]]
+set script_dir "scripts_risc_v"
+set ekit_dir   [file dirname ${script_dir}]
+
+#Check if dependent scripts have been loaded
+if {![info exists top_module]} {
+  source ${script_dir}/init_design.tcl
+}
+
+#=======================================================#
+#Load technology libraries (Liberty and LEF)
+#=======================================================#
+
+# Read Oasys libraries (ODB)
+read_db ${ekit_dir}/libs/nangate_mvt.odb
+foreach vt [list hvt svt lvt] {
+  set vtUC [string toupper $vt]
+  set lib_cells(${vt}) [get_lib_cells *${vtUC}*]
+  if { [sizeof_collection $lib_cells(${vt})] > 0 } {
+    create_threshold_voltage_group ${vtUC} -lib_cells $lib_cells($vt)
+  }
+}
+
+
+#=====================================================================================#
+#1. Report the libraries and operating conditions
+#find the help files in Documents folder (oasys rtl command reference manual)
+#=====================================================================================#
+
+#insert your code here
+
+#=====================================================================================#
+#=====================================================================================#
+
+
+
+#Config the tolerance level for RTL parser for elobration
+
+config_tolerance -blackbox true -connection_mismatch true \
+        -missing_physical_library true \
+        -continue_on_error false
+
+#Read verilog design files
+
+if {[file exists ${ekit_dir}/riscv_rtl/hw/rtl/alu.sv]} {
+  read_verilog -sv $rtl_list  -include $search_path
+}
+
+#Set design-specific parameters before synthesis
+
+
+#Set the max routing layer (defined in 1_init_design.tcl)
+set_max_route_layer $max_route_layer  				
+
+#Reset dont_use property on all lib cells
+set_dont_use [get_lib_cell * ] false 				
+
+#Specify clock gating options
+#set_clock_gating_options -control_point before \
+	-minimum_bitwidth 4 -sequential_cell latch 			
+
+echo "\n-----------------------------"
+echo "\nDone preparing design for synthesis"
+echo "\n-----------------------------\n"
@@ -0,0 +1,98 @@
+
+#########################################################
+#                 2_synthesize_optimize.tcl
+#
+# Description:  Synthesize and optimize the 
+#               DEMO CHIP and generate
+#               the Oasys-RTL databases. 
+#
+# Usage:        source in Oasys-RTL Command prompt
+#
+# Dependencies: init_design.tcl
+#               1_read_design.tcl
+#               Launched from Oasys-RTL shell
+#
+#########################################################
+
+
+#Check Status of Flow and load prior scripts if needed
+set script_dir [file dirname [info script]]
+set ekit_dir   [file dirname ${script_dir}]
+
+#Check if dependent scripts have been loaded
+if {![info exists top_module]} {
+     source ${script_dir}/init_design.tcl
+     source ${script_dir}/1_read_design.tcl
+}
+
+
+#Synthesize the DEMO CHIP RTL core
+
+if {![file exists ${ekit_dir}/riscv_rtl/hw/rtl/pc.sv]} {
+  puts "ERROR: RTL source files from OpenCores.org were not found.\n"
+  puts "You can read a design database for a previously optimized design"
+  puts "by running the following command:\n"
+  puts "read_db ${ekit_dir}/demo_chip_rtl/demo_chip.odb\n\n"
+  return
+}
+
+#=====================================================================================#
+#1. Perform Synthesis
+#find the help files in Documents folder (Quick start to oasys)
+#=====================================================================================#
+
+#insert your code here to perform synthesis
+synthesize -module ${top_module} -map_to_scan -gate_clock
+
+#=====================================================================================#
+#=====================================================================================#
+
+set_route_layer_max_usage metal2 0.5
+set_route_layer_max_usage metal3 0.8
+set_route_layer_max_usage metal6 0.8
+
+write_db  ${output_dir}/odb/riscv_chip.syn.odb
+
+
+#Read constraints (logical and physical)
+read_sdc -verbose  ${ekit_dir}/constraints/riscv.sdc 
+
+# Create User Path groups
+group_path -name I2R -from [all_inputs]
+group_path -name I2O -from [all_inputs] -to [all_outputs]
+group_path -name R2O                    -to  [all_outputs]
+
+
+#=====================================================================================#
+#2. Perform Optimization for timing
+#find the help files in Documents folder (Quick start to oasys)
+#=====================================================================================#
+
+#insert your code here to perform optimization
+#what is the difference in slack with and without this optimization
+
+#=====================================================================================#
+#=====================================================================================#
+
+write_db  ${output_dir}/odb/riscv_chip.virtual_opt.odb
+
+#=================================================================#
+#3. Write the oasys commands to find the following:
+#Timing
+#Path groups
+#Design metrics
+#find the help files in Documents folder (Quick start to oasys)
+#================================================================#
+
+#Insert your code here
+
+#=====================================================================================#
+#=====================================================================================#
+
+
+
+echo "\n-------------------------------------"
+echo "\nSynthesis and optimization complete"
+echo "\n-------------------------------------\n"
+
+
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+
+#########################################################
+#                 2_synthesize_optimize.tcl
+#
+# Description:  Synthesize and optimize the 
+#               DEMO CHIP and generate
+#               the Oasys-RTL databases. 
+#
+# Usage:        source in Oasys-RTL Command prompt
+#
+# Dependencies: init_design.tcl
+#               1_read_design.tcl
+#               Launched from Oasys-RTL shell
+#
+#########################################################
+
+
+#=======================================================#
+#Check Status of Flow and load prior scripts if needed
+#=======================================================#
+set script_dir [file dirname [info script]]
+set ekit_dir   [file dirname ${script_dir}]
+
+#Check if dependent scripts have been loaded
+if {![info exists top_module]} {
+     source ${script_dir}/init_design.tcl
+     source ${script_dir}/1_read_design.tcl
+     source ${script_dir}/2_synthesize_optimize.tcl
+}
+
+#=======================================================#	
+#Perform DFT
+#=======================================================#
+if {[info exists dft_flow] && [string match $dft_flow tessent]} {
+  puts "INFO::Running oasys Tessent DFT flow"
+  source scripts_risc_v/oasys_tessent_dft.tcl
+  echo "\n-------------------------------------"
+  echo "\n Tessent DFT complete"
+  echo "\n-------------------------------------\n"
+} elseif {[info exists dft_flow] && [string match $dft_flow oasys]} {
+  puts "INFO::Running oasys native DFT flow"
+  source scripts/oasys_dft.tcl
+  report_scan_chains
+  echo "\n-------------------------------------"
+  echo "\n Oasys DFT complete"
+  echo "\n-------------------------------------\n"
+} else {
+  puts "\nINFO:: 'dft_flow'  variable not set to 'tessent' or 'oasys'."
+  puts "       skipping DFT flow. 'source' following script to run DFT"
+  puts "       source ${ekit_dir}/scripts/oasys_dft.tcl"
+  puts "       source ${ekit_dir}/scripts/oasys_tessent_dft.tcl"
+}
+
+#exit
@@ -0,0 +1,32 @@
+
+#########################################################
+#                  3_export_design.tcl
+#
+# Description:  Export the design data
+#
+# Usage:        source in Oasys-RTL Command prompt
+#
+# Dependencies: init_design.tcl
+#               1_load_design.tcl
+#               2_synthesize_optimize.tcl
+#               Launched from Oasys-RTL shell after
+#               synthesis and optimization
+#
+#########################################################
+
+#Check if dependent scripts have been loaded
+if {![info exists top_module]} {
+  source scripts/init_design.tcl
+}
+
+# Write results
+write_db      ${output_dir}/odb/demo_chip.oasys_final.odb
+write_verilog ${output_dir}/demo_chip.oasys_final.v
+write_sdc     ${output_dir}/demo_chip.oasys_final.sdc
+write_def     ${output_dir}/demo_chip.def
+write_stil    ${output_dir}/demo_chip.stil
+write_ctl     ${output_dir}/demo_chip.ctl
+
+echo "\n-----------------------------"
+echo "\nDesign data exported to output dir."
+echo "\n-----------------------------\n"
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+set_context patterns -scan
+
+set_tsdb_output_directory /users/projekte/projekt01/RISC-V_no_RAM-Macros/oasys.tessent.08/tsdb_outdir
+read_cell_library /users/projekte/projekt01/RISC-V_no_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib
+read_cell_library /users/projekte/projekt01/RISC-V_no_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib
+read_cell_library /users/projekte/projekt01/RISC-V_no_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib
+read_cell_library /users/projekte/projekt01/RISC-V_no_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib
+read_cell_library /users/projekte/projekt01/RISC-V_no_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib
+read_cell_library /users/projekte/projekt01/RISC-V_no_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib
+read_cell_library /users/projekte/projekt01/RISC-V_no_RAM-Macros/libs/fastscan/PLL.fslib
+read_cell_library /users/projekte/projekt01/RISC-V_no_RAM-Macros/libs/fastscan/IO.fslib
+
+read_design cpu -design_id Scan_0
+
+set_current_design cpu
+set_design_level physical_block
+
+# import_scan_mode reads the TCD which now includes clk12p5_reg/Q as TestClock
+import_scan_mode unwrapped
+
+# --- ADD THESE LINES HERE, before set_system_mode analysis ---
+add_input_constraints scan_mode -c1   ;# force scan_mode active during ATPG, this was not assumed on its own
+
+set_clock_off_simulation on
+
+set_system_mode analysis
+
+
+report_clocks
+report_drc_rules
+
+set_fault_type stuck
+
+add_faults -all
+
+create_patterns
+
+report_statistics
+report_faults -summary
+
+write_patterns cpu_patterns.stil         -stil    -replace
+write_patterns cpu_patterns_serial.v     -verilog -serial   -replace
+write_tsdb_data -replace
@@ -0,0 +1,37 @@
+###POWER PLANNING####
+##Make PG rails and stripes and connect macros to the power pins##
+
+create_supply_net -net_name VDD -power_net true 
+create_supply_net -net_name VSS -power_net false
+
+connect_supply_net VDD -pins [get_pins *vdd* ] 
+connect_supply_net VSS -pins [get_pins *gnd* ] 
+
+## Adding Power Structure
+remove_routing  -route_types pre_route
+
+create_pg_rings -partitions "demo_chip" -nets "VDD VSS" -window false -layers { metal9 metal10 } -widths { 45000a 50000a } -step 32000a -spacing 15000a -offset { 165000a 165000a 165000a 165000a } -keep_pattern all -bridge_pattern single -ignore_blockages { placement } -check_drc { all } -measure_from edge -corner_style concentric -insert_vias true -location auto
+
+create_pg_stripes -partitions "demo_chip" -nets "VDD VSS" -window false -layer metal10 -widths { 80000a 80000a } -step 500000a -spacing 20000a -direction vertical -offset { 500000a 500000a } -margin { 300000a 300000a } -measure_from center_line -keep_pattern false -ignore_blockages { placement } -check_drc { all }
+
+create_pg_stripes -partitions "demo_chip" -nets "VDD VSS" -window false -layer metal9 -widths { 80000a 80000a } -step 500000a -spacing 20000a -direction horizontal -offset { 500000a 500000a } -margin { 300000a 300000a } -measure_from center_line -keep_pattern false -ignore_blockages { placement } -check_drc { all }
+
+insert_pg_vias -nets {VDD VSS} -layers {metal9 metal10} -extend true -from_type stripe -to_type ring
+insert_pg_vias -nets {VDD VSS} -from_type stripe -to_type stripe -layers {metal9 metal10}
+
+create_pg_stripes -partitions "demo_chip" -nets "VDD VSS" -window false -layer metal4 -widths { 40000a 40000a } -step 500000a -spacing 20000a -direction vertical -offset { 800000a 800000a } -margin { 300000a 300000a } -measure_from center_line -keep_pattern false -ignore_blockages { placement } -check_drc { all }
+
+insert_pg_vias -nets {VDD VSS} -from_type stripe -to_type stripe -layers {metal9 metal4}  -extend true 
+insert_pg_vias -nets {VDD VSS} -from_type ring -to_type stripe -layers {metal9 metal4}  -extend true 
+
+create_pg_rails -partitions "demo_chip" -nets "VDD VSS" -window false -sites "FreePDK45_38x28_10R_NP_162NW_34O" -ignore_blockages { none }
+insert_pg_vias -from_type stripe -to_type rail -layers {metal1 metal4}
+
+insert_pg_vias -nets {VDD VSS} -layers {metal6 metal10} -from_type stripe -to_type macro_port
+insert_pg_vias -nets {VDD VSS} -layers {metal4 metal5} -from_type stripe -to_type macro_port 
+
+
+####################Check DRC####################
+check_drc  -only false 
+clean_drc -force
+check_drc -with_pre_route
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+####################################################Read_RTL###########################################
+
+set search_path "${demo_chip_rtl_dir}"
+
+set rtl_list { alu.sv
+cpu.sv
+decoder.sv 
+MemGen_32_11.sv
+main_mem.sv 
+pc.sv 
+reg_file.sv }
@@ -0,0 +1,38 @@
+#########################################################
+#                 dse_base.tcl
+#
+# Description:  Sets up the design for exploration
+#
+# Usage:        source in Oasys-RTL Command prompt
+#
+# Dependencies: init_design.tcl
+#########################################################
+
+#Initialize script parameters
+source scripts/init_design.tcl
+
+#Disable warning messages
+message -enable false TA-116
+message -enable false LIB-136
+message -enable false LIB-114
+message -enable false NL-138
+message -enable false NL-120
+
+source scripts/open_database.tcl
+###########################
+# If available, synthesize opencore files
+#   instead of the pre-optimized ODB file
+############################
+# read_verilog $rtl_list  -include $search_path
+# synthesize -module ${top_module} -map_to_scan -gate_clock
+# create_clock -period 2.50ns -name sysclk sysclk 
+# read_sdc -verbose $demo_chip_sdc_files
+
+#insert clk explorer here
+
+#Optimize
+optimize -virtual
+report_clocks
+report_power
+report_design_metrics
+
@@ -0,0 +1,45 @@
+#########################################################
+#                 dse_base.tcl
+#
+# Description:  Sets up the design for exploration
+#
+# Usage:        source in Oasys-RTL Command prompt
+#
+# Dependencies: init_design.tcl
+#########################################################
+
+#Initialize script parameters
+set_explore -variable clock_period \
+            -options { 2.00ns 2.25ns 2.50ns 2.75ns }
+
+source scripts/init_design.tcl
+
+#Disable warning messages
+message -enable false TA-116
+message -enable false LIB-136
+message -enable false LIB-114
+message -enable false NL-138
+message -enable false NL-120
+
+source scripts/open_database.tcl
+###########################
+# If available, synthesize opencore files
+#   instead of the pre-optimized ODB file
+############################
+# read_verilog $rtl_list  -include $search_path
+# synthesize -module ${top_module} -map_to_scan -gate_clock
+# create_clock -period 2.50ns -name sysclk sysclk 
+# read_sdc -verbose $demo_chip_sdc_files
+
+explore clock_period {
+  2.00ns { scale_clock -all -20 }
+  2.25ns { scale_clock -all -10 }
+  2.75ns { scale_clock -all 10 }
+}
+
+#Optimize
+optimize -virtual
+report_clocks
+report_power
+report_design_metrics
+
@@ -0,0 +1,44 @@
+set script_dir [file dirname [info script]]
+set ekit_dir   [file normalize [file dirname ${script_dir}]]
+set libs_dir   ${ekit_dir}/nangate/libs
+set lefs_dir   ${ekit_dir}/nangate/lefs
+puts "Base Dir: ${ekit_dir}"
+
+
+#set lib(io)  "${libs_dir}/lib_WCLCOM_ss_0p95v/LowPowerOpenCellLibrary_worst_low_ccs.lib  \
+#              ${libs_dir}/lib_WCLCOM_ss_0p95v/NangateOpenCellLibrary_worst_low_ccs.lib 
+set lib(io)  "${libs_dir}/IO.lib \
+              ${libs_dir}/PLL.lib \
+              ${libs_dir}/MemGen_16_10.lib"
+
+set lib(hvt) "${libs_dir}/lib_WCLCOM_ss_0p85v/0p85/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.lib \
+              ${libs_dir}/lib_WCLCOM_ss_0p95v/0p95/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.lib"
+
+set lib(svt) "${libs_dir}/lib_WCLCOM_ss_0p85v/0p85/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.lib  \
+              ${libs_dir}/lib_WCLCOM_ss_0p95v/0p95/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.lib"
+
+set lib(lvt) "${libs_dir}/lib_WCLCOM_ss_0p85v/0p85/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.lib \
+              ${libs_dir}/lib_WCLCOM_ss_0p95v/0p95/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.lib"
+
+#Specify the Physical libraries
+set lef(io)  "${lefs_dir}/IO.lef \
+              ${lefs_dir}/PLL.lef \
+              ${lefs_dir}/MemGen_16_10.lef "
+#              ${lefs_dir}/NangateOpenCellLibrary.macro.lef"
+set lef(hvt)  ${lefs_dir}/NangateOpenCellLibrary_HVT.macro.lef
+set lef(svt)  ${lefs_dir}/NangateOpenCellLibrary_SVT.macro.lef
+set lef(lvt)  ${lefs_dir}/NangateOpenCellLibrary_LVT.macro.lef
+
+#################################################
+### Build the library ODB
+#################################################
+read_lef ${lefs_dir}/tech_lef/NangateOpenCellLibrary.tech.lef
+read_ptf -temperature 0 ${ekit_dir}/nangate/ptf/NCSU_FreePDK_45nm.ptf
+foreach vt [list io hvt svt lvt] {
+  puts "processing ${vt}... " 
+  read_library  $lib(${vt})
+  read_lef $lef(${vt})
+}
+write_db -data library ${ekit_dir}/libs/nangate_mvt.odb
+puts "wrote ${vt}: ${libs_dir}/libs/nangate_mvt.odb" 
+
@@ -0,0 +1,36 @@
+#########################################################
+#                 gen_tcelllib.tcl
+#
+# Description:  Erzeugt tcelllib aus NanGate fslib
+#               für Tessent Shell MBIST Insertion
+#
+# Usage:        Im Tessent Shell Prompt:
+#               SETUP> set script_dir "scripts_risc_v"
+#               SETUP> set ekit_dir "."
+#               SETUP> source scripts_risc_v/gen_tcelllib.tcl
+#
+# Dependencies: Tessent Shell (kein Oasys benötigt)
+#########################################################
+set script_dir "scripts_risc_v"
+if {![info exists ekit_dir]} {
+    set ekit_dir [file dirname ${script_dir}]
+}
+
+set fastscan_lib "${ekit_dir}/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib"
+set output_dir   "${ekit_dir}/output"
+
+# Prüfen ob fslib existiert
+if {![file exists $fastscan_lib]} {
+    puts "ERROR: fslib nicht gefunden: $fastscan_lib"
+    exit 1
+}
+
+puts "\nINFO: Lade fslib: $fastscan_lib"
+read_cell_library $fastscan_lib
+
+puts "\nINFO: Schreibe tcelllib..."
+file mkdir ${output_dir}
+write_cell_library ${output_dir}/nangate_complete.tcelllib -replace
+
+puts "\nINFO: Fertig -> ${output_dir}/nangate_complete.tcelllib"
+exit
@@ -0,0 +1,33 @@
+# Enable capture of commands
+ config_shell -echo true
+
+###################Top Module Specification###########
+set top_module "cpu"
+set max_route_layer "10"
+
+# Set design file path variables
+#set script_dir [file dirname [info script]]
+set script_dir "scripts_risc_v"
+set ekit_dir   [file dirname ${script_dir}]
+
+set demo_chip_rtl_dir "${ekit_dir}/riscv_rtl/hw/rtl"
+set demo_chip_sdc_files "${ekit_dir}/constraints/riscv.sdc"
+set output_dir "${ekit_dir}/output"
+
+
+##set a consistant reporting format for timing
+config_report timing -format "cell edge arrival delay arc_delay net_delay slew net_load load fanout location power_domain"
+
+# Set DFT flow settings 
+# To run the tessent DFT flow, please set the dft_flow variable to "tessent" from "oasys" and update tessent_build path 
+set dft_flow tessent
+set tessent_build "/applications/SiemensEDA/siemenseda2023/tessent/bin/tessent"
+#set tessent_build $env(TESSENT)/bin/tessent
+
+#Source the script that sets the path variables for all input files
+source ${script_dir}/demo_chip_design_files.tcl
+
+echo "\n-----------------------------"
+echo "\nDone setting design variables"
+echo "\n-----------------------------\n"
+
@@ -0,0 +1,72 @@
+#=======================================================#
+#Enable shift registers identification
+#=======================================================#
+infer_shift_registers
+
+#=======================================================#
+#Define dft settings
+#=======================================================#
+define_test_pin -pin SCAN_ENABLE -scan 1 -default_scan_enable -create_port
+define_test_pin -pin scan_mode -scan 1
+define_test_clock -pin sysclk_byp -test_domain A
+connect_clock_gating_test_pin -test_pin SCAN_ENABLE
+
+#Check the DFT violation and use autofix feature to adress them
+check_dft -auto_test_clock -auto_test_pins
+report_dft_violations
+
+#=======================================================#
+# Pre fix_dft_violation database
+#=======================================================#
+write_db ${output_dir}/odb/demo_chip.oasysdft_pre_fix.odb
+
+fix_dft_violations -type all -test_clock sysclk_byp -test_control scan_mode
+check_dft
+report_dft_violations
+
+#=======================================================#
+#Disable scan on enable_nova0_reg & enable_nova1_reg
+#=======================================================#
+set_dont_scan -verbose [get_cell  enable_nova0_reg] true
+set_dont_scan -verbose [get_cell  enable_nova1_reg] true
+
+#=======================================================#
+#Final optimize
+#=======================================================#
+optimize 
+write_db ${output_dir}/odb/demo_chip.oasysdft_post_fix.odb
+write_verilog ${output_dir}/demo_chip.oasysdft_post_fix.v
+report_timing
+report_endpoints
+report_power
+report_path_groups
+
+
+### Using partitioned based DFT Flow
+
+# Should report 'default' as current dft partition
+current_dft_partition
+
+# Define DFT partitions 
+define_dft_partition P1 -instances {i_cpu_sys nova1}
+define_dft_partition P2 -instances { nova0}
+
+
+report_dft_partitions
+
+## define_scan_chain 
+define_scan_chain -scan_in SI_1 -scan_out SO_1 -create_port -partition P1
+
+current_dft_partition P2
+# following definition scope is limited to P2
+define_scan_chain -scan_in SI_2 -scan_out SO_2 -create_port
+
+# Resetting the partition definition to 'Default'
+reset_dft_partition
+
+# Following scan chains should be created corresponding to 'Default' partition, meaning any logic outside of already coverd partitions.
+define_scan_chain -scan_in SI_3 -scan_out SO_3 -create_port
+
+#connect_scan_chains
+connect_scan_chains -physical -mix_clock_edges
+
@@ -0,0 +1,165 @@
+if {[info exists tessent_build] && [string match $dft_flow tessent]} {
+  puts "INFO::using $tessent_build build to run the Tessent DFT flow"
+} else {
+  puts "ERROR::To run the tessent DFT flow, Please set the following variables (as shown in the scripts/init_design.tcl file)"
+  puts "    - 'tessent_build' variable to the tessent executable"
+  puts "    # set dft_flow tessent"
+  puts ""
+  puts "    - 'dft_flow' variable to 'tessent'"
+  puts "    # set tessent_build \$env(TESSENT)/bin/tessent"
+  return 0 
+}
+
+config_tessent -exec_path $tessent_build
+
+
+#=======================================================#
+#Define dft settings
+#=======================================================#
+
+define_test_clock -pin clk_25mhz
+
+#define_test_pin -pin reset -scan 1 
+# Define scan enable port (create it since counter doesn't have one)
+#define_test_pin -pin scan_en -scan 1 -default_scan_enable -create_port
+define_test_pin -pin scan_en -scan_mode 1 -default_scan_enable -create_port true
+
+define_test_pin -pin scan_mode -scan_mode 1
+
+# Add this - exclude main_mem from scan insertion entirely
+# Exclude memory subsystem from scan insertion
+#set_dont_scan theMem true          
+
+# Define reset as test pin
+#define_test_pin -pin btn[0] reset -scan 1
+#For reset: check the polarity:
+#Active-high reset → -scan_mode 0-> so it does no reset during scan
+#Active-low reset → -scan_mode 1
+define_test_pin -name reset -pin btn[0] -scan_mode 1
+
+
+# connect_clock_gating_test_pin -test_pin scan_mode_pad/C
+
+#set_dont_scan clk12p5_reg true
+
+#config_tessent_scan -add_dofile_cmds "add_input_constraints scan_en -C1"
+
+# Check the DFT violation and use autofix feature to adress them
+check_dft -auto_test_clock -auto_test_pins
+
+#=======================================================#
+# Pre fix_dft_violation database
+#=======================================================#
+write_db  ${output_dir}/odb/riscv.tessent_pre_fix.odb
+fix_dft_violations -type all -test_clock clk_25mhz -test_control scan_en
+
+#fix_dft_violations -type all -test_clock sysclk_byp -test_control scan_mode_pad/C
+
+#check_dft < Error: There was 1 S6 violation (driven scan-in pin of a sub chain or of a scan cell in unspecified scncan)
+#//For failed scan cells, use "add_scan_chains" or "add_scan_segments" commands to declare previously inserted scan chains.
+
+report_dft_violations
+
+#=======================================================#
+#Final optimize
+#=======================================================#
+optimize 
+write_db      ${output_dir}/odb/riscv.tessent_post_fix.odb
+write_verilog ${output_dir}/riscv.tessent_post_fix.v
+#report_timing
+#report_endpoints
+#report_power
+#report_path_groups
+
+#========================================================#
+# Formalpro verification command
+#========================================================#
+
+#verify ${output_dir}/verilog/post_optimize.v -base_directory post_optimize
+
+
+#=======================================================#
+# configuring Tessent build
+#=======================================================#
+#Specify the path to Tessent exec.
+
+#config_tessent -exec_path $tessent_build
+
+#=======================================================#
+# Tessent TPI
+#=======================================================#
+
+#set fastscan_path "${ekit_dir}/libs/fastscan"
+#config_tessent -ignore_clock_gating "on"
+#set lib_list [glob -nocomplain $fastscan_path/*.fslib ]
+#config_tessent -library $lib_list
+#config_tessent_tpi  -total_number 2% -control_point_enable control_test_point_en -observe_point_enable observe_test_point_en
+
+#run_tessent_tpi
+
+# Only add library if it exists
+set fastscan_path "${ekit_dir}/libs/fastscan"
+if {[file exists $fastscan_path]} {
+  set lib_list [glob -nocomplain $fastscan_path/*.fslib]
+  if {[llength $lib_list] > 0} {
+    config_tessent -library $lib_list
+  }
+}
+
+#=======================================================#
+# WICHTIG: clk12p5_reg von Scan ausschließen
+# Dieser interne Clock-Teiler-FF verursacht den S6-Fehler,
+# weil fix_dft_violations bereits einen MUX-SI daran
+# verdrahtet hat, den Tessent als "undeklarierte Sub-Chain"
+# erkennt.
+#=======================================================#
+#set_dont_scan clk12p5_reg
+#add_scan_segments clk12p5_reg
+
+# Skip TPI for counter - coverage already high
+# run_tessent_tpi  ← not needed
+
+#========================================================#
+# Formalpro verification command
+#========================================================#
+
+#verify ${output_dir}/verilog/post_tpi.v -base_directory post_tpi
+
+
+#=======================================================#
+# Tessent SCAN only
+#=======================================================#
+
+echo "\n--------------check dft---------------"
+check_dft
+
+echo "\n--------------define Scan-Chains---------------"
+# Scan-Chains definieren
+for {set i 1} {$i <= 4} {incr i} {
+    define_scan_chain -scan_in SI_$i -scan_out SO_$i  -create_port
+}
+
+#define_scan_chain -scan_in SI_1 -scan_out SO_1 -create_port
+echo "\n----------run_tessent_scan----------------"
+run_tessent_scan
+
+write_db      ${output_dir}/odb/riscv.tessent_post_scan.odb
+write_verilog ${output_dir}/riscv.tessent_post_scan.v
+
+echo "\n----------report_power----------------"
+report_power
+echo "\n----------report_path_groups----------------"
+report_path_groups
+echo "\n----------report_scan_chains----------------"
+report_scan_chains
+echo "\n----------report_timing----------------"
+report_timing
+
+#========================================================#
+#Formalpro verification command
+#========================================================#
+
+#verify ${output_dir}/verilog/post_dft.v -base_directory post_dft
+
+
+
@@ -0,0 +1,43 @@
+#########################################################
+#                 open_database.tcl
+#
+# Description:  Load the generated Oasys-RTL databases (.odb)
+#               into the tool
+#
+# Usage:        source in Oasys-RTL Command prompt
+#
+# Dependencies: 1_init_design.tcl
+#               Existing odb created from the 
+#               Launched from Oasys-RTL shell
+#
+#########################################################
+
+# Check if dependent scripts have been loaded
+if {![info exists top_module]} {
+  source scripts/init_design.tcl
+}
+
+if { ![info exists ekit_dir] } { return }
+
+# Read existing Oasys-RTL database (design and libraries)	
+if {[file exists ${ekit_dir}/output/odb/demo_chip.oasys_final.odb]} {
+  puts "Using ODB from output directory" 
+  read_db ${ekit_dir}/output/odb/demo_chip.oasys_final.odb
+} elseif {[file exists ${ekit_dir}/demo_chip_rtl/demo_chip.odb]} {
+  puts "Using pre-defined ODB from demo_chip_rtl directory" 
+  read_db ${ekit_dir}/demo_chip_rtl/demo_chip.odb
+} else {
+  puts "unable to locate ODB file for demo_chip design" 
+}
+
+# Report DFT if scan chains exist
+if { [get_scan_chains] > 0 } {
+  check_dft
+  report_scan_chains
+}
+
+# Report design	
+puts "Running timing reports..."
+report_path_groups
+report_timing
+
@@ -0,0 +1,87 @@
+#########################################################
+#                 4_mbist_tessent_shell.tcl
+#
+# Description:  MemoryBIST insertion für RISC-V Design
+#
+# Usage:        Im Tessent Shell Prompt:
+#               SETUP> set script_dir "scripts_risc_v"
+#               SETUP> set ekit_dir "."
+#               SETUP> source scripts_risc_v/4_mbist_tessent_shell.tcl
+#
+# Dependencies: - nangate_complete.tcelllib (aus gen_tcelllib.tcl)
+#               - riscv.tessent_post_scan.v (aus Oasys DFT Flow)
+#               - MemGen_16_10.memlib
+#########################################################
+set script_dir "scripts_risc_v"
+
+
+if {![info exists ekit_dir]} {
+    set ekit_dir [file dirname ${script_dir}]
+}
+
+#----------------------------------------------------------
+# 1. Kontext setzen - Gate-Level Netlist
+#----------------------------------------------------------
+set_context dft -no_rtl
+
+#----------------------------------------------------------
+# 2. Libraries laden
+#----------------------------------------------------------
+# Tessent Cell Library
+read_cell_library ${ekit_dir}/output/nangate_complete.tcelllib
+
+# Memory BIST Model für MemGen_16_10
+read_core_descriptions ${ekit_dir}/libs/MemGen_16_10.memlib
+
+#----------------------------------------------------------
+# 3. Gate-Level Netlist laden
+#----------------------------------------------------------
+read_verilog ${ekit_dir}/output/riscv.tessent_post_scan.v
+
+#----------------------------------------------------------
+# 4. Top-Level und Design-Level setzen
+#----------------------------------------------------------
+set_current_design cpu
+set_design_level chip
+
+#----------------------------------------------------------
+# 5. MBIST Anforderungen setzen
+#----------------------------------------------------------
+set_dft_specification_requirements -memory_test on
+
+# Gefundene Memory-Instanzen anzeigen
+report_memory_instances
+
+#----------------------------------------------------------
+# 6. Clocks definieren
+#----------------------------------------------------------
+add_clocks clk_25mhz -period 40ns -label mbist_clk
+
+#----------------------------------------------------------
+# 7. Design Rule Check
+#----------------------------------------------------------
+check_design_rules
+
+#----------------------------------------------------------
+# 8. DFT Specification erstellen und verarbeiten
+#----------------------------------------------------------
+set dft_spec [create_dft_specification]
+report_config_data $dft_spec
+validate_dft_specification
+process_dft_specification
+extract_icl
+
+#----------------------------------------------------------
+# 9. Pattern Generation
+#----------------------------------------------------------
+set pat_spec [create_patterns_specification]
+process_patterns_specification
+
+#----------------------------------------------------------
+# 10. Simulation und Synthese
+#----------------------------------------------------------
+run_testbench_simulations
+check_testbench_simulations
+run_synthesis
+
+exit
@@ -0,0 +1,8 @@
+set rtVersion [get_parameter version]
+
+## remove all placement
+delete_physical -all -verbose true
+##  create a new rectilinear die given a list of points
+create_chip -points {{0  0} {0  700} {700  700} {700  1600} {2500  1600} {2500  0} } -overwrite true -verbose true
+report_design_metrics
+#optimize -place
@@ -0,0 +1,84 @@
+#! /bin/sh -f
+#\
+exec tessent -shell -log logfiles/$0.log -replace -dofile "$0"
+
+# Set the context to insert DFT into RTL-level design
+set_context dft -rtl -design_id rtl1
+
+# Set the location of the TSDB. Default is the current working directory.
+set_tsdb_output_directory ../tsdb_outdir
+
+# Read the verilog
+read_verilog ../RTL/cpu_top.v
+read_verilog ../RTL/piccpu.v
+
+# Read the cell library
+read_cell_library ../library/standard_cells/tessent/adk.tcelllib
+read_cell_library ../library/memories/picdram.tcelllib
+
+# Define location of memory library files
+set_design_sources -format tcd_memory -Y ../library/memories -extension tcd_memory
+
+set_current_design cpu_top
+
+# Set the design level before running check_design_rules
+set_design_level chip
+
+# Define set_dft_specification_requirements
+set_dft_specification_requirements -boundary_scan on -memory_test on
+
+# Specify the TAP pins using set_attribute_value
+set_attribute_value tck_p -name function -value tck
+set_attribute_value tdi_p -name function -value tdi
+set_attribute_value tms_p -name function -value tms
+set_attribute_value trst_p -name function -value trst
+set_attribute_value tdo_p -name function -value tdo
+
+set_boundary_scan_port_options clk* -cell_options dont_touch
+set_boundary_scan_port_options ramclk_p -cell_options dont_touch
+
+# Specify the clocks feeding memories
+add_clocks 0 ramclk_p -period 5ns
+
+check_design_rules
+
+# Create and report a DFT Specification
+set spec [create_dft_specification]
+report_config_data $spec
+
+# Set parameter to divide the boundary scan chain into smaller segments to be used during logic test
+set_config_value $spec/BoundaryScan/max_segment_length_for_logictest 65
+
+report_config_data $spec
+
+# Add auxilary mux on the inputs and outputs used for EDT Channel pins
+read_config_data -in ${spec}/BoundaryScan -from_string {
+  AuxiliaryInputOutputPorts {
+    auxiliary_input_ports  : portain_p[0], portain_p[1], portain_p[2], enable_p, pdata_p[0], pdata_p[1] ;
+    auxiliary_output_ports  : portbout_p[0], portbout_p[1], portbout_p[2] ;
+  }
+}
+report_config_data $spec
+
+# Generate and insert the hardware
+process_dft_specification
+
+# Extract IJAG network and create ICL file for the design
+extract_icl
+
+# Provides new and original updated RTL into this new file to be elaborated and Synthesized later
+# If not using logic test (EDT insertion in next step) this would be used for synthesis
+#write_design_import_script  use_in_synthesis.tcl -replace
+
+# Generate patterns to verify the inserted DFT logic
+create_pattern_specification
+process_patterns_specification
+
+# Point to the libraries and run the simulation 
+set_simulation_library_sources -v ../library/standard_cells/verilog/adk.v -v ../library/memories/picdram.v
+run_testbench_simulations
+
+# If simulation fails, use this command to see which pattern failed
+#check_testbench_simulations
+
+exit