# do run.do
# QuestaSim-64 vlog 2023.2 Compiler 2023.04 Apr 11 2023
# Start time: 13:15:58 on Apr 29,2026
# vlog -sv dummz_memgen_16.sv 
# -- Compiling module MemGen_16_10
# 
# Top level modules:
# 	MemGen_16_10
# End time: 13:15:58 on Apr 29,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2023.2 Compiler 2023.04 Apr 11 2023
# Start time: 13:15:58 on Apr 29,2026
# vlog -sv -lint -pedanticerrors -f rtl_flist.f 
# -- Compiling module pc
# -- Compiling module reg_file
# -- Compiling module alu
# -- Compiling module MemGen_32_11
# -- Compiling module main_mem
# -- Compiling module decoder
# -- Compiling module cpu
# 
# Top level modules:
# 	cpu
# End time: 13:15:58 on Apr 29,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vopt 2023.2 Compiler 2023.04 Apr 11 2023
# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
# Start time: 13:15:58 on Apr 29,2026
# vopt work.cpu -o cpu_opt "+acc" -pedanticerrors 
# 
# Top level modules:
# 	cpu
# 
# Analyzing design...
# -- Loading module cpu
# -- Loading module decoder
# -- Loading module alu
# -- Loading module reg_file
# -- Loading module pc
# -- Loading module main_mem
# -- Loading module MemGen_32_11
# -- Loading module MemGen_16_10
# Optimizing 8 design-units (inlining 0/11 module instances):
# -- Optimizing module decoder(fast)
# -- Optimizing module main_mem(fast)
# -- Optimizing module MemGen_32_11(fast)
# -- Optimizing module cpu(fast)
# -- Optimizing module alu(fast)
# -- Optimizing module MemGen_16_10(fast)
# -- Optimizing module reg_file(fast)
# -- Optimizing module pc(fast)
# Optimized design name is cpu_opt
# End time: 13:15:58 on Apr 29,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1