charapallivenkatsaja@efiapps0:/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock$ tessent -shell // Tessent Shell 2023.4-p1 Mon Feb 19 16:22:02 GMT 2024 // Unpublished work. Copyright 2024 Siemens // // This material contains trade secrets or otherwise confidential // information owned by Siemens Industry Software Inc. or its affiliates // (collectively, "SISW"), or its licensors. Access to and use of this // information is strictly limited as set forth in the Customer's // applicable agreements with SISW. // // Siemens software executing under x86-64 Linux on Thu May 28 17:29:18 CEST 2026. // 64 bit version // Host: efiapps0.ads1.fh-nuernberg.de (12 x 3.5 GHz, 48014 MB RAM, 24575 MB Swap) // SETUP> source scri scripts scripts_risc_v SETUP> source scripts_risc_v/5_atpg.do // sub-command: set_context patterns -scan // sub-command: set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir // sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib // Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib // Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib // sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib // Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib // Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib // sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib // Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib // Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib // sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib // Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib // Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib // sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib // Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib // Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib // sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib // Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib // Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib // sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib // Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib // Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib // sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib // Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib // Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib // sub-command: read_design cpu -design_id Scan_0 // sub-command: add_black_boxes -modules " MemGen_16_10 " // Command 'add_black_boxes' requires an elaborated design. Automatically elaborating the design ... // Note: 36 duplicate cell library models were read. The last model read of the same name was kept. // To see detailed messages per duplicate model, issue 'set_cell_library_options -report_duplicate_models on' // before issuing 'read_cell_library'. // Warning: 1 cell library model contained 2 floating model outputs. // To see detailed messages per model, issue 'set_cell_library_options -report_floating_nets on' // before issuing 'read_cell_library'. // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X1_SVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X2_SVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X4_SVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X8_SVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X1' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X2' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X4' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X8' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X1_HVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X2_HVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X4_HVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X8_HVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X1_LVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X2_LVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X4_LVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' // Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' // Model 'CLKGATE_X8_LVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' // Note: Top design is 'cpu'. // Warning: 32 cases: Unused net in DFT library model // Warning: 106 cases: Undriven net in netlist module // Warning: 1 case: Floating input on instance in netlist // Warning: 47 cases: Net in netlist not connected // Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings // Design elaboration successful. // sub-command: add_black_boxes -modules " MemGen_32_11 " // sub-command: add_black_boxes -modules " main_mem " // sub-command: set_current_design cpu // Warning: Undefined modules were found. // Before using "set_system_mode" or "create_flat_model", you must either define // the missing modules using "read_verilog" and/or "read_cell_library", or use the // following command to treat them as black boxes: add_black_boxes -modules { \ MemGen_16_10 \ } // You can also use "add_black_boxes -auto" to black box all undefined modules but // it is recommended that you do not add this command to your dofile. Doing so may // unintentionally black-box new undefined modules in future runs. // Warning: 106 cases: Undriven net in netlist module // Warning: 1 case: Floating input on instance in netlist // Warning: 47 cases: Net in netlist not connected // Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings // Note: Design level set to 'physical_block' from previous settings // sub-command: set_design_level physical_block // sub-command: import_scan_mode unwrapped // Resetting design. // Warning: The current mode name was not specified and will be set to 'unwrapped'. // Different ATPG configurations should use different mode names, otherwise // they will overwrite each other in the TSDB when 'write_tsdb_data -replace' is called. // If you will have multiple ATPG configurations for this scan mode of this design, // use the 'set_current_mode' command to change the current mode name. // sub-command: set_system_mode analysis // Warning: Rule FN1 violation occurs 152 times // Flattening process completed, cell instances=4041, gates=16395, PIs=13, POs=12, CPU time=0.08 sec. // --------------------------------------------------------------------------- // Begin circuit learning analyses. // -------------------------------- // Learning completed, CPU time=0.04 sec. // --------------------------------------------------------------------------- // Begin scan chain identification process, memory elements = 1059. // --------------------------------------------------------------------------- // Begin simulation of load_unload procedure. // Simulation of load_unload procedure completed, CPU time=0.0 sec. // Chain = unwrapped_chain1 successfully traced with scan_cells = 256. // Chain = unwrapped_chain2 successfully traced with scan_cells = 256. // Chain = unwrapped_chain3 successfully traced with scan_cells = 256. // Chain = unwrapped_chain4 successfully traced with scan_cells = 256. // 1024 scan cells have been identified in 4 scan chains. // Longest scan chain has 256 scan cells. // --------------------------------------------------------------------------- // Begin transparent latch checking for 35 latches. // --------------------------------------------------------------------------- // Number transparent latches = 35. // --------------------------------------------------------------------------- // Begin scan clock rules checking. // --------------------------------------------------------------------------- // 1 scan clock/set/reset lines have been identified. // All scan clocks successfully passed off-state check. // Capture clock is set to clk_25mhz. // --------------------------------------------------------------------------- // 35 non-scan memory elements are identified. // --------------------------------------------------------------------------- // 35 non-scan memory elements are identified as TLA. (D5) // --------------------------------------------------------------------------- // 64 gates may have an observable X-state. (E5) // sub-command: report_clocks User-defined Clock (1): ========================= Sync and Async Source Clock ============================ ----------- --------- -------- Name Off State Internal ----------- --------- -------- 'clk_25mhz' 0 No // sub-command: report_drc_rules D5: #fails=35 handling=warning (non-scan memory element) E5: #fails=64 handling=note (X-state propagation) // sub-command: set_fault_type stuck // sub-command: add_faults -all // sub-command: create_patterns // | ------------------------------------------------------------------------------------------------------------------ | // | Analyzing the design | // | | // | Current clock restriction setting: Domain_clock (edge interaction) | // | (optimal) | // | | // | Current abort limit setting: 30 | // | Calling: set_abort_limit 300 100 | // | ------------------------------------------------------------------------------------------------------------------ | // | | // | Current sequential depth: 0 (optimal) | // | | // | ------------------------------------------------------------------------------------------------------------------ | // ------------------------------------------------------------------------ // Simulation performed for #gates = 16395 #faults = 4988 // system mode = analysis pattern source = internal patterns // ------------------------------------------------------------------------ // #patterns test #faults #faults # eff. # test process RE/AU/AAB // simulated coverage in list detected patterns patterns CPU time // --- ------ --- --- --- --- 6.31 sec 0/27368/0 // 16 25.95% 0 2239 10 10 6.32 sec // ----------------------------------------------------------------------- // Performing redundant fault identification for 27368 faults // ----------------------------------------------------------------------- // deterministic ATPG invoked with abort limit = 300 // # red. # non-red. # abort # remn. progress test process // faults faults faults faults coverage CPU time // 20 27338 10 0 100.00% 25.96% 1903.57 sec Statistics Report Stuck-at Faults --------------------------------------- Fault Classes #faults (total) ----------------------- -------------- FU (full) 39020 --------------------- -------------- DS (det_simulation) 2239 ( 5.74%) DI (det_implication) 7351 (18.84%) UU (unused) 2062 ( 5.28%) RE (redundant) 20 ( 0.05%) AU (atpg_untestable) 27348 (70.09%) --------------------------------------- Fault Sub-classes --------------------- AU (atpg_untestable) BB (black_boxes) 24599 (63.04%) Unclassified 2749 ( 7.05%) --------------------------------------- Coverage --------------------- test_coverage 25.96% fault_coverage 24.58% atpg_effectiveness 100.00% --------------------------------------- #test_patterns 10 #simulated_patterns 16 CPU_time (secs) 1925.7 --------------------------------------- // sub-command: report_statistics Statistics Report Stuck-at Faults --------------------------------------- Fault Classes #faults (total) ----------------------- -------------- FU (full) 39020 --------------------- -------------- DS (det_simulation) 2239 ( 5.74%) DI (det_implication) 7351 (18.84%) UU (unused) 2062 ( 5.28%) RE (redundant) 20 ( 0.05%) AU (atpg_untestable) 27348 (70.09%) --------------------------------------- Fault Sub-classes --------------------- AU (atpg_untestable) BB (black_boxes) 24599 (63.04%) Unclassified 2749 ( 7.05%) --------------------------------------- Coverage --------------------- test_coverage 25.96% fault_coverage 24.58% atpg_effectiveness 100.00% --------------------------------------- #test_patterns 10 #simulated_patterns 16 CPU_time (secs) 1925.7 --------------------------------------- // sub-command: report_faults -summary Statistics Report Stuck-at Faults --------------------------------------- Fault Classes #faults (total) ----------------------- -------------- FU (full) 39020 --------------------- -------------- DS (det_simulation) 2239 ( 5.74%) DI (det_implication) 7351 (18.84%) UU (unused) 2062 ( 5.28%) RE (redundant) 20 ( 0.05%) AU (atpg_untestable) 27348 (70.09%) --------------------------------------- Fault Sub-classes --------------------- AU (atpg_untestable) BB (black_boxes) 24599 (63.04%) Unclassified 2749 ( 7.05%) --------------------------------------- Coverage --------------------- test_coverage 25.96% fault_coverage 24.58% atpg_effectiveness 100.00% --------------------------------------- #test_patterns 10 #simulated_patterns 16 CPU_time (secs) 1925.7 --------------------------------------- // sub-command: write_patterns cpu_patterns.stil -stil -replace // sub-command: write_patterns cpu_patterns_serial.v -verilog -serial -replace // sub-command: write_tsdb_data -replace // Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped.tcd.gz // Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped.flat.gz // Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.patdb // Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.faults.gz // sub-command: exit