# =============================================================================
# Constraints File: cpu.sdc
# Project: BCDC Microtec Academy - RISC-V CPU
# Top Module: cpu
# =============================================================================

# -----------------------------------------------------------------------------
# 1. Primary Clock - 25 MHz input clock
# -----------------------------------------------------------------------------
create_clock -name clk_25mhz \
             -period 40.000 \
             -waveform {0 20} \
             [get_ports clk_25mhz]

# -----------------------------------------------------------------------------
# 2. Generated Clock - 12.5 MHz (divided by 2 inside always_ff)
# -----------------------------------------------------------------------------
#create_generated_clock -name clk_12p5 \
#                       -source [get_ports clk_25mhz] \
 #                      -divide_by 2 \
 #                      [get_pins thePC/clk]

# -----------------------------------------------------------------------------
# 3. Clock Uncertainty & Transition
# -----------------------------------------------------------------------------
set_clock_uncertainty -setup 0.5 [get_clocks clk_25mhz]
set_clock_uncertainty -hold  0.2 [get_clocks clk_25mhz]

set_clock_transition 0.1 [get_clocks clk_25mhz]

# -----------------------------------------------------------------------------
# 4. Input Delays (btn pins - relative to clk_25mhz)
# -----------------------------------------------------------------------------
set_input_delay -clock clk_25mhz -max 2.0 [get_ports {btn[*]}]
set_input_delay -clock clk_25mhz -min 0.5 [get_ports {btn[*]}]

# -----------------------------------------------------------------------------
# 5. Output Delays (led pins)
# -----------------------------------------------------------------------------
set_output_delay -clock clk_25mhz -max 2.0 [get_ports {led[*]}]
set_output_delay -clock clk_25mhz -min 0.5 [get_ports {led[*]}]

# -----------------------------------------------------------------------------
# 6. False Paths
# -----------------------------------------------------------------------------
# Reset is async and driven from a button - no timing analysis needed
set_false_path -from [get_ports {btn[0]}]

# LED outputs driven from combinational/slow logic - relax if needed
# set_false_path -to [get_ports {led[*]}]

# -----------------------------------------------------------------------------
# 7. Clock Domain Crossing
# -----------------------------------------------------------------------------
# clk12p5 is derived from clk_25mhz via FF division - set as async crossing
# to prevent hold violations across the two domains
#set_clock_groups -asynchronous \
                 -group [get_clocks clk_25mhz] \
                 -group [get_clocks clk_12p5]

# -----------------------------------------------------------------------------
# 8. Drive Strength & Load (adjust to your target technology)
# -----------------------------------------------------------------------------
#set_driving_cell -lib_cell <YOUR_INPUT_BUF> [get_ports {btn[*]}]

set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[*]}]

set_load 0.05 [get_ports {led[*]}]

# -----------------------------------------------------------------------------
# 9. Max Fanout & Transition
# -----------------------------------------------------------------------------
set_max_fanout 20 [current_design]
set_max_transition 0.5 [current_design]