#! /bin/sh -f
#\
exec tessent -shell -log logfiles/$0.log -replace -dofile "$0"

# Set the context to insert DFT into RTL-level design
set_context dft -rtl -design_id rtl1

# Set the location of the TSDB. Default is the current working directory.
set_tsdb_output_directory ../tsdb_outdir

# Read the verilog
read_verilog ../RTL/cpu_top.v
read_verilog ../RTL/piccpu.v

# Read the cell library
read_cell_library ../library/standard_cells/tessent/adk.tcelllib
read_cell_library ../library/memories/picdram.tcelllib

# Define location of memory library files
set_design_sources -format tcd_memory -Y ../library/memories -extension tcd_memory

set_current_design cpu_top

# Set the design level before running check_design_rules
set_design_level chip

# Define set_dft_specification_requirements
set_dft_specification_requirements -boundary_scan on -memory_test on

# Specify the TAP pins using set_attribute_value
set_attribute_value tck_p -name function -value tck
set_attribute_value tdi_p -name function -value tdi
set_attribute_value tms_p -name function -value tms
set_attribute_value trst_p -name function -value trst
set_attribute_value tdo_p -name function -value tdo

set_boundary_scan_port_options clk* -cell_options dont_touch
set_boundary_scan_port_options ramclk_p -cell_options dont_touch

# Specify the clocks feeding memories
add_clocks 0 ramclk_p -period 5ns

check_design_rules

# Create and report a DFT Specification
set spec [create_dft_specification]
report_config_data $spec

# Set parameter to divide the boundary scan chain into smaller segments to be used during logic test
set_config_value $spec/BoundaryScan/max_segment_length_for_logictest 65

report_config_data $spec

# Add auxilary mux on the inputs and outputs used for EDT Channel pins
read_config_data -in ${spec}/BoundaryScan -from_string {
  AuxiliaryInputOutputPorts {
    auxiliary_input_ports  : portain_p[0], portain_p[1], portain_p[2], enable_p, pdata_p[0], pdata_p[1] ;
    auxiliary_output_ports  : portbout_p[0], portbout_p[1], portbout_p[2] ;
  }
}
report_config_data $spec

# Generate and insert the hardware
process_dft_specification

# Extract IJAG network and create ICL file for the design
extract_icl

# Provides new and original updated RTL into this new file to be elaborated and Synthesized later
# If not using logic test (EDT insertion in next step) this would be used for synthesis
#write_design_import_script  use_in_synthesis.tcl -replace

# Generate patterns to verify the inserted DFT logic
create_pattern_specification
process_patterns_specification

# Point to the libraries and run the simulation 
set_simulation_library_sources -v ../library/standard_cells/verilog/adk.v -v ../library/memories/picdram.v
run_testbench_simulations

# If simulation fails, use this command to see which pattern failed
#check_testbench_simulations

exit