// MemGen_16_10_stub.sv
// Behavioral stub - ports matched from MemGen_32_11.sv instantiation
module MemGen_16_10 #(
    parameter ADDR_WIDTH = 10,
    parameter DATA_WIDTH = 16
)(
    input  logic                  chip_en,
    input  logic                  clock,
    input  logic [ADDR_WIDTH-1:0] addr,
    input  logic                  rd_en,
    output logic [DATA_WIDTH-1:0] rd_data,
    input  logic                  wr_en,
    input  logic [DATA_WIDTH-1:0] wr_data
);
    logic [DATA_WIDTH-1:0] mem [0:(2**ADDR_WIDTH)-1];

    always_ff @(posedge clock) begin
        if (chip_en) begin
            if (wr_en)
                mem[addr] <= wr_data;
            else if (rd_en)
                rd_data <= mem[addr];
        end
    end
endmodule