//  *********************************************************************************************
//  Project Version  : v1.0
//  Project          : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
//  -----
//  Copyright (c)    : 2025 Fraunhofer IIS, Department IDS
//  Created          : 15.Oct.2025  by Bomin Kim
//  Last Modified    : 23.Oct.2025  by Bomin Kim       [commit 2f8f03d]
//  -----
//  HISTORY          : Date         By         Comments
//                     -----------  ---------  -------------------------------------------------
//  *********************************************************************************************



`timescale 1ns/1ns

module pc_tb ();

  // Local Signals
  logic[31:0] CurrentPC;
  logic[31:0] JumpOrBranchPC;
  logic       JumpOrBranch;
  logic[31:0] NextPC;
  logic       reset;
  logic       clk;

  // Toplevel instance (DUT)
  pc u_pc (
      .CurrentPC(CurrentPC),
      .JumpOrBranchPC(JumpOrBranchPC),
      .JumpOrBranch(JumpOrBranch),
      .NextPC(NextPC),
      .reset(reset),
      .clk(clk)
  );

  // Clock generation
  always #20 clk = ~clk;

  // Initialization and run simulation
  initial begin
    dumpWave("wave.vcd");
    clk   = 0;
    JumpOrBranchPC = 32'h8;
    JumpOrBranch = 0;
    reset = 0; #100;
    reset = 1; #100;
    reset = 0; #490;
    JumpOrBranch = 1; #60;
    JumpOrBranch = 0; #500;
    $finish;
  end

  // NextPC Monitor
  initial begin
    $monitor("time=%0t clk=%b reset=%b JumpOrBranch=%0h CurrentPC=%0h NextPC=%0h", $time, clk, reset, JumpOrBranch, CurrentPC, NextPC);
  end

  // Wave Dump Helper Task
  task dumpWave(string fileName);
    // Open wave file and dump all signals (2D arrays not included)
    $display("\nTime =  %0dns \t  : Opening wave file '%s'", $time, fileName);
    $dumpfile(fileName);
    $display("Time =  %0dns \t  : Dumping all %s signals in wave file (2D arrays not included)", $time, "pc_tb");
    $dumpvars(0, pc_tb);
  endtask: dumpWave

endmodule