19 lines
724 B
Fortran
19 lines
724 B
Fortran
// *********************************************************************************************
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 12.Aug.2025 by Marcus Bednara
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// Last Modified : 01.Nov.2025 by Hussein Elzomor
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// ------
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// Notes : All ${}-variables must be provided by shell or Makefile {using export}
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// *********************************************************************************************
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hw/rtl/pc.sv
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hw/rtl/reg_file.sv
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hw/rtl/alu.sv
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hw/rtl/MemGen_32_11.sv
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hw/rtl/main_mem.sv
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hw/rtl/decoder.sv
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hw/rtl/cpu.sv
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