46 lines
1.2 KiB
Tcl
Executable File
46 lines
1.2 KiB
Tcl
Executable File
#########################################################
|
|
# dse_base.tcl
|
|
#
|
|
# Description: Sets up the design for exploration
|
|
#
|
|
# Usage: source in Oasys-RTL Command prompt
|
|
#
|
|
# Dependencies: init_design.tcl
|
|
#########################################################
|
|
|
|
#Initialize script parameters
|
|
set_explore -variable clock_period \
|
|
-options { 2.00ns 2.25ns 2.50ns 2.75ns }
|
|
|
|
source scripts/init_design.tcl
|
|
|
|
#Disable warning messages
|
|
message -enable false TA-116
|
|
message -enable false LIB-136
|
|
message -enable false LIB-114
|
|
message -enable false NL-138
|
|
message -enable false NL-120
|
|
|
|
source scripts/open_database.tcl
|
|
###########################
|
|
# If available, synthesize opencore files
|
|
# instead of the pre-optimized ODB file
|
|
############################
|
|
# read_verilog $rtl_list -include $search_path
|
|
# synthesize -module ${top_module} -map_to_scan -gate_clock
|
|
# create_clock -period 2.50ns -name sysclk sysclk
|
|
# read_sdc -verbose $demo_chip_sdc_files
|
|
|
|
explore clock_period {
|
|
2.00ns { scale_clock -all -20 }
|
|
2.25ns { scale_clock -all -10 }
|
|
2.75ns { scale_clock -all 10 }
|
|
}
|
|
|
|
#Optimize
|
|
optimize -virtual
|
|
report_clocks
|
|
report_power
|
|
report_design_metrics
|
|
|