ESY1_Projekt_2022/fsm/tb_Fsm.sv

`include "Clk_generator.sv"
`include "Fsm.sv"

module tb_Fsm;
    wire clk;
    logic tim_ready;
    logic alarm;
    wire adc_en;
    wire tim_en;
    wire fram_c_en;
    wire led_c_en;
    Clk_generator clk_gen(.clk(clk));
    
  Fsm myfsm
    (
      .clk(clk),
      .tim_ready(tim_ready),
      .alarm(alarm),
      .adc_en(adc_en),
      .tim_en(tim_en),
      .fram_c_en(fram_c_en),
      .led_c_en(led_c_en)
    );

    always @(posedge clk) begin
      #1 tim_ready <= ~tim_ready;
    end
  

    initial begin
        $dumpfile("tb_Fsm.vcd");
        $dumpvars(0, tb_Fsm);
        #50 $finish;
    end
  
    initial begin
        #0 tim_ready = 1'b0;
        #0 alarm = 1'b0;
    end

endmodule