47 lines
876 B
Systemverilog
47 lines
876 B
Systemverilog
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module led_top (
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input wire clk12M,
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input wire rst,
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input wire [7:0] data_input,
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input wire data_valid,
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output reg REDn,
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output reg GRNn,
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output reg RED,
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output reg GRN,
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output reg alarm
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);
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wire red_pwm;
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wire grn_pwm;
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defparam U1.on_hi = 2'b10;
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defparam U1.on_lo = 2'b01;
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defparam U1.off = 2'b00;
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defparam U1.Brightness = 4'b0111; // 50% Brightness
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defparam U2.RGB0_CURRENT = "0b111111";
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defparam U2.RGB1_CURRENT = "0b111111";
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defparam U2.RGB2_CURRENT = "0b111111";
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LED_control1 U1 (.clk12M(clk12M),.enable(rst),.data_input(data_input),.data_valid(data_valid),.red_pwm(red_pwm),.grn_pwm(grn_pwm),.alarm(alarm));
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RGB U2 (.CURREN('b1),.RGB0PWM(),.RGB1PWM(grn_pwm),.RGB2PWM(red_pwm),.RGBLEDEN('b1),.RGB0(),.RGB1(GRNn),.RGB2(REDn));
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assign RED = red_pwm;
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assign GRN = grn_pwm;
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endmodule
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