ESY1_Projekt_2022/timer_port/testbench.sv

// Code your testbench here
// or browse Examples


`timescale 1ns/1ps;
module tb();
  reg inClk, inEN, inTaste;
  wire outReadTemp;
  wire outTasteAktiv;

  reg [7:0] inData;
  reg inEndOfConv;
  wire outDataValid;
  wire [7:0] outData;
  
  
  
  timer t1 (.inClk(inClk),
			.inTaste(inTaste),
			.inEN(inEN),
            .outReadTemp(outReadTemp),
			.outTasteAktiv(outTasteAktiv));
			
			
  parallelport p1 (.inData(inData),
					.inClk(inClk),
					.inTimerMeas(outReadTemp),
					.inEndOfConv(inEndOfConv), 
					.outDataValid(outDataValid), 
					.outData(outData));
            
           
  always #83 inClk <= ~inClk;
  always #1000000000 inEndOfConv <= ~inEndOfConv;
  always #100000000 inData = inData +1;
  
  initial begin
    //$dumpfile("dump.vcd");
    //$dumpvars;
    inClk <= 0;
	inEN <= 0;
	inTaste <= 0;

	inData <= 8'b0;
	inEndOfConv <= 0;
	#1000000000
	inTaste = 1;
	#1000000000
	#1000000000
	#1000000000
	inTaste = 0;
	#1000000000
	inEN <= 1;
	#1000000000
	inEN <= 0;
	#1000000000
	
	#1000000000
	#1000000000
	#1000000000
	#1000000000
	#1000000000
	#1000000000
	
	#1000000000
	#1000000000
	#1000000000
	#1000000000
	#1000000000
	#1000000000
	
	#1000000000
	#1000000000
	#1000000000
	#1000000000
	#1000000000
	#1000000000
	
	#1000000000
	#1000000000
	#1000000000
	#1000000000
	#1000000000
	#1000000000
	$stop;
  end
endmodule