diff --git a/Source_Ampel/rgb_led_top.sv b/Source_Ampel/rgb_led_top.sv index e2bec6d..f2c9af9 100644 --- a/Source_Ampel/rgb_led_top.sv +++ b/Source_Ampel/rgb_led_top.sv @@ -3,8 +3,6 @@ input wire clk12M, input wire rst, input wire [7:0] data_input, input wire data_valid, -output reg REDn, -output reg GRNn, output reg RED, output reg GRN, output reg alarm @@ -12,7 +10,8 @@ output reg alarm wire red_pwm; wire grn_pwm; - +reg REDn; +reg GRNn; defparam U1.on_hi = 2'b10; defparam U1.on_lo = 2'b01; defparam U1.off = 2'b00; diff --git a/Top/Top.sv b/Top/Top.sv index 4566c71..e553531 100644 --- a/Top/Top.sv +++ b/Top/Top.sv @@ -6,14 +6,24 @@ >>>>>>> b8d8341 (Initalized top level design) ======= `include "../Bus_if/Bus_if.sv" +<<<<<<< HEAD >>>>>>> c93bdaf (Added bus_if and fsm to top level design) +======= +`include "../timer_port/timer_top.sv" +>>>>>>> 026899b (Added parallelport, timer and ampelsteuerung) module Top( - input wire clk + input wire clk, + input wire rst, + input wire endOfConv, + output wire LEDg, + output wire LEDr, + output wire AlarmAmpel ); // Bus (Interface) Bus_if bus(.clk(clk)); // SPI Interface + // FSM <<<<<<< HEAD >>>>>>> b8d8341 (Initalized top level design) @@ -29,8 +39,34 @@ module Top( ); >>>>>>> c93bdaf (Added bus_if and fsm to top level design) // Parallelport + parallelport parallelport1 ( + .inClk(clk), + .inTimerMeas(bus.TimerMeas), + .inEndOfConv(endOfConv), + .inData(bus.Data), + .outDataValid(bus.DataValid), + .outData(bus.Data) + ); // FRAM-Controller // Timer + timer timer1 ( + .inClk(clk), + .inTaste(bus.Taste), + .inEN(bus.TimerEN), + .outReadTemp(bus.ReadTemp), + .outTasteAktiv(bus.TasteAktiv) + ); // Ampelsteuerung + led_top ampelsteuerung ( + .clk12M(clk), + .rst(rst), + .data_input(bus.Data), + .data_valid(bus.DataValid), + .RED(LEDr), + .GRN(LEDg), + .alarm(bus.AlarmAmpel) + ); + + assign AlarmAmpel = bus.AlarmAmpel; endmodule \ No newline at end of file