From 026899b930835597e8ea85d65177e75bdc2b1a06 Mon Sep 17 00:00:00 2001 From: sessleral71711 Date: Tue, 14 Jun 2022 12:21:25 +0200 Subject: [PATCH] Added parallelport, timer and ampelsteuerung --- Source_Ampel/rgb_led_top.sv | 5 ++--- Top/Top.sv | 35 ++++++++++++++++++++++++++++++++++- 2 files changed, 36 insertions(+), 4 deletions(-) diff --git a/Source_Ampel/rgb_led_top.sv b/Source_Ampel/rgb_led_top.sv index e2bec6d..f2c9af9 100644 --- a/Source_Ampel/rgb_led_top.sv +++ b/Source_Ampel/rgb_led_top.sv @@ -3,8 +3,6 @@ input wire clk12M, input wire rst, input wire [7:0] data_input, input wire data_valid, -output reg REDn, -output reg GRNn, output reg RED, output reg GRN, output reg alarm @@ -12,7 +10,8 @@ output reg alarm wire red_pwm; wire grn_pwm; - +reg REDn; +reg GRNn; defparam U1.on_hi = 2'b10; defparam U1.on_lo = 2'b01; defparam U1.off = 2'b00; diff --git a/Top/Top.sv b/Top/Top.sv index 0e0361f..89eef3d 100644 --- a/Top/Top.sv +++ b/Top/Top.sv @@ -1,13 +1,20 @@ `include "../spi_interface.v" `include "../fsm/Fsm.sv" `include "../Bus_if/Bus_if.sv" +`include "../timer_port/timer_top.sv" module Top( - input wire clk + input wire clk, + input wire rst, + input wire endOfConv, + output wire LEDg, + output wire LEDr, + output wire AlarmAmpel ); // Bus (Interface) Bus_if bus(.clk(clk)); // SPI Interface + // FSM Fsm fsm( .clk(clk), @@ -19,8 +26,34 @@ module Top( .outTimerEN(bus.TimerEN) ); // Parallelport + parallelport parallelport1 ( + .inClk(clk), + .inTimerMeas(bus.TimerMeas), + .inEndOfConv(endOfConv), + .inData(bus.Data), + .outDataValid(bus.DataValid), + .outData(bus.Data) + ); // FRAM-Controller // Timer + timer timer1 ( + .inClk(clk), + .inTaste(bus.Taste), + .inEN(bus.TimerEN), + .outReadTemp(bus.ReadTemp), + .outTasteAktiv(bus.TasteAktiv) + ); // Ampelsteuerung + led_top ampelsteuerung ( + .clk12M(clk), + .rst(rst), + .data_input(bus.Data), + .data_valid(bus.DataValid), + .RED(LEDr), + .GRN(LEDg), + .alarm(bus.AlarmAmpel) + ); + + assign AlarmAmpel = bus.AlarmAmpel; endmodule \ No newline at end of file