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ESY1_Projekt_2022
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Added Clk_generator
top_level_design
sessleral71711
2 years ago
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dcb19f11aa
commit
48610eeb8c
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fsm/Clk_generator.sv
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fsm/Clk_generator.sv
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module Clk_generator #(CLK_PERIOD = 2) (output logic clk);
initial #0 clk <= 0;
always #(CLK_PERIOD/2) clk=~clk;
endmodule
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