From 53868c67fd2eb380599d9db4a8cde96f349c0377 Mon Sep 17 00:00:00 2001
From: sessleral71711 <sessleral71711@th-nuernberg.de>
Date: Tue, 14 Jun 2022 11:45:29 +0200
Subject: [PATCH] Added Bus_if and fsm to top level design

---
 Top/Top.sv | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/Top/Top.sv b/Top/Top.sv
index d8e489c..0e0361f 100644
--- a/Top/Top.sv
+++ b/Top/Top.sv
@@ -1,12 +1,23 @@
 `include "../spi_interface.v"
 `include "../fsm/Fsm.sv"
+`include "../Bus_if/Bus_if.sv"
 
 module Top(
     input wire clk
 );
     // Bus (Interface)
+    Bus_if bus(.clk(clk));
     // SPI Interface
     // FSM
+    Fsm fsm(
+        .clk(clk),
+        .inAlarmAmpel(bus.AlarmAmpel),
+        .inDataValid(bus.DataValid),
+        .inTasteAktiv(bus.TasteAktiv),
+        .outAlarm_R(bus.Alarm_R),
+        .outSendData(bus.SendData),
+        .outTimerEN(bus.TimerEN)
+    );
     // Parallelport
     // FRAM-Controller
     // Timer