From 6a72019f256254faaf709f6d0a6206f678d3f3d4 Mon Sep 17 00:00:00 2001
From: sessleral71711 <sessleral71711@th-nuernberg.de>
Date: Tue, 14 Jun 2022 10:35:05 +0200
Subject: [PATCH] Initalized top level design

---
 Top/Top.sv | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Top/Top.sv b/Top/Top.sv
index 0e0361f..cfdcbd1 100644
--- a/Top/Top.sv
+++ b/Top/Top.sv
@@ -1,11 +1,15 @@
 `include "../spi_interface.v"
 `include "../fsm/Fsm.sv"
+<<<<<<< HEAD
 `include "../Bus_if/Bus_if.sv"
+=======
+>>>>>>> b8d8341 (Initalized top level design)
 
 module Top(
     input wire clk
 );
     // Bus (Interface)
+<<<<<<< HEAD
     Bus_if bus(.clk(clk));
     // SPI Interface
     // FSM
@@ -18,6 +22,10 @@ module Top(
         .outSendData(bus.SendData),
         .outTimerEN(bus.TimerEN)
     );
+=======
+    // SPI Interface
+    // FSM
+>>>>>>> b8d8341 (Initalized top level design)
     // Parallelport
     // FRAM-Controller
     // Timer