From 71b0458554ac82e9d0b056ba42977217bf78a0e6 Mon Sep 17 00:00:00 2001
From: sessleral71711 <sessleral71711@th-nuernberg.de>
Date: Thu, 2 Jun 2022 09:26:16 +0200
Subject: [PATCH] FSM mit 2 States erstellt und getestet

---
 fsm/Fsm.sv    | 93 +++++++++++++++++++++++----------------------------
 fsm/tb_Fsm.sv | 55 ++++++++++++++++++------------
 2 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/fsm/Fsm.sv b/fsm/Fsm.sv
index f842d41..b4a07d8 100644
--- a/fsm/Fsm.sv
+++ b/fsm/Fsm.sv
@@ -1,63 +1,52 @@
 module Fsm
     (
         input wire clk,
-        input wire tim_ready,
-        input wire alarm,
-        output logic adc_en,
-        output logic tim_en,
-        output logic fram_c_en,
-        output logic led_c_en
+        input wire inAlarmAmpel,
+        input wire inDataValid,
+        input wire inTasteAktiv,
+        output logic outAlarm_R,
+        output logic outSendData,
+        output logic outTimerEN
     );
-    real S0 = 0;
-    real S1 = 1;
-    real S2 = 2;
-    real S3 = 3;
-    real S4 = 4;
-    real S5 = 5;
-    real S6 = 6;
-  
-    logic[2:0] state;
+    real IDLE = 0;
+    real ALARM = 1;
+
+    logic state;
     initial begin
-      #0 state <= 0;
-      #0 adc_en <= 0;
-      #0 tim_en <= 0;
-      #0 fram_c_en <= 0;
-      #0 led_c_en <= 0;
+      #0 state <= IDLE;
+      #0 outAlarm_R <= 0;
+      #0 outSendData <= 0;
+      #0 outTimerEN <= 0;
     end
-  
+
     always @(posedge clk) begin
       case(state)
-        S0: begin 
-                adc_en <= 1'b1;
-                tim_en <= 1'b1;
-                state <= S1;
-            end
-        S1: begin
-                adc_en <= 1'b0;
-                tim_en <= 1'b0;
-                if(tim_ready) begin
-                    fram_c_en <= 1'b1; 
-                    led_c_en  <= 1'b1; 
-                    state <= S2;
-                end
-                else begin
-                    // do nothing
-                end
-            end
-        S2: begin
-                fram_c_en <= 0'b0;
-                led_c_en  <= 0'b0;
-                if(alarm) begin
-                    // taster
-                end
-                else begin
-                    if(tim_ready) begin
-                    end
-                    state <= S0;
-                end
-            end
+        IDLE:  begin
+                   if(inDataValid) begin
+                       outSendData <= 1;
+                   end
+                   else begin
+                       outSendData <= 0;
+                   end
+                   if(inAlarmAmpel) begin
+                       outAlarm_R <= 1;
+                       state <= ALARM;
+                   end
+               end
+        ALARM: begin
+                   if(inDataValid) begin
+                       outSendData <= 1;
+                   end
+                   else begin
+                       outSendData <= 0;
+                   end
+                   if(inTasteAktiv) begin
+                       outAlarm_R <= 0;
+                       state <= IDLE;
+                   end
+               end
         default: ;
       endcase
     end
-        
-endmodule
\ No newline at end of file
+
+endmodule
diff --git a/fsm/tb_Fsm.sv b/fsm/tb_Fsm.sv
index 63407cd..c2dae8f 100644
--- a/fsm/tb_Fsm.sv
+++ b/fsm/tb_Fsm.sv
@@ -3,39 +3,50 @@
 
 module tb_Fsm;
     wire clk;
-    logic tim_ready;
-    logic alarm;
-    wire adc_en;
-    wire tim_en;
-    wire fram_c_en;
-    wire led_c_en;
+    logic inAlarmAmpel;
+    logic inDataValid;
+    logic inTasteAktiv;
+    wire outAlarm_R;
+    wire outSendData;
+    wire outTimerEN;
+
     Clk_generator clk_gen(.clk(clk));
-    
-  Fsm myfsm
+
+    Fsm myfsm
     (
       .clk(clk),
-      .tim_ready(tim_ready),
-      .alarm(alarm),
-      .adc_en(adc_en),
-      .tim_en(tim_en),
-      .fram_c_en(fram_c_en),
-      .led_c_en(led_c_en)
+      .inAlarmAmpel(inAlarmAmpel),
+      .inDataValid(inDataValid),
+      .inTasteAktiv(inTasteAktiv),
+      .outAlarm_R(outAlarm_R),
+      .outSendData(outSendData),
+      .outTimerEN(outTimerEN)
     );
 
-    always @(posedge clk) begin
-      #1 tim_ready <= ~tim_ready;
-    end
-  
 
     initial begin
         $dumpfile("tb_Fsm.vcd");
         $dumpvars(0, tb_Fsm);
         #50 $finish;
     end
-  
+
     initial begin
-        #0 tim_ready = 1'b0;
-        #0 alarm = 1'b0;
+        #0 inAlarmAmpel = 1'b0;
+        #0 inDataValid = 1'b0;
+        #0 inTasteAktiv = 1'b0;
+    end
+  
+   initial begin
+        #4 inAlarmAmpel = 1'b1;
+        #5 inAlarmAmpel = 1'b0;
+     
+        #8 inDataValid = 1'b1;
+        #9 inDataValid = 1'b0;
+     
+        #10 inTasteAktiv = 1'b1;
+        #11 inTasteAktiv = 1'b0;
     end
 
-endmodule
\ No newline at end of file
+
+endmodule
+