From b8d834144be80086a32a76f1769deccce6eaee15 Mon Sep 17 00:00:00 2001 From: sessleral71711 Date: Tue, 14 Jun 2022 10:35:05 +0200 Subject: [PATCH 1/6] Initalized top level design --- Top/Top.sv | 15 +++++++++++++++ Top/tb_Top.sv | 5 +++++ 2 files changed, 20 insertions(+) create mode 100644 Top/Top.sv create mode 100644 Top/tb_Top.sv diff --git a/Top/Top.sv b/Top/Top.sv new file mode 100644 index 0000000..d8e489c --- /dev/null +++ b/Top/Top.sv @@ -0,0 +1,15 @@ +`include "../spi_interface.v" +`include "../fsm/Fsm.sv" + +module Top( + input wire clk +); + // Bus (Interface) + // SPI Interface + // FSM + // Parallelport + // FRAM-Controller + // Timer + // Ampelsteuerung + +endmodule \ No newline at end of file diff --git a/Top/tb_Top.sv b/Top/tb_Top.sv new file mode 100644 index 0000000..cf1b286 --- /dev/null +++ b/Top/tb_Top.sv @@ -0,0 +1,5 @@ +`include "Top.sv" + +module tb_Top; + +endmodule \ No newline at end of file From 6b874ba5c7a49bcfb3680a1bf2d634f292152ba1 Mon Sep 17 00:00:00 2001 From: sessleral71711 Date: Tue, 14 Jun 2022 10:35:05 +0200 Subject: [PATCH 2/6] Initalized top level design --- Top/Top.sv | 15 +++++++++++++++ Top/tb_Top.sv | 5 +++++ 2 files changed, 20 insertions(+) create mode 100644 Top/Top.sv create mode 100644 Top/tb_Top.sv diff --git a/Top/Top.sv b/Top/Top.sv new file mode 100644 index 0000000..d8e489c --- /dev/null +++ b/Top/Top.sv @@ -0,0 +1,15 @@ +`include "../spi_interface.v" +`include "../fsm/Fsm.sv" + +module Top( + input wire clk +); + // Bus (Interface) + // SPI Interface + // FSM + // Parallelport + // FRAM-Controller + // Timer + // Ampelsteuerung + +endmodule \ No newline at end of file diff --git a/Top/tb_Top.sv b/Top/tb_Top.sv new file mode 100644 index 0000000..cf1b286 --- /dev/null +++ b/Top/tb_Top.sv @@ -0,0 +1,5 @@ +`include "Top.sv" + +module tb_Top; + +endmodule \ No newline at end of file From 20f8e707bd8136163675de49669b86f99a096ad6 Mon Sep 17 00:00:00 2001 From: sessleral71711 Date: Tue, 14 Jun 2022 11:45:29 +0200 Subject: [PATCH 3/6] Added Bus_if and fsm to top level design --- Top/Top.sv | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Top/Top.sv b/Top/Top.sv index d8e489c..0e0361f 100644 --- a/Top/Top.sv +++ b/Top/Top.sv @@ -1,12 +1,23 @@ `include "../spi_interface.v" `include "../fsm/Fsm.sv" +`include "../Bus_if/Bus_if.sv" module Top( input wire clk ); // Bus (Interface) + Bus_if bus(.clk(clk)); // SPI Interface // FSM + Fsm fsm( + .clk(clk), + .inAlarmAmpel(bus.AlarmAmpel), + .inDataValid(bus.DataValid), + .inTasteAktiv(bus.TasteAktiv), + .outAlarm_R(bus.Alarm_R), + .outSendData(bus.SendData), + .outTimerEN(bus.TimerEN) + ); // Parallelport // FRAM-Controller // Timer From 1be3ce1cea2505ca28c0da02b9402ac52774ec51 Mon Sep 17 00:00:00 2001 From: sessleral71711 Date: Tue, 14 Jun 2022 11:52:04 +0200 Subject: [PATCH 4/6] merge konflikt behoben --- Top/Top.sv | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/Top/Top.sv b/Top/Top.sv index c85f29f..daabb63 100644 --- a/Top/Top.sv +++ b/Top/Top.sv @@ -1,7 +1,6 @@ `include "../spi_interface.v" `include "../fsm/Fsm.sv" <<<<<<< HEAD -`include "../Bus_if/Bus_if.sv" ======= >>>>>>> b8d834144be80086a32a76f1769deccce6eaee15 @@ -10,18 +9,7 @@ module Top( ); // Bus (Interface) <<<<<<< HEAD - Bus_if bus(.clk(clk)); - // SPI Interface - // FSM - Fsm fsm( - .clk(clk), - .inAlarmAmpel(bus.AlarmAmpel), - .inDataValid(bus.DataValid), - .inTasteAktiv(bus.TasteAktiv), - .outAlarm_R(bus.Alarm_R), - .outSendData(bus.SendData), - .outTimerEN(bus.TimerEN) - ); + ======= // SPI Interface // FSM From c93bdaf629c36234379c5ee6bcd9ba666ef19c08 Mon Sep 17 00:00:00 2001 From: sessleral71711 Date: Tue, 14 Jun 2022 11:53:20 +0200 Subject: [PATCH 5/6] Added bus_if and fsm to top level design --- Top/Top.sv | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/Top/Top.sv b/Top/Top.sv index daabb63..0e0361f 100644 --- a/Top/Top.sv +++ b/Top/Top.sv @@ -1,19 +1,23 @@ `include "../spi_interface.v" `include "../fsm/Fsm.sv" -<<<<<<< HEAD -======= ->>>>>>> b8d834144be80086a32a76f1769deccce6eaee15 +`include "../Bus_if/Bus_if.sv" module Top( input wire clk ); // Bus (Interface) -<<<<<<< HEAD - -======= + Bus_if bus(.clk(clk)); // SPI Interface // FSM ->>>>>>> b8d834144be80086a32a76f1769deccce6eaee15 + Fsm fsm( + .clk(clk), + .inAlarmAmpel(bus.AlarmAmpel), + .inDataValid(bus.DataValid), + .inTasteAktiv(bus.TasteAktiv), + .outAlarm_R(bus.Alarm_R), + .outSendData(bus.SendData), + .outTimerEN(bus.TimerEN) + ); // Parallelport // FRAM-Controller // Timer From 026899b930835597e8ea85d65177e75bdc2b1a06 Mon Sep 17 00:00:00 2001 From: sessleral71711 Date: Tue, 14 Jun 2022 12:21:25 +0200 Subject: [PATCH 6/6] Added parallelport, timer and ampelsteuerung --- Source_Ampel/rgb_led_top.sv | 5 ++--- Top/Top.sv | 35 ++++++++++++++++++++++++++++++++++- 2 files changed, 36 insertions(+), 4 deletions(-) diff --git a/Source_Ampel/rgb_led_top.sv b/Source_Ampel/rgb_led_top.sv index e2bec6d..f2c9af9 100644 --- a/Source_Ampel/rgb_led_top.sv +++ b/Source_Ampel/rgb_led_top.sv @@ -3,8 +3,6 @@ input wire clk12M, input wire rst, input wire [7:0] data_input, input wire data_valid, -output reg REDn, -output reg GRNn, output reg RED, output reg GRN, output reg alarm @@ -12,7 +10,8 @@ output reg alarm wire red_pwm; wire grn_pwm; - +reg REDn; +reg GRNn; defparam U1.on_hi = 2'b10; defparam U1.on_lo = 2'b01; defparam U1.off = 2'b00; diff --git a/Top/Top.sv b/Top/Top.sv index 0e0361f..89eef3d 100644 --- a/Top/Top.sv +++ b/Top/Top.sv @@ -1,13 +1,20 @@ `include "../spi_interface.v" `include "../fsm/Fsm.sv" `include "../Bus_if/Bus_if.sv" +`include "../timer_port/timer_top.sv" module Top( - input wire clk + input wire clk, + input wire rst, + input wire endOfConv, + output wire LEDg, + output wire LEDr, + output wire AlarmAmpel ); // Bus (Interface) Bus_if bus(.clk(clk)); // SPI Interface + // FSM Fsm fsm( .clk(clk), @@ -19,8 +26,34 @@ module Top( .outTimerEN(bus.TimerEN) ); // Parallelport + parallelport parallelport1 ( + .inClk(clk), + .inTimerMeas(bus.TimerMeas), + .inEndOfConv(endOfConv), + .inData(bus.Data), + .outDataValid(bus.DataValid), + .outData(bus.Data) + ); // FRAM-Controller // Timer + timer timer1 ( + .inClk(clk), + .inTaste(bus.Taste), + .inEN(bus.TimerEN), + .outReadTemp(bus.ReadTemp), + .outTasteAktiv(bus.TasteAktiv) + ); // Ampelsteuerung + led_top ampelsteuerung ( + .clk12M(clk), + .rst(rst), + .data_input(bus.Data), + .data_valid(bus.DataValid), + .RED(LEDr), + .GRN(LEDg), + .alarm(bus.AlarmAmpel) + ); + + assign AlarmAmpel = bus.AlarmAmpel; endmodule \ No newline at end of file