diff --git a/Top/Top.sv b/Top/Top.sv
index 81790ae..4566c71 100644
--- a/Top/Top.sv
+++ b/Top/Top.sv
@@ -1,19 +1,33 @@
 `include "../spi_interface.v"
 `include "../fsm/Fsm.sv"
 <<<<<<< HEAD
+<<<<<<< HEAD
 =======
 >>>>>>> b8d8341 (Initalized top level design)
+=======
+`include "../Bus_if/Bus_if.sv"
+>>>>>>> c93bdaf (Added bus_if and fsm to top level design)
 
 module Top(
     input wire clk
 );
     // Bus (Interface)
-<<<<<<< HEAD
-
-=======
+    Bus_if bus(.clk(clk));
     // SPI Interface
     // FSM
+<<<<<<< HEAD
 >>>>>>> b8d8341 (Initalized top level design)
+=======
+    Fsm fsm(
+        .clk(clk),
+        .inAlarmAmpel(bus.AlarmAmpel),
+        .inDataValid(bus.DataValid),
+        .inTasteAktiv(bus.TasteAktiv),
+        .outAlarm_R(bus.Alarm_R),
+        .outSendData(bus.SendData),
+        .outTimerEN(bus.TimerEN)
+    );
+>>>>>>> c93bdaf (Added bus_if and fsm to top level design)
     // Parallelport
     // FRAM-Controller
     // Timer