From c93bdaf629c36234379c5ee6bcd9ba666ef19c08 Mon Sep 17 00:00:00 2001 From: sessleral71711 Date: Tue, 14 Jun 2022 11:53:20 +0200 Subject: [PATCH] Added bus_if and fsm to top level design --- Top/Top.sv | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/Top/Top.sv b/Top/Top.sv index daabb63..0e0361f 100644 --- a/Top/Top.sv +++ b/Top/Top.sv @@ -1,19 +1,23 @@ `include "../spi_interface.v" `include "../fsm/Fsm.sv" -<<<<<<< HEAD -======= ->>>>>>> b8d834144be80086a32a76f1769deccce6eaee15 +`include "../Bus_if/Bus_if.sv" module Top( input wire clk ); // Bus (Interface) -<<<<<<< HEAD - -======= + Bus_if bus(.clk(clk)); // SPI Interface // FSM ->>>>>>> b8d834144be80086a32a76f1769deccce6eaee15 + Fsm fsm( + .clk(clk), + .inAlarmAmpel(bus.AlarmAmpel), + .inDataValid(bus.DataValid), + .inTasteAktiv(bus.TasteAktiv), + .outAlarm_R(bus.Alarm_R), + .outSendData(bus.SendData), + .outTimerEN(bus.TimerEN) + ); // Parallelport // FRAM-Controller // Timer