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base: kuntzschcl:19177edb3f4d3d158ae5a74682c402cde758108e
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kuntzschcl:main
kuntzschcl:top_level_design
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compare: kuntzschcl:37989e5bc1e20f1205bb895a459cc3fe8e2bde96
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kuntzschcl:main
kuntzschcl:top_level_design

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87
timer_port/testbench.sv
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// Code your testbench here
// or browse Examples
`timescale 1ns/1ps;
module tb();
reg inClk, inEN, inTaste;
wire outReadTemp;
wire outTasteAktiv;
reg [7:0] inData;
reg inEndOfConv;
wire outDataValid;
wire [7:0] outData;
timer t1 (.inClk(inClk),
.inTaste(inTaste),
.inEN(inEN),
.outReadTemp(outReadTemp),
.outTasteAktiv(outTasteAktiv));
parallelport p1 (.inData(inData),
.inClk(inClk),
.inTimerMeas(outReadTemp),
.inEndOfConv(inEndOfConv),
.outDataValid(outDataValid),
.outData(outData));
always #83 inClk <= ~inClk;
always #1000000000 inEndOfConv <= ~inEndOfConv;
always #100000000 inData = inData +1;
initial begin
//$dumpfile("dump.vcd");
//$dumpvars;
inClk <= 0;
inEN <= 0;
inTaste <= 0;
inData <= 8'b0;
inEndOfConv <= 0;
#1000000000
inTaste = 1;
#1000000000
#1000000000
#1000000000
inTaste = 0;
#1000000000
inEN <= 1;
#1000000000
inEN <= 0;
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
#1000000000
$stop;
end
endmodule

62
timer_port/timer_top.sv
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//clock divider
module timer(input inClk, inTaste, inEN, output reg outReadTemp, outTasteAktiv);
int divide1 = 30000000;
int divide2 = 60000;
logic state = 0;
logic [31:0] count1 = 32'b0;
logic [31:0] count2 = 32'b0;
initial begin
outReadTemp = 0;
outTasteAktiv = 0;
end
always @(posedge inClk or posedge inEN) begin
if(inEN) begin
count1 <= 0;
count2 <= 0;
outReadTemp <= 0;
end
else begin
count1 <= count1 +1;
if(count1>=((2**32)-1))
count1 <= 32'b0;
if(count1 % divide1 == 0)
outReadTemp <= ~outReadTemp;
if(inTaste) begin
count2 <= count2 +1;
if(count2 >= 6000000)
outTasteAktiv = 1;
end
else begin
outTasteAktiv <= 0;
count2 <= 0;
end
end
end
endmodule // clk_divider
module parallelport(input inClk, inTimerMeas, inEndOfConv, [7:0] inData, output reg outDataValid, [7:0] outData);
logic [7:0] storage = 8'b0;
initial begin
outDataValid <= 0;
outData <= 8'b0;
end
always @(posedge inClk) begin
if(inEndOfConv)
storage <= inData;
if(inTimerMeas == 1 && outDataValid == 0) begin
outData = storage;
outDataValid <= 1;
end
else if(inTimerMeas == 0)
outDataValid <= 0;
end
endmodule