kuntzschcl/ESY1_Projekt_2022
kuntzschcl/ESY1_Projekt_2022
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base: kuntzschcl:e8af8d04c8c0dfcbd24d64c062b9a7d8677f4659
Branches Tags
kuntzschcl:main
kuntzschcl:top_level_design
..
compare: kuntzschcl:7b858e7068dbe578312fa0cc8885c9bd7c213683
Branches Tags
kuntzschcl:main
kuntzschcl:top_level_design

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3 changed files with 0 additions and 108 deletions
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4
fsm/Clk_generator.sv
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@ -1,4 +0,0 @@
module Clk_generator #(CLK_PERIOD = 2) (output logic clk);
initial #0 clk <= 0;
always #(CLK_PERIOD/2) clk=~clk;
endmodule

52
fsm/Fsm.sv
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@ -1,52 +0,0 @@
module Fsm
(
input wire clk,
input wire inAlarmAmpel,
input wire inDataValid,
input wire inTasteAktiv,
output logic outAlarm_R,
output logic outSendData,
output logic outTimerEN
);
real IDLE = 0;
real ALARM = 1;
logic state;
initial begin
#0 state <= IDLE;
#0 outAlarm_R <= 0;
#0 outSendData <= 0;
#0 outTimerEN <= 0;
end
always @(posedge clk) begin
case(state)
IDLE: begin
if(inDataValid) begin
outSendData <= 1;
end
else begin
outSendData <= 0;
end
if(inAlarmAmpel) begin
outAlarm_R <= 1;
state <= ALARM;
end
end
ALARM: begin
if(inDataValid) begin
outSendData <= 1;
end
else begin
outSendData <= 0;
end
if(inTasteAktiv) begin
outAlarm_R <= 0;
state <= IDLE;
end
end
default: ;
endcase
end
endmodule

52
fsm/tb_Fsm.sv
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@ -1,52 +0,0 @@
`include "Clk_generator.sv"
`include "Fsm.sv"
module tb_Fsm;
wire clk;
logic inAlarmAmpel;
logic inDataValid;
logic inTasteAktiv;
wire outAlarm_R;
wire outSendData;
wire outTimerEN;
Clk_generator clk_gen(.clk(clk));
Fsm myfsm
(
.clk(clk),
.inAlarmAmpel(inAlarmAmpel),
.inDataValid(inDataValid),
.inTasteAktiv(inTasteAktiv),
.outAlarm_R(outAlarm_R),
.outSendData(outSendData),
.outTimerEN(outTimerEN)
);
initial begin
$dumpfile("tb_Fsm.vcd");
$dumpvars(0, tb_Fsm);
#50 $finish;
end
initial begin
#0 inAlarmAmpel = 1'b0;
#0 inDataValid = 1'b0;
#0 inTasteAktiv = 1'b0;
end
initial begin
#4 inAlarmAmpel = 1'b1;
#5 inAlarmAmpel = 1'b0;
#8 inDataValid = 1'b1;
#9 inDataValid = 1'b0;
#10 inTasteAktiv = 1'b1;
#11 inTasteAktiv = 1'b0;
end
endmodule