`include "../spi_interface.v"
`include "../fsm/Fsm.sv"
<<<<<<< HEAD
`include "../Bus_if/Bus_if.sv"
=======
>>>>>>> b8d834144be80086a32a76f1769deccce6eaee15

module Top(
    input wire clk
);
    // Bus (Interface)
<<<<<<< HEAD
    Bus_if bus(.clk(clk));
    // SPI Interface
    // FSM
    Fsm fsm(
        .clk(clk),
        .inAlarmAmpel(bus.AlarmAmpel),
        .inDataValid(bus.DataValid),
        .inTasteAktiv(bus.TasteAktiv),
        .outAlarm_R(bus.Alarm_R),
        .outSendData(bus.SendData),
        .outTimerEN(bus.TimerEN)
    );
=======
    // SPI Interface
    // FSM
>>>>>>> b8d834144be80086a32a76f1769deccce6eaee15
    // Parallelport
    // FRAM-Controller
    // Timer
    // Ampelsteuerung
    
endmodule