ESY1_Projekt_2022/Top/Top.sv

`include "../spi_interface.v"
`include "../fsm/Fsm.sv"
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module Top(
    input wire clk
);
    // Bus (Interface)
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    // SPI Interface
    // FSM
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    // Parallelport
    // FRAM-Controller
    // Timer
    // Ampelsteuerung
    
endmodule