ESY1_Projekt_2022/Source_Ampel/testbench.sv

//   ==================================================================
//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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//   Copyright (c) 2017 by Lattice Semiconductor Corporation
//   ALL RIGHTS RESERVED  
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//   Permission:
//
//      Lattice SG Pte. Ltd. grants permission to use this code
//      pursuant to the terms of the Lattice Reference Design License Agreement. 
//
//
//   Disclaimer:
//
//      This VHDL or Verilog source code is intended as a design reference
//      which illustrates how these types of functions can be implemented.
//      It is the user's responsibility to verify their design for
//      consistency and functionality through the use of formal
//      verification methods.  Lattice provides no warranty
//      regarding the use or functionality of this code.
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// --------------------------------------------------------------------
//
//  Project:           iCE5UP 5K RGB LED Tutorial 
//  File:              testbench.v
//  Title:             LED PWM control
//  Description:       Creates RGB PWM per control inputs
//                 
//
// --------------------------------------------------------------------
//
//------------------------------------------------------------
// Notes:
//
//
//------------------------------------------------------------
// Development History:
//
//   __DATE__ _BY_ _REV_ _DESCRIPTION___________________________
//   04/05/17  RK  1.0    Initial tutorial design for Lattice Radiant
//
//------------------------------------------------------------
// Dependencies:
//
// 
//
//------------------------------------------------------------



//------------------------------------------------------------
// 
//
//                     Testbench
//
//------------------------------------------------------------
`timescale 1ns/1ps
module tb;
	
//GSR GSR_INST ( .GSR(1));
//PUR PUR_INST ( .PUR(1));



reg clk12M;
reg rst;
reg [9:0]data_input;
reg data_valid;
wire RED;
wire GRN;
wire alarm;

led_top dut(.clk12M(clk12M),
			.rst(rst),
			.data_input(data_input),
			.data_valid(data_valid),
			.RED(RED),
			.GRN(GRN),
			.alarm(alarm)
			);     

initial
begin
    clk12M=1'b0;
end

always 
  #41.666666 clk12M=~clk12M;                             //clock generation
  

 initial
 begin             
 rst=1'b1; 
 data_input=10'b0000000010; // data for green
 data_valid=1'b0; 
 #500000
 rst=1'b0;
 #500000
 data_valid = 1'b1;
 #500000
 data_valid = 1'b0;
 #500000
 rst=1'b1;
 #500000
 rst=1'b0;
 data_valid=1'b1;
 data_input=10'b1000000001; // data for yellow
 #500000
 data_valid=1'b0; 
 data_input = 10'b1100000001; //data for red
 #500000
data_valid = 1'b1;
 #500000
  data_input=10'b1000000001; // data for yellow
 #500000
rst=1'b1;
 #500000   
 $stop;
 end 
 
 initial
	 begin
		 $monitor("time=%t,rst=%d,",$time,rst);
	end

endmodule