Projektdaten für das ESY1B Praktikum im Sommersemester 2022
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Clk_generator.sv 131B

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  1. module Clk_generator #(CLK_PERIOD = 2) (output logic clk);
  2. initial #0 clk <= 0;
  3. always #(CLK_PERIOD/2) clk=~clk;
  4. endmodule