ESY1_Projekt_2022/fsm/Fsm.sv

module Fsm
    (
        input wire clk,
        input wire tim_ready,
        input wire alarm,
        output logic adc_en,
        output logic tim_en,
        output logic fram_c_en,
        output logic led_c_en
    );
    real S0 = 0;
    real S1 = 1;
    real S2 = 2;
    real S3 = 3;
    real S4 = 4;
    real S5 = 5;
    real S6 = 6;
  
    logic[2:0] state;
    initial begin
      #0 state <= 0;
      #0 adc_en <= 0;
      #0 tim_en <= 0;
      #0 fram_c_en <= 0;
      #0 led_c_en <= 0;
    end
  
    always @(posedge clk) begin
      case(state)
        S0: begin 
                adc_en <= 1'b1;
                tim_en <= 1'b1;
                state <= S1;
            end
        S1: begin
                adc_en <= 1'b0;
                tim_en <= 1'b0;
                if(tim_ready) begin
                    fram_c_en <= 1'b1; 
                    led_c_en  <= 1'b1; 
                    state <= S2;
                end
                else begin
                    // do nothing
                end
            end
        S2: begin
                fram_c_en <= 0'b0;
                led_c_en  <= 0'b0;
                if(alarm) begin
                    // taster
                end
                else begin
                    if(tim_ready) begin
                    end
                    state <= S0;
                end
            end
        default: ;
      endcase
    end
        
endmodule