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- interface Bus_if (input clk);
- logic sbclk;
- logic sbstb;
- logic sbrw;
- logic[7:0] sbadr;
- logic[7:0] sbdat_r;
- logic[7:0] sbdat_w;
- logic sback;
- logic[9:0] Data;
- logic SendData;
- logic TimerMeas;
- logic Clk;
- logic DataValid;
- logic AlarmAmpel;
- logic TasteAktiv;
- logic Alarm_R;
- logic TimerEN;
- logic Taste;
- logic ReadTemp;
- logic LEDg;
- logic LEDr;
-
- modport Fsm (
- input clk,
- input AlarmAmpel,
- input DataValid,
- input TasteAktiv,
- output Alarm_R,
- output SendData,
- output TimerEN
- );
- endinterface //Bus
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