ESY1_Projekt_2022/fsm/Fsm.sv

module Fsm
    (
        input wire clk,
        input wire inAlarmAmpel,
        input wire inDataValid,
        input wire inTasteAktiv,
        output logic outAlarm_R,
        output logic outSendData,
        output logic outTimerEN
    );
    real IDLE = 0;
    real ALARM = 1;

    logic state;
    initial begin
      #0 state <= IDLE;
      #0 outAlarm_R <= 0;
      #0 outSendData <= 0;
      #0 outTimerEN <= 0;
    end

    always @(posedge clk) begin
      case(state)
        IDLE:  begin
                   if(inDataValid) begin
                       outSendData <= 1;
                   end
                   else begin
                       outSendData <= 0;
                   end
                   if(inAlarmAmpel) begin
                       outAlarm_R <= 1;
                       state <= ALARM;
                   end
               end
        ALARM: begin
                   if(inDataValid) begin
                       outSendData <= 1;
                   end
                   else begin
                       outSendData <= 0;
                   end
                   if(inTasteAktiv) begin
                       outAlarm_R <= 0;
                       state <= IDLE;
                   end
               end
        default: ;
      endcase
    end

endmodule