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- `include "../spi_interface.v"
- `include "../fsm/Fsm.sv"
- <<<<<<< HEAD
- <<<<<<< HEAD
- <<<<<<< HEAD
- =======
- >>>>>>> b8d8341 (Initalized top level design)
- =======
- `include "../Bus_if/Bus_if.sv"
- <<<<<<< HEAD
- >>>>>>> c93bdaf (Added bus_if and fsm to top level design)
- =======
- `include "../timer_port/timer_top.sv"
- >>>>>>> 026899b (Added parallelport, timer and ampelsteuerung)
- =======
- `include "../Bus_if/Bus_if.sv"
- `include "../timer_port/timer_top.sv"
- >>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
-
- module Top(
- input wire clk,
- input wire rst,
- input wire endOfConv,
- output wire LEDg,
- output wire LEDr,
- output wire AlarmAmpel
- );
- // Bus (Interface)
- Bus_if bus(.clk(clk));
- // SPI Interface
-
- // FSM
- <<<<<<< HEAD
- <<<<<<< HEAD
- >>>>>>> b8d8341 (Initalized top level design)
- =======
- =======
- >>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
- Fsm fsm(
- .clk(clk),
- .inAlarmAmpel(bus.AlarmAmpel),
- .inDataValid(bus.DataValid),
- .inTasteAktiv(bus.TasteAktiv),
- .outAlarm_R(bus.Alarm_R),
- .outSendData(bus.SendData),
- .outTimerEN(bus.TimerEN)
- );
- <<<<<<< HEAD
- >>>>>>> c93bdaf (Added bus_if and fsm to top level design)
- =======
- >>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
- // Parallelport
- parallelport parallelport1 (
- .inClk(clk),
- .inTimerMeas(bus.TimerMeas),
- .inEndOfConv(endOfConv),
- .inData(bus.Data),
- .outDataValid(bus.DataValid),
- .outData(bus.Data)
- );
- // FRAM-Controller
- // Timer
- timer timer1 (
- .inClk(clk),
- .inTaste(bus.Taste),
- .inEN(bus.TimerEN),
- .outReadTemp(bus.ReadTemp),
- .outTasteAktiv(bus.TasteAktiv)
- );
- // Ampelsteuerung
- led_top ampelsteuerung (
- .clk12M(clk),
- .rst(rst),
- .data_input(bus.Data),
- .data_valid(bus.DataValid),
- .RED(LEDr),
- .GRN(LEDg),
- .alarm(bus.AlarmAmpel)
- );
-
- assign AlarmAmpel = bus.AlarmAmpel;
-
- endmodule
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