ESY1_Projekt_2022/timer_port/timer_top.sv

//clock divider
module timer(input inClk, inTaste, inEN, output reg outReadTemp, outTasteAktiv);
  int divide1 = 30000000;
  int divide2 = 60000;
  
  logic 			state = 0;
  logic [31:0] 		count1 = 32'b0;
  logic [31:0]		count2 = 32'b0;
  
  initial begin
    outReadTemp = 0;
	outTasteAktiv = 0;
  end

   always @(posedge inClk or posedge inEN) begin
	   if(inEN) begin
      count1 <= 0;
	  count2 <= 0;
	  outReadTemp <= 0;
	   end
	else begin
      count1 <= count1 +1;
     if(count1>=((2**32)-1))
		count1 <= 32'b0;
     if(count1 % divide1 == 0)
       outReadTemp <= ~outReadTemp;
		
	if(inTaste) begin
		count2 <= count2 +1;
		if(count2 >= 6000000) 
			outTasteAktiv = 1;
		end
		else begin
			outTasteAktiv <= 0;
			count2 <= 0;
	end	
	end
	end
endmodule // clk_divider

module parallelport(input inClk, inTimerMeas, inEndOfConv, [7:0] inData, output reg outDataValid, [7:0] outData);

	logic [7:0] 		storage = 8'b0;
	
	
	initial begin
		outDataValid <= 0;
		outData <= 8'b0;
		end
		
		always @(posedge inClk) begin
			if(inEndOfConv)
				storage <= inData;
			
			if(inTimerMeas == 1 && outDataValid == 0) begin
				outData = storage;
				outDataValid <= 1;
			end
			else if(inTimerMeas == 0)
				outDataValid <= 0;
		end	
endmodule