ESY1_Projekt_2022/Top/Top.sv

`include "../spi_interface.v"
`include "../fsm/Fsm.sv"
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>>>>>>> b8d8341 (Initalized top level design)
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`include "../Bus_if/Bus_if.sv"
>>>>>>> c93bdaf (Added bus_if and fsm to top level design)

module Top(
    input wire clk
);
    // Bus (Interface)
    Bus_if bus(.clk(clk));
    // SPI Interface
    // FSM
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    Fsm fsm(
        .clk(clk),
        .inAlarmAmpel(bus.AlarmAmpel),
        .inDataValid(bus.DataValid),
        .inTasteAktiv(bus.TasteAktiv),
        .outAlarm_R(bus.Alarm_R),
        .outSendData(bus.SendData),
        .outTimerEN(bus.TimerEN)
    );
>>>>>>> c93bdaf (Added bus_if and fsm to top level design)
    // Parallelport
    // FRAM-Controller
    // Timer
    // Ampelsteuerung
    
endmodule