Projektdaten für das ESY1B Praktikum im Sommersemester 2022
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spi_interface.v 41KB

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  1. /*******************************************************************************
  2. Verilog netlist generated by IPGEN Lattice Radiant Software (64-bit)
  3. 3.1.1.232.1
  4. Soft IP Version: 1.0.0
  5. 2022 05 31 12:27:15
  6. *******************************************************************************/
  7. /*******************************************************************************
  8. SPI Interface Ports
  9. trying to follow instructions from:
  10. https://www.chipverify.com/systemverilog/systemverilog-interface
  11. *******************************************************************************/
  12. interface spi_interface_ports (input clk);
  13. // Connection to BUS side (internal)
  14. // Inputs from BUS
  15. logic sb_clk_i; // Clock
  16. logic sb_stb_i; // Chip Select from FRAM-Controller who is SPI-Master
  17. logic sb_wr_i; // Write/Read from FRAM-Controller
  18. logic sb_adr_i[7:0]; // Adddress from FRAM-Controller
  19. logic sb_dat_i[7:0]; // Data in from FRAM-Controller
  20. // Outputs to BUS
  21. logic sb_dat_o[7:0]; // Data out to FRAM-Controller
  22. logic sb_ack_o; // ACK to FRAM-Controller
  23. // Connection to SPI side (external)
  24. logic spi1_mosi_io; // MasterOutSlaveIn --> Master to Slave
  25. logic spi1_miso_io; // MasterInSlaveOut --> Slave to Master
  26. logic spi1_mcs_n_o[3:0]; // MasterChipSelect --> Master selects Slave
  27. logic spi1_sck_io; // Clock for SPI-Slave
  28. // MODPORT form BUS perspective (internal)
  29. // modport output from BUS (internal)
  30. modport BUS (output sb_clk_i, sb_stb_i, sb_wr_i, sb_adr_i[7:0], sb_dat_i[7:0], spi1_miso_io);
  31. // modport input to BUS (internal)
  32. modport BUS (input sb_dat_o[7:0], sb_ack_o, spi1_mosi_io, spi1_mcs_n_o[3:0], spi_sck_io);
  33. // MODPORT from SPI perspective (external)
  34. // modport output from SPI (external)
  35. modport SPI (output spi1_miso_io);
  36. // modport input to SPI (external)
  37. modport SPI (input spi1_mosi_io, spi1_mcs_n_o[3:0], spi_sck_io);
  38. endinterface
  39. /*******************************************************************************
  40. Wrapper Module generated per user settings.
  41. *******************************************************************************/
  42. module spi_interface (spi1_miso_io,
  43. spi1_mosi_io,
  44. spi1_sck_io,
  45. spi1_scs_n_i,
  46. spi1_mcs_n_o,
  47. rst_i,
  48. ipload_i,
  49. ipdone_o,
  50. sb_clk_i,
  51. sb_wr_i,
  52. sb_stb_i,
  53. sb_adr_i,
  54. sb_dat_i,
  55. sb_dat_o,
  56. sb_ack_o,
  57. spi_pirq_o,
  58. spi_pwkup_o) ;
  59. inout spi1_miso_io ;
  60. inout spi1_mosi_io ;
  61. inout spi1_sck_io ;
  62. input spi1_scs_n_i ;
  63. output [3:0] spi1_mcs_n_o ;
  64. input rst_i ;
  65. input ipload_i ;
  66. output ipdone_o ;
  67. input sb_clk_i ;
  68. input sb_wr_i ;
  69. input sb_stb_i ;
  70. input [7:0] sb_adr_i ;
  71. input [7:0] sb_dat_i ;
  72. output [7:0] sb_dat_o ;
  73. output sb_ack_o ;
  74. output [1:0] spi_pirq_o ;
  75. output [1:0] spi_pwkup_o ;
  76. spi_interface_ipgen_lscc_spi_i2c #(.i2c_left_enable(0),
  77. .i2c_right_enable(0),
  78. .spi_left_enable(0),
  79. .spi_right_enable(1),
  80. .FREQUENCY_PIN_SBCLKI("12.0"),
  81. .I2C_LEFT_CLK_PRESCALE("29"),
  82. .I2C_LEFT_CLK_DIVIDER(120),
  83. .I2C_LEFT_SLAVE_INIT_ADDR("0b1111101"),
  84. .I2C_LEFT_SDA_INPUT_DELAYED("1"),
  85. .I2C_LEFT_SDA_OUTPUT_DELAYED("0"),
  86. .I2C_LEFT_INIT_VALUE_0(128),
  87. .I2C_LEFT_INIT_VALUE_1(31),
  88. .I2C_LEFT_INIT_VALUE_2(0),
  89. .I2C_RIGHT_CLK_PRESCALE("29"),
  90. .I2C_RIGHT_CLK_DIVIDER(120),
  91. .I2C_RIGHT_SLAVE_INIT_ADDR("0b1111110"),
  92. .I2C_RIGHT_SDA_INPUT_DELAYED("1"),
  93. .I2C_RIGHT_SDA_OUTPUT_DELAYED("0"),
  94. .I2C_RIGHT_INIT_VALUE_5(128),
  95. .I2C_RIGHT_INIT_VALUE_6(31),
  96. .I2C_RIGHT_INIT_VALUE_7(0),
  97. .SPI_LEFT_CLK_DIVIDER(1),
  98. .SPI_LEFT_CLK_PRESCALE("0"),
  99. .SPI_LEFT_MASTER_CHIP_SELECTS(1),
  100. .SPI_LEFT_WAKEUP_ENABLE(1),
  101. .SPI_LEFT_INIT_VALUE_10(8),
  102. .SPI_LEFT_INIT_VALUE_13(0),
  103. .SPI_RIGHT_CLK_DIVIDER(1),
  104. .SPI_RIGHT_CLK_PRESCALE("0"),
  105. .SPI_RIGHT_MASTER_CHIP_SELECTS(3),
  106. .SPI_RIGHT_WAKEUP_ENABLE(0),
  107. .SPI_RIGHT_INIT_VALUE_15(12),
  108. .SPI_RIGHT_INIT_VALUE_18(128)) lscc_spi_i2c_inst (.i2c2_scl_io(),
  109. .i2c2_sda_io(),
  110. .i2c1_scl_io(),
  111. .i2c1_sda_io(),
  112. .spi2_miso_io(),
  113. .spi2_mosi_io(),
  114. .spi2_sck_io(),
  115. .spi2_scs_n_i(1'b0),
  116. .spi2_mcs_n_o(),
  117. .spi1_miso_io(spi1_miso_io),
  118. .spi1_mosi_io(spi1_mosi_io),
  119. .spi1_sck_io(spi1_sck_io),
  120. .spi1_scs_n_i(spi1_scs_n_i),
  121. .spi1_mcs_n_o(spi1_mcs_n_o[3:0]),
  122. .rst_i(rst_i),
  123. .ipload_i(ipload_i),
  124. .ipdone_o(ipdone_o),
  125. .sb_clk_i(sb_clk_i),
  126. .sb_wr_i(sb_wr_i),
  127. .sb_stb_i(sb_stb_i),
  128. .sb_adr_i(sb_adr_i[7:0]),
  129. .sb_dat_i(sb_dat_i[7:0]),
  130. .sb_dat_o(sb_dat_o[7:0]),
  131. .sb_ack_o(sb_ack_o),
  132. .i2c_pirq_o(),
  133. .i2c_pwkup_o(),
  134. .spi_pirq_o(spi_pirq_o[1:0]),
  135. .spi_pwkup_o(spi_pwkup_o[1:0])) ;
  136. endmodule
  137. `timescale 1ns/1ns
  138. // =============================================================================
  139. // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
  140. // -----------------------------------------------------------------------------
  141. // Copyright (c) 2017 by Lattice Semiconductor Corporation
  142. // ALL RIGHTS RESERVED
  143. // -----------------------------------------------------------------------------
  144. //
  145. // Permission:
  146. //
  147. // Lattice SG Pte. Ltd. grants permission to use this code
  148. // pursuant to the terms of the Lattice Reference Design License Agreement.
  149. //
  150. //
  151. // Disclaimer:
  152. //
  153. // This VHDL or Verilog source code is intended as a design reference
  154. // which illustrates how these types of functions can be implemented.
  155. // It is the user's responsibility to verify their design for
  156. // consistency and functionality through the use of formal
  157. // verification methods. Lattice provides no warranty
  158. // regarding the use or functionality of this code.
  159. //
  160. // -----------------------------------------------------------------------------
  161. //
  162. // Lattice SG Pte. Ltd.
  163. // 101 Thomson Road, United Square #07-02
  164. // Singapore 307591
  165. //
  166. //
  167. // TEL: 1-800-Lattice (USA and Canada)
  168. // +65-6631-2000 (Singapore)
  169. // +1-503-268-8001 (other locations)
  170. //
  171. // web: http://www.latticesemi.com/
  172. // email: techsupport@latticesemi.com
  173. //
  174. // -----------------------------------------------------------------------------
  175. //
  176. // =============================================================================
  177. // FILE DETAILS
  178. // Project :
  179. // File : lscc_spi_i2c.v
  180. // Title :
  181. // Dependencies : I2C_B primitive
  182. // : SPI_B primitive
  183. // Description :
  184. // =============================================================================
  185. // REVISION HISTORY
  186. // Version : 1.0.0.
  187. // Author(s) :
  188. // Mod. Date :
  189. // Changes Made : Initial release.
  190. // =============================================================================
  191. module spi_interface_ipgen_lscc_spi_i2c #(parameter num_regs = 23,
  192. parameter i2c_left_enable = 0,
  193. parameter i2c_right_enable = 0,
  194. parameter spi_left_enable = 0,
  195. parameter spi_right_enable = 0,
  196. parameter FREQUENCY_PIN_SBCLKI = "NONE",
  197. parameter I2C_LEFT_CLK_DIVIDER = 8,
  198. parameter I2C_LEFT_CLK_PRESCALE = "1",
  199. parameter I2C_LEFT_INIT_VALUE_0 = 0,
  200. parameter I2C_LEFT_INIT_VALUE_1 = 0,
  201. parameter I2C_LEFT_INIT_VALUE_2 = 0,
  202. parameter I2C_LEFT_SLAVE_INIT_ADDR = "0b1111100001",
  203. parameter I2C_LEFT_SDA_INPUT_DELAYED = "1",
  204. parameter I2C_LEFT_SDA_OUTPUT_DELAYED = "0",
  205. parameter I2C_RIGHT_CLK_DIVIDER = 8,
  206. parameter I2C_RIGHT_CLK_PRESCALE = "1",
  207. parameter I2C_RIGHT_INIT_VALUE_5 = 0,
  208. parameter I2C_RIGHT_INIT_VALUE_6 = 0,
  209. parameter I2C_RIGHT_INIT_VALUE_7 = 0,
  210. parameter I2C_RIGHT_SLAVE_INIT_ADDR = "0b1111100010",
  211. parameter I2C_RIGHT_SDA_INPUT_DELAYED = "1",
  212. parameter I2C_RIGHT_SDA_OUTPUT_DELAYED = "0",
  213. parameter SPI_LEFT_INIT_VALUE_10 = 0,
  214. parameter SPI_LEFT_INIT_VALUE_13 = 0,
  215. parameter SPI_RIGHT_INIT_VALUE_15 = 0,
  216. parameter SPI_RIGHT_INIT_VALUE_18 = 0,
  217. parameter SPI_LEFT_WAKEUP_ENABLE = 1,
  218. parameter SPI_LEFT_CLK_DIVIDER = 2,
  219. parameter SPI_LEFT_CLK_PRESCALE = "1",
  220. parameter SPI_LEFT_MASTER_CHIP_SELECTS = 1,
  221. parameter SPI_RIGHT_WAKEUP_ENABLE = 1,
  222. parameter SPI_RIGHT_CLK_DIVIDER = 2,
  223. parameter SPI_RIGHT_CLK_PRESCALE = "1",
  224. parameter SPI_RIGHT_MASTER_CHIP_SELECTS = 1) (
  225. // -----------------------------------------------------------------------------
  226. // Module Parameters
  227. // -----------------------------------------------------------------------------
  228. // (I2C_LEFT_CLK_PRESCALE+1) * 4
  229. // (1 - 1023)
  230. // (I2C_RIGHT_CLK_PRESCALE+1) * 4
  231. // (1 - 1023)
  232. // SPI_LEFT_CLK_PRESCALE + 1
  233. // (1 - 63)
  234. // SPI_RIGHT_CLK_PRESCALE + 1
  235. // (1 - 63)
  236. // -----------------------------------------------------------------------------
  237. // Input/Output Ports
  238. // -----------------------------------------------------------------------------
  239. // I2C Left
  240. inout wire i2c2_scl_io,
  241. inout wire i2c2_sda_io,
  242. // I2c Right
  243. inout wire i2c1_scl_io,
  244. inout wire i2c1_sda_io,
  245. // SPI Left
  246. inout wire spi2_miso_io,
  247. inout wire spi2_mosi_io,
  248. inout wire spi2_sck_io,
  249. input wire spi2_scs_n_i,
  250. output wire [3:0] spi2_mcs_n_o,
  251. // SPI Right
  252. inout wire spi1_miso_io,
  253. inout wire spi1_mosi_io,
  254. inout wire spi1_sck_io,
  255. input wire spi1_scs_n_i,
  256. output wire [3:0] spi1_mcs_n_o,
  257. // Fabric Interface
  258. input wire rst_i,
  259. input wire ipload_i,
  260. output wire ipdone_o,
  261. input wire sb_clk_i,
  262. input wire sb_wr_i,
  263. input wire sb_stb_i,
  264. input wire [7:0] sb_adr_i,
  265. input wire [7:0] sb_dat_i,
  266. output wire [7:0] sb_dat_o,
  267. output wire sb_ack_o,
  268. output wire [1:0] i2c_pirq_o,
  269. output wire [1:0] i2c_pwkup_o,
  270. output wire [1:0] spi_pirq_o,
  271. output wire [1:0] spi_pwkup_o) ;
  272. // -----------------------------------------------------------------------------
  273. // Local Parameters
  274. // -----------------------------------------------------------------------------
  275. localparam RSVD = 8'hFF ;
  276. // I2C Base Address
  277. localparam I2CBADDRL = 4'b0001 ; // I2C LEFT
  278. localparam I2CBADDRR = 4'b0011 ; // I2C RIGHT
  279. // I2C Register Address
  280. localparam I2CCR1 = 4'b1000 ; // I2C Control Register 1
  281. localparam I2CCMDR = 4'b1001 ; // I2C Command Register
  282. localparam I2CBRLSB = 4'b1010 ; // I2C Clock Presale register, LSB
  283. localparam I2CBRMSB = 4'b1011 ; // I2C Clock Presale register, MSB
  284. localparam I2CSR = 4'b1100 ; // I2C Status Register
  285. localparam I2CTXDR = 4'b1101 ; // I2C Transmitting Data Register
  286. localparam I2CRXDR = 4'b1110 ; // I2C Receiving Data Register
  287. localparam I2CGCDR = 4'b1111 ; // I2C General Call Information Register
  288. localparam I2CINTCR = 4'b0111 ; // I2C Interrupt Control Register
  289. localparam I2CINTSR = 4'b0110 ; // I2C Interrupt Status Register
  290. localparam I2CSADDR = 4'b0011 ; // I2C Slave address MSB
  291. // SPI Base Address
  292. localparam SPIBADDRL = 4'b0000 ; // SPI LEFT
  293. localparam SPIBADDRR = 4'b0010 ; // SPI RIGHT
  294. // SPI Register Address
  295. localparam SPICR0 = 4'b1000 ; // SPI Control Register0
  296. localparam SPICR1 = 4'b1001 ; // SPI Control Register1
  297. localparam SPICR2 = 4'b1010 ; // SPI Control Register2
  298. localparam SPIBR = 4'b1011 ; // SPI Baud Rate Register
  299. localparam SPISR = 4'b1100 ; // SPI Status Register
  300. localparam SPITXDR = 4'b1101 ; // SPI Transmitting Data Register
  301. localparam SPIRXDR = 4'b1110 ; // SPI Receiving Data Register
  302. localparam SPICSR = 4'b1111 ; // SPI Chip Select Mask for Master Mode
  303. localparam SPIINTCR = 4'b0111 ; // SPI Interrupt Control Register
  304. localparam SPIINTSR = 4'b0110 ; // SPI Interrupt Status Register
  305. // -----------------------------------------------------------------------------
  306. // Combinatorial/Sequential Registers
  307. // -----------------------------------------------------------------------------
  308. reg [7:0] SBDATo_i ;
  309. reg load_d1 ;
  310. reg load_d2 ;
  311. reg start ;
  312. reg pup ;
  313. reg run ;
  314. reg [5:0] trans_count ;
  315. reg IPDONE_i ;
  316. reg sb_idle ;
  317. reg strobe ;
  318. reg wb_we_ix ;
  319. reg wb_stb_ix ;
  320. reg [7:0] wb_adr_ix ;
  321. reg [7:0] wb_dat_ix ;
  322. reg [5:0] start_count ;
  323. reg [5:0] next_count ;
  324. // -----------------------------------------------------------------------------
  325. // Wire Declarations
  326. // -----------------------------------------------------------------------------
  327. wire hard_SBWRi ;
  328. wire hard_SBSTBi ;
  329. wire [7:0] hard_SBADRi ;
  330. wire [7:0] hard_SBDATi ;
  331. wire hard00_SBACKO ;
  332. wire hard01_SBACKO ;
  333. wire hard10_SBACKO ;
  334. wire hard11_SBACKO ;
  335. wire [3:0] hard_ACKs ;
  336. wire SBACKo_i ;
  337. wire [7:0] hard00_SBDATo ;
  338. wire [7:0] hard01_SBDATo ;
  339. wire [7:0] hard10_SBDATo ;
  340. wire [7:0] hard11_SBDATo ;
  341. wire ssm_SBWRi ;
  342. wire ssm_SBSTBi ;
  343. wire [7:0] ssm_SBADRi ;
  344. wire [7:0] ssm_SBDATi ;
  345. wire I2C2_SCLo ;
  346. wire I2C2_SCLoe ;
  347. wire I2C2_SCLi ;
  348. wire I2C2_SDAo ;
  349. wire I2C2_SDAoe ;
  350. wire I2C2_SDAi ;
  351. wire I2C1_SCLo ;
  352. wire I2C1_SCLoe ;
  353. wire I2C1_SCLi ;
  354. wire I2C1_SDAo ;
  355. wire I2C1_SDAoe ;
  356. wire I2C1_SDAi ;
  357. wire SPI2_SO ;
  358. wire SPI2_SOoe ;
  359. wire SPI2_MI ;
  360. wire SPI2_MO ;
  361. wire SPI2_MOoe ;
  362. wire SPI2_SI ;
  363. wire SPI2_SCKo ;
  364. wire SPI2_SCKoe ;
  365. wire SPI2_SCKi ;
  366. wire SPI2_SCSNi ;
  367. wire [3:0] SPI2_MCSNo ;
  368. wire [3:0] SPI2_MCSNoe ;
  369. wire SPI1_SO ;
  370. wire SPI1_SOoe ;
  371. wire SPI1_MI ;
  372. wire SPI1_MO ;
  373. wire SPI1_MOoe ;
  374. wire SPI1_SI ;
  375. wire SPI1_SCKo ;
  376. wire SPI1_SCKoe ;
  377. wire SPI1_SCKi ;
  378. wire SPI1_SCSNi ;
  379. wire [3:0] SPI1_MCSNo ;
  380. wire [3:0] SPI1_MCSNoe ;
  381. wire [7:0] init_value [0:(num_regs - 1)] ;
  382. wire [7:0] init_addr [0:(num_regs - 1)] ;
  383. wire [11:0] i2c_left_prescale ;
  384. wire [11:0] i2c_right_prescale ;
  385. // -----------------------------------------------------------------------------
  386. // Assign Statements
  387. // -----------------------------------------------------------------------------
  388. assign i2c_left_prescale = ((I2C_LEFT_CLK_DIVIDER > 4) ? (I2C_LEFT_CLK_DIVIDER - 4) : 0) ;
  389. assign i2c_right_prescale = ((I2C_RIGHT_CLK_DIVIDER > 4) ? (I2C_RIGHT_CLK_DIVIDER - 4) : 0) ;
  390. assign init_value[0] = I2C_LEFT_INIT_VALUE_0 ;
  391. assign init_value[1] = I2C_LEFT_INIT_VALUE_1 ;
  392. assign init_value[2] = I2C_LEFT_INIT_VALUE_2 ;
  393. assign init_value[3] = i2c_left_prescale[9:2] ;
  394. assign init_value[4] = {6'd0,
  395. i2c_left_prescale[11:10]} ;
  396. assign init_value[5] = I2C_RIGHT_INIT_VALUE_5 ;
  397. assign init_value[6] = I2C_RIGHT_INIT_VALUE_6 ;
  398. assign init_value[7] = I2C_RIGHT_INIT_VALUE_7 ;
  399. assign init_value[8] = i2c_right_prescale[9:2] ;
  400. assign init_value[9] = {6'd0,
  401. i2c_right_prescale[11:10]} ;
  402. assign init_value[10] = {3'd0,
  403. SPI_LEFT_INIT_VALUE_10[3:0],
  404. 1'b0} ;
  405. assign init_value[11] = {4'd0,
  406. SPI_LEFT_MASTER_CHIP_SELECTS[3:0]} ;
  407. assign init_value[12] = {1'b1,
  408. SPI_LEFT_WAKEUP_ENABLE[0],
  409. 6'd0} ;
  410. assign init_value[13] = (SPI_LEFT_INIT_VALUE_13 & 8'hA7) ; // 8'hA7 - masks reserved bits
  411. assign init_value[14] = (SPI_LEFT_CLK_DIVIDER - 1) ;
  412. assign init_value[15] = {3'd0,
  413. SPI_RIGHT_INIT_VALUE_15[3:0],
  414. 1'b0} ;
  415. assign init_value[16] = {4'd0,
  416. SPI_RIGHT_MASTER_CHIP_SELECTS[3:0]} ;
  417. assign init_value[17] = {1'b1,
  418. SPI_RIGHT_WAKEUP_ENABLE[0],
  419. 6'd0} ;
  420. assign init_value[18] = (SPI_RIGHT_INIT_VALUE_18 & 8'hA7) ; // 8'hA7 - masks reserved bits
  421. assign init_value[19] = (SPI_RIGHT_CLK_DIVIDER - 1) ;
  422. assign init_value[20] = RSVD ;
  423. assign init_value[21] = RSVD ;
  424. assign init_value[22] = RSVD ;
  425. assign init_addr[20] = RSVD ;
  426. assign init_addr[21] = RSVD ;
  427. assign init_addr[22] = RSVD ;
  428. // SYSTEM BUS multiplexing
  429. assign hard_SBWRi = (IPDONE_i ? sb_wr_i : ssm_SBWRi) ;
  430. assign hard_SBSTBi = (IPDONE_i ? sb_stb_i : ssm_SBSTBi) ;
  431. assign hard_SBADRi = (IPDONE_i ? sb_adr_i : ssm_SBADRi) ;
  432. assign hard_SBDATi = (IPDONE_i ? sb_dat_i : ssm_SBDATi) ;
  433. // {i2c_right, spi_righ, i2c_left, spi_left}
  434. assign hard_ACKs = {hard11_SBACKO,
  435. hard10_SBACKO,
  436. hard01_SBACKO,
  437. hard00_SBACKO} ;
  438. assign SBACKo_i = (|hard_ACKs) ;
  439. // Initialization SSM outputs
  440. assign ssm_SBWRi = 1 ; // All transaction are WRITE
  441. assign ssm_SBSTBi = strobe ;
  442. assign ssm_SBADRi = init_addr[trans_count] ;
  443. assign ssm_SBDATi = init_value[trans_count] ;
  444. assign sb_dat_o = SBDATo_i ;
  445. assign sb_ack_o = (SBACKo_i && IPDONE_i) ;
  446. assign ipdone_o = IPDONE_i ;
  447. // -----------------------------------------------------------------------------
  448. // Generate Assign Statements
  449. // -----------------------------------------------------------------------------
  450. generate
  451. if ((i2c_left_enable == 1))
  452. begin : genblk1
  453. assign init_addr[0] = {I2CBADDRL,
  454. I2CCR1} ;
  455. assign init_addr[1] = {I2CBADDRL,
  456. I2CSADDR} ;
  457. assign init_addr[2] = {I2CBADDRL,
  458. I2CINTCR} ;
  459. assign init_addr[3] = {I2CBADDRL,
  460. I2CBRLSB} ;
  461. assign init_addr[4] = {I2CBADDRL,
  462. I2CBRMSB} ;
  463. end
  464. else
  465. begin : genblk1
  466. assign init_addr[0] = RSVD ;
  467. assign init_addr[1] = RSVD ;
  468. assign init_addr[2] = RSVD ;
  469. assign init_addr[3] = RSVD ;
  470. assign init_addr[4] = RSVD ;
  471. end
  472. if ((i2c_right_enable == 1))
  473. begin : genblk2
  474. assign init_addr[5] = {I2CBADDRR,
  475. I2CCR1} ;
  476. assign init_addr[6] = {I2CBADDRR,
  477. I2CSADDR} ;
  478. assign init_addr[7] = {I2CBADDRR,
  479. I2CINTCR} ;
  480. assign init_addr[8] = {I2CBADDRR,
  481. I2CBRLSB} ;
  482. assign init_addr[9] = {I2CBADDRR,
  483. I2CBRMSB} ;
  484. end
  485. else
  486. begin : genblk2
  487. assign init_addr[5] = RSVD ;
  488. assign init_addr[6] = RSVD ;
  489. assign init_addr[7] = RSVD ;
  490. assign init_addr[8] = RSVD ;
  491. assign init_addr[9] = RSVD ;
  492. end
  493. if ((spi_left_enable == 1))
  494. begin : genblk3
  495. assign init_addr[10] = {SPIBADDRL,
  496. SPIINTCR} ;
  497. assign init_addr[11] = {SPIBADDRL,
  498. SPICSR} ;
  499. assign init_addr[12] = {SPIBADDRL,
  500. SPICR1} ;
  501. assign init_addr[13] = {SPIBADDRL,
  502. SPICR2} ;
  503. assign init_addr[14] = {SPIBADDRL,
  504. SPIBR} ;
  505. end
  506. else
  507. begin : genblk3
  508. assign init_addr[10] = RSVD ;
  509. assign init_addr[11] = RSVD ;
  510. assign init_addr[12] = RSVD ;
  511. assign init_addr[13] = RSVD ;
  512. assign init_addr[14] = RSVD ;
  513. end
  514. if ((spi_right_enable == 1))
  515. begin : genblk4
  516. assign init_addr[15] = {SPIBADDRR,
  517. SPIINTCR} ;
  518. assign init_addr[16] = {SPIBADDRR,
  519. SPICSR} ;
  520. assign init_addr[17] = {SPIBADDRR,
  521. SPICR1} ;
  522. assign init_addr[18] = {SPIBADDRR,
  523. SPICR2} ;
  524. assign init_addr[19] = {SPIBADDRR,
  525. SPIBR} ;
  526. end
  527. else
  528. begin : genblk4
  529. assign init_addr[15] = RSVD ;
  530. assign init_addr[16] = RSVD ;
  531. assign init_addr[17] = RSVD ;
  532. assign init_addr[18] = RSVD ;
  533. assign init_addr[19] = RSVD ;
  534. end
  535. endgenerate
  536. generate
  537. if ((i2c_left_enable == 1))
  538. begin : genblk5
  539. assign i2c2_scl_io = (I2C2_SCLoe ? I2C2_SCLo : 1'bZ) ;
  540. assign i2c2_sda_io = (I2C2_SDAoe ? I2C2_SDAo : 1'bZ) ;
  541. assign I2C2_SCLi = i2c2_scl_io ;
  542. assign I2C2_SDAi = i2c2_sda_io ;
  543. end
  544. if ((i2c_right_enable == 1))
  545. begin : genblk6
  546. assign i2c1_scl_io = (I2C1_SCLoe ? I2C1_SCLo : 1'bZ) ;
  547. assign i2c1_sda_io = (I2C1_SDAoe ? I2C1_SDAo : 1'bZ) ;
  548. assign I2C1_SCLi = i2c1_scl_io ;
  549. assign I2C1_SDAi = i2c1_sda_io ;
  550. end
  551. if ((spi_left_enable == 1))
  552. begin : genblk7
  553. assign spi2_miso_io = (SPI2_SOoe ? SPI2_SO : 1'bZ) ;
  554. assign SPI2_MI = spi2_miso_io ;
  555. assign spi2_mosi_io = (SPI2_MOoe ? SPI2_MO : 1'bZ) ;
  556. assign SPI2_SI = spi2_mosi_io ;
  557. assign spi2_sck_io = (SPI2_SCKoe ? SPI2_SCKo : 1'bZ) ;
  558. assign SPI2_SCKi = spi2_sck_io ;
  559. assign SPI2_SCSNi = spi2_scs_n_i ;
  560. assign spi2_mcs_n_o[3] = (SPI2_MCSNoe[3] ? SPI2_MCSNo[3] : 1'bZ) ;
  561. assign spi2_mcs_n_o[2] = (SPI2_MCSNoe[2] ? SPI2_MCSNo[2] : 1'bZ) ;
  562. assign spi2_mcs_n_o[1] = (SPI2_MCSNoe[1] ? SPI2_MCSNo[1] : 1'bZ) ;
  563. assign spi2_mcs_n_o[0] = (SPI2_MCSNoe[0] ? SPI2_MCSNo[0] : 1'bZ) ;
  564. end
  565. if ((spi_right_enable == 1))
  566. begin : genblk8
  567. assign spi1_miso_io = (SPI1_SOoe ? SPI1_SO : 1'bZ) ;
  568. assign SPI1_MI = spi1_miso_io ;
  569. assign spi1_mosi_io = (SPI1_MOoe ? SPI1_MO : 1'bZ) ;
  570. assign SPI1_SI = spi1_mosi_io ;
  571. assign spi1_sck_io = (SPI1_SCKoe ? SPI1_SCKo : 1'bZ) ;
  572. assign SPI1_SCKi = spi1_sck_io ;
  573. assign SPI1_SCSNi = spi1_scs_n_i ;
  574. assign spi1_mcs_n_o[3] = (SPI1_MCSNoe[3] ? SPI1_MCSNo[3] : 1'bZ) ;
  575. assign spi1_mcs_n_o[2] = (SPI1_MCSNoe[2] ? SPI1_MCSNo[2] : 1'bZ) ;
  576. assign spi1_mcs_n_o[1] = (SPI1_MCSNoe[1] ? SPI1_MCSNo[1] : 1'bZ) ;
  577. assign spi1_mcs_n_o[0] = (SPI1_MCSNoe[0] ? SPI1_MCSNo[0] : 1'bZ) ;
  578. end
  579. endgenerate
  580. // -----------------------------------------------------------------------------
  581. // Combinatorial Blocks
  582. // -----------------------------------------------------------------------------
  583. always
  584. @(*)
  585. begin
  586. wb_we_ix = hard_SBWRi ;
  587. end
  588. always
  589. @(*)
  590. begin
  591. wb_stb_ix = hard_SBSTBi ;
  592. end
  593. always
  594. @(*)
  595. begin
  596. wb_adr_ix = hard_SBADRi ;
  597. end
  598. always
  599. @(*)
  600. begin
  601. wb_dat_ix = hard_SBDATi ;
  602. end
  603. //-----------------------------------------------------------------------------
  604. // DATo mux
  605. //-----------------------------------------------------------------------------
  606. always
  607. @(*)
  608. begin
  609. case (hard_ACKs)
  610. 4'b1000 :
  611. SBDATo_i = hard11_SBDATo ;
  612. 4'b0100 :
  613. SBDATo_i = hard10_SBDATo ;
  614. 4'b0010 :
  615. SBDATo_i = hard01_SBDATo ;
  616. 4'b0001 :
  617. SBDATo_i = hard00_SBDATo ;
  618. default :
  619. SBDATo_i = 8'b0 ;
  620. endcase
  621. end
  622. //-----------------------------------------------------------------------------
  623. // Initialization SSM control: Start, Run, Done
  624. //-----------------------------------------------------------------------------
  625. always
  626. @(posedge sb_clk_i or
  627. posedge rst_i)
  628. begin
  629. if (rst_i)
  630. begin
  631. load_d1 <= 0 ;
  632. load_d2 <= 0 ;
  633. start <= 0 ;
  634. pup <= 1 ;
  635. run <= 0 ;
  636. trans_count <= 0 ;
  637. IPDONE_i <= 0 ;
  638. end
  639. else
  640. begin
  641. load_d1 <= (ipload_i || pup) ;
  642. load_d2 <= load_d1 ;
  643. start <= (load_d1 && (!load_d2)) ;// rising-edge detection
  644. if (start) // clear power-up launch flag
  645. pup <= 0 ;
  646. if (start)
  647. run <= 1 ;
  648. else
  649. // start init sequence
  650. if (IPDONE_i) // clear when init complete
  651. run <= 0 ;
  652. // reset control upon Start
  653. if (start)
  654. begin
  655. trans_count <= start_count ;
  656. IPDONE_i <= 0 ;
  657. end
  658. else
  659. // DONE
  660. if ((init_addr[trans_count] == 8'hFF))
  661. begin
  662. IPDONE_i <= 1 ;
  663. end
  664. else
  665. // increment if not DONE
  666. if (SBACKo_i)
  667. begin
  668. trans_count <= next_count ;
  669. end
  670. end
  671. end
  672. always
  673. @(*)
  674. begin
  675. start_count = (i2c_left_enable ? 6'd0 : (i2c_right_enable ? 6'd5 : (spi_left_enable ? 6'd10 : (spi_right_enable ? 6'd15 : 6'd20)))) ;
  676. next_count = ((((trans_count + 1) < 6'd20) && (init_addr[(trans_count + 1)] != 8'hFF)) ? (trans_count + 1) : ((((trans_count + 6) < 6'd20) && (init_addr[(trans_count + 6)] != 8'hFF)) ? (trans_count + 6) : ((((trans_count + 11) < 6'd20) && (init_addr[(trans_count + 11)] != 8'hFF)) ? (trans_count + 11) : 6'd20))) ;
  677. end//--always @*--
  678. //-----------------------------------------------------------------------------
  679. // System Bus transaction control
  680. // Assert stb until EFB acknowledges with sb_ack_o
  681. //-----------------------------------------------------------------------------
  682. always
  683. @(posedge sb_clk_i or
  684. posedge rst_i)
  685. begin
  686. if (rst_i)
  687. begin
  688. sb_idle <= 1 ;
  689. strobe <= 0 ;
  690. end
  691. else
  692. begin
  693. // Assert stb signals to start SB transaction
  694. if (sb_idle)
  695. begin
  696. if (run)
  697. begin
  698. // delay 1 ns to avoid simulation/hardware mismatch
  699. strobe <= #(1) 1 ;
  700. sb_idle <= 0 ;
  701. end
  702. end
  703. else
  704. // Monitor sb_ack_o for end of transaction
  705. begin
  706. if ((SBACKo_i | (!run)))
  707. begin
  708. strobe <= 0 ;
  709. sb_idle <= 1 ;
  710. end
  711. end
  712. end
  713. end
  714. // -----------------------------------------------------------------------------
  715. // Submodule Instantiations
  716. // -----------------------------------------------------------------------------
  717. generate
  718. if ((i2c_left_enable == 1))
  719. begin : genblk9
  720. I2C_B #(.I2C_SLAVE_INIT_ADDR(I2C_LEFT_SLAVE_INIT_ADDR),
  721. .BUS_ADDR74("0b0001"),
  722. .I2C_CLK_DIVIDER(I2C_LEFT_CLK_PRESCALE),
  723. .FREQUENCY_PIN_SBCLKI(FREQUENCY_PIN_SBCLKI),
  724. .SDA_INPUT_DELAYED(I2C_LEFT_SDA_INPUT_DELAYED),
  725. .SDA_OUTPUT_DELAYED(I2C_LEFT_SDA_OUTPUT_DELAYED)) u_I2C_B_INST_LT (.SBCLKI(sb_clk_i),
  726. .SBRWI(wb_we_ix),
  727. .SBSTBI(wb_stb_ix),
  728. .SBADRI7(wb_adr_ix[7]),
  729. .SBADRI6(wb_adr_ix[6]),
  730. .SBADRI5(wb_adr_ix[5]),
  731. .SBADRI4(wb_adr_ix[4]),
  732. .SBADRI3(wb_adr_ix[3]),
  733. .SBADRI2(wb_adr_ix[2]),
  734. .SBADRI1(wb_adr_ix[1]),
  735. .SBADRI0(wb_adr_ix[0]),
  736. .SBDATI7(wb_dat_ix[7]),
  737. .SBDATI6(wb_dat_ix[6]),
  738. .SBDATI5(wb_dat_ix[5]),
  739. .SBDATI4(wb_dat_ix[4]),
  740. .SBDATI3(wb_dat_ix[3]),
  741. .SBDATI2(wb_dat_ix[2]),
  742. .SBDATI1(wb_dat_ix[1]),
  743. .SBDATI0(wb_dat_ix[0]),
  744. .SCLI(I2C2_SCLi),
  745. .SDAI(I2C2_SDAi),
  746. .SBDATO7(hard01_SBDATo[7]),
  747. .SBDATO6(hard01_SBDATo[6]),
  748. .SBDATO5(hard01_SBDATo[5]),
  749. .SBDATO4(hard01_SBDATo[4]),
  750. .SBDATO3(hard01_SBDATo[3]),
  751. .SBDATO2(hard01_SBDATo[2]),
  752. .SBDATO1(hard01_SBDATo[1]),
  753. .SBDATO0(hard01_SBDATo[0]),
  754. .SBACKO(hard01_SBACKO),
  755. .I2CIRQ(i2c_pirq_o[0]),
  756. .I2CWKUP(i2c_pwkup_o[0]),
  757. .SCLO(I2C2_SCLo),
  758. .SCLOE(I2C2_SCLoe),
  759. .SDAO(I2C2_SDAo),
  760. .SDAOE(I2C2_SDAoe)) ;
  761. end
  762. else
  763. begin : genblk9
  764. assign hard01_SBDATo[7] = 1'b0 ;
  765. assign hard01_SBDATo[6] = 1'b0 ;
  766. assign hard01_SBDATo[5] = 1'b0 ;
  767. assign hard01_SBDATo[4] = 1'b0 ;
  768. assign hard01_SBDATo[3] = 1'b0 ;
  769. assign hard01_SBDATo[2] = 1'b0 ;
  770. assign hard01_SBDATo[1] = 1'b0 ;
  771. assign hard01_SBDATo[0] = 1'b0 ;
  772. assign hard01_SBACKO = 1'b0 ;
  773. assign i2c_pirq_o[0] = 1'b0 ;
  774. assign i2c_pwkup_o[0] = 1'b0 ;
  775. end
  776. if ((i2c_right_enable == 1))
  777. begin : genblk10
  778. I2C_B #(.I2C_SLAVE_INIT_ADDR(I2C_RIGHT_SLAVE_INIT_ADDR),
  779. .BUS_ADDR74("0b0011"),
  780. .I2C_CLK_DIVIDER(I2C_RIGHT_CLK_PRESCALE),
  781. .FREQUENCY_PIN_SBCLKI(FREQUENCY_PIN_SBCLKI),
  782. .SDA_INPUT_DELAYED(I2C_RIGHT_SDA_INPUT_DELAYED),
  783. .SDA_OUTPUT_DELAYED(I2C_RIGHT_SDA_OUTPUT_DELAYED)) u_I2C_B_INST_RT (.SBCLKI(sb_clk_i),
  784. .SBRWI(wb_we_ix),
  785. .SBSTBI(wb_stb_ix),
  786. .SBADRI7(wb_adr_ix[7]),
  787. .SBADRI6(wb_adr_ix[6]),
  788. .SBADRI5(wb_adr_ix[5]),
  789. .SBADRI4(wb_adr_ix[4]),
  790. .SBADRI3(wb_adr_ix[3]),
  791. .SBADRI2(wb_adr_ix[2]),
  792. .SBADRI1(wb_adr_ix[1]),
  793. .SBADRI0(wb_adr_ix[0]),
  794. .SBDATI7(wb_dat_ix[7]),
  795. .SBDATI6(wb_dat_ix[6]),
  796. .SBDATI5(wb_dat_ix[5]),
  797. .SBDATI4(wb_dat_ix[4]),
  798. .SBDATI3(wb_dat_ix[3]),
  799. .SBDATI2(wb_dat_ix[2]),
  800. .SBDATI1(wb_dat_ix[1]),
  801. .SBDATI0(wb_dat_ix[0]),
  802. .SCLI(I2C1_SCLi),
  803. .SDAI(I2C1_SDAi),
  804. .SBDATO7(hard11_SBDATo[7]),
  805. .SBDATO6(hard11_SBDATo[6]),
  806. .SBDATO5(hard11_SBDATo[5]),
  807. .SBDATO4(hard11_SBDATo[4]),
  808. .SBDATO3(hard11_SBDATo[3]),
  809. .SBDATO2(hard11_SBDATo[2]),
  810. .SBDATO1(hard11_SBDATo[1]),
  811. .SBDATO0(hard11_SBDATo[0]),
  812. .SBACKO(hard11_SBACKO),
  813. .I2CIRQ(i2c_pirq_o[1]),
  814. .I2CWKUP(i2c_pwkup_o[1]),
  815. .SCLO(I2C1_SCLo),
  816. .SCLOE(I2C1_SCLoe),
  817. .SDAO(I2C1_SDAo),
  818. .SDAOE(I2C1_SDAoe)) ;
  819. end
  820. else
  821. begin : genblk10
  822. assign hard11_SBDATo[7] = 1'b0 ;
  823. assign hard11_SBDATo[6] = 1'b0 ;
  824. assign hard11_SBDATo[5] = 1'b0 ;
  825. assign hard11_SBDATo[4] = 1'b0 ;
  826. assign hard11_SBDATo[3] = 1'b0 ;
  827. assign hard11_SBDATo[2] = 1'b0 ;
  828. assign hard11_SBDATo[1] = 1'b0 ;
  829. assign hard11_SBDATo[0] = 1'b0 ;
  830. assign hard11_SBACKO = 1'b0 ;
  831. assign i2c_pirq_o[1] = 1'b0 ;
  832. assign i2c_pwkup_o[1] = 1'b0 ;
  833. end
  834. if ((spi_left_enable == 1))
  835. begin : genblk11
  836. SPI_B #(.FREQUENCY_PIN_SBCLKI(FREQUENCY_PIN_SBCLKI),
  837. .SPI_CLK_DIVIDER(SPI_LEFT_CLK_PRESCALE),
  838. .BUS_ADDR74("0b0000")) u_SPI_B_INST_LT (.SBCLKI(sb_clk_i),
  839. .SBRWI(wb_we_ix),
  840. .SBSTBI(wb_stb_ix),
  841. .SBADRI7(wb_adr_ix[7]),
  842. .SBADRI6(wb_adr_ix[6]),
  843. .SBADRI5(wb_adr_ix[5]),
  844. .SBADRI4(wb_adr_ix[4]),
  845. .SBADRI3(wb_adr_ix[3]),
  846. .SBADRI2(wb_adr_ix[2]),
  847. .SBADRI1(wb_adr_ix[1]),
  848. .SBADRI0(wb_adr_ix[0]),
  849. .SBDATI7(wb_dat_ix[7]),
  850. .SBDATI6(wb_dat_ix[6]),
  851. .SBDATI5(wb_dat_ix[5]),
  852. .SBDATI4(wb_dat_ix[4]),
  853. .SBDATI3(wb_dat_ix[3]),
  854. .SBDATI2(wb_dat_ix[2]),
  855. .SBDATI1(wb_dat_ix[1]),
  856. .SBDATI0(wb_dat_ix[0]),
  857. .MI(SPI2_MI),
  858. .SI(SPI2_SI),
  859. .SCKI(SPI2_SCKi),
  860. .SCSNI(SPI2_SCSNi),
  861. .SBDATO7(hard00_SBDATo[7]),
  862. .SBDATO6(hard00_SBDATo[6]),
  863. .SBDATO5(hard00_SBDATo[5]),
  864. .SBDATO4(hard00_SBDATo[4]),
  865. .SBDATO3(hard00_SBDATo[3]),
  866. .SBDATO2(hard00_SBDATo[2]),
  867. .SBDATO1(hard00_SBDATo[1]),
  868. .SBDATO0(hard00_SBDATo[0]),
  869. .SBACKO(hard00_SBACKO),
  870. .SPIIRQ(spi_pirq_o[0]),
  871. .SPIWKUP(spi_pwkup_o[0]),
  872. .SO(SPI2_SO),
  873. .SOE(SPI2_SOoe),
  874. .MO(SPI2_MO),
  875. .MOE(SPI2_MOoe),
  876. .SCKO(SPI2_SCKo),
  877. .SCKOE(SPI2_SCKoe),
  878. .MCSNO3(SPI2_MCSNo[3]),
  879. .MCSNO2(SPI2_MCSNo[2]),
  880. .MCSNO1(SPI2_MCSNo[1]),
  881. .MCSNO0(SPI2_MCSNo[0]),
  882. .MCSNOE3(SPI2_MCSNoe[3]),
  883. .MCSNOE2(SPI2_MCSNoe[2]),
  884. .MCSNOE1(SPI2_MCSNoe[1]),
  885. .MCSNOE0(SPI2_MCSNoe[0])) ;
  886. end
  887. else
  888. begin : genblk11
  889. assign hard00_SBDATo[7] = 1'b0 ;
  890. assign hard00_SBDATo[6] = 1'b0 ;
  891. assign hard00_SBDATo[5] = 1'b0 ;
  892. assign hard00_SBDATo[4] = 1'b0 ;
  893. assign hard00_SBDATo[3] = 1'b0 ;
  894. assign hard00_SBDATo[2] = 1'b0 ;
  895. assign hard00_SBDATo[1] = 1'b0 ;
  896. assign hard00_SBDATo[0] = 1'b0 ;
  897. assign hard00_SBACKO = 1'b0 ;
  898. assign spi_pirq_o[0] = 1'b0 ;
  899. assign spi_pwkup_o[0] = 1'b0 ;
  900. end
  901. if ((spi_right_enable == 1))
  902. begin : genblk12
  903. SPI_B #(.FREQUENCY_PIN_SBCLKI(FREQUENCY_PIN_SBCLKI),
  904. .SPI_CLK_DIVIDER(SPI_RIGHT_CLK_PRESCALE),
  905. .BUS_ADDR74("0b0010")) u_SPI_B_INST_RT (.SBCLKI(sb_clk_i),
  906. .SBRWI(wb_we_ix),
  907. .SBSTBI(wb_stb_ix),
  908. .SBADRI7(wb_adr_ix[7]),
  909. .SBADRI6(wb_adr_ix[6]),
  910. .SBADRI5(wb_adr_ix[5]),
  911. .SBADRI4(wb_adr_ix[4]),
  912. .SBADRI3(wb_adr_ix[3]),
  913. .SBADRI2(wb_adr_ix[2]),
  914. .SBADRI1(wb_adr_ix[1]),
  915. .SBADRI0(wb_adr_ix[0]),
  916. .SBDATI7(wb_dat_ix[7]),
  917. .SBDATI6(wb_dat_ix[6]),
  918. .SBDATI5(wb_dat_ix[5]),
  919. .SBDATI4(wb_dat_ix[4]),
  920. .SBDATI3(wb_dat_ix[3]),
  921. .SBDATI2(wb_dat_ix[2]),
  922. .SBDATI1(wb_dat_ix[1]),
  923. .SBDATI0(wb_dat_ix[0]),
  924. .MI(SPI1_MI),
  925. .SI(SPI1_SI),
  926. .SCKI(SPI1_SCKi),
  927. .SCSNI(SPI1_SCSNi),
  928. .SBDATO7(hard10_SBDATo[7]),
  929. .SBDATO6(hard10_SBDATo[6]),
  930. .SBDATO5(hard10_SBDATo[5]),
  931. .SBDATO4(hard10_SBDATo[4]),
  932. .SBDATO3(hard10_SBDATo[3]),
  933. .SBDATO2(hard10_SBDATo[2]),
  934. .SBDATO1(hard10_SBDATo[1]),
  935. .SBDATO0(hard10_SBDATo[0]),
  936. .SBACKO(hard10_SBACKO),
  937. .SPIIRQ(spi_pirq_o[1]),
  938. .SPIWKUP(spi_pwkup_o[1]),
  939. .SO(SPI1_SO),
  940. .SOE(SPI1_SOoe),
  941. .MO(SPI1_MO),
  942. .MOE(SPI1_MOoe),
  943. .SCKO(SPI1_SCKo),
  944. .SCKOE(SPI1_SCKoe),
  945. .MCSNO3(SPI1_MCSNo[3]),
  946. .MCSNO2(SPI1_MCSNo[2]),
  947. .MCSNO1(SPI1_MCSNo[1]),
  948. .MCSNO0(SPI1_MCSNo[0]),
  949. .MCSNOE3(SPI1_MCSNoe[3]),
  950. .MCSNOE2(SPI1_MCSNoe[2]),
  951. .MCSNOE1(SPI1_MCSNoe[1]),
  952. .MCSNOE0(SPI1_MCSNoe[0])) ;
  953. end
  954. else
  955. begin : genblk12
  956. assign hard10_SBDATo[7] = 1'b0 ;
  957. assign hard10_SBDATo[6] = 1'b0 ;
  958. assign hard10_SBDATo[5] = 1'b0 ;
  959. assign hard10_SBDATo[4] = 1'b0 ;
  960. assign hard10_SBDATo[3] = 1'b0 ;
  961. assign hard10_SBDATo[2] = 1'b0 ;
  962. assign hard10_SBDATo[1] = 1'b0 ;
  963. assign hard10_SBDATo[0] = 1'b0 ;
  964. assign hard10_SBACKO = 1'b0 ;
  965. assign spi_pirq_o[1] = 1'b0 ;
  966. assign spi_pwkup_o[1] = 1'b0 ;
  967. end
  968. endgenerate
  969. endmodule