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fram_interface.sv 1.8KB

1 year ago
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  1. `include "FRAM_Controller.sv"
  2. module spi(bus.spi_port b, fram_if.fram_port_top i);
  3. parameter ringbuffer_size = 256;
  4. logic [19:0] FRAM_Adr;
  5. logic [7:0] FRAM_DATA_OUT;
  6. logic [7:0] FRAM_DATA_IN;
  7. logic FRAM_RW;
  8. logic FRAM_RSTATUS;
  9. logic FRAM_hbn;
  10. logic FRAM_go;
  11. logic FRAM_busy;
  12. logic [7:0] clk_cntr;
  13. initial begin
  14. FRAM_Adr <= 20'h0;
  15. FRAM_DATA_IN <= 8'h0;
  16. FRAM_RW = 0;
  17. FRAM_RSTATUS = 0;
  18. FRAM_hbn = 0;
  19. FRAM_go = 0;
  20. clk_cntr = 0;
  21. end
  22. always @ (posedge b.timer) begin
  23. if(b.dip[0] == 0) begin //Reset
  24. FRAM_Adr <= 20'h0;
  25. FRAM_DATA_IN <= 8'h0;
  26. FRAM_RW = 0;
  27. FRAM_RSTATUS = 0;
  28. FRAM_hbn = 0;
  29. FRAM_go = 0;
  30. clk_cntr = 0;
  31. end
  32. else if(b.dip[1] == 1) begin //Read
  33. FRAM_Adr <= (FRAM_Adr - 1) % (ringbuffer_size - 1);
  34. FRAM_RW <= 1'h1; //Read
  35. FRAM_go <= 1'h1; //Go
  36. end
  37. else if(b.dip[1] == 0) begin //Write
  38. FRAM_Adr <= (FRAM_Adr + 1) % (ringbuffer_size - 1);
  39. FRAM_DATA_IN <= {6'h0, b.dip[4:3]};
  40. FRAM_RW <= 1'h0; //Write Operation
  41. FRAM_go <= 1'h1; //Go
  42. end
  43. end
  44. always @ (posedge b.oszi_clk) begin
  45. if(FRAM_go == 1)
  46. clk_cntr <= clk_cntr + 1;
  47. if(clk_cntr > 50 && FRAM_RW == 1'h1) begin
  48. b.spi_read <= FRAM_DATA_OUT[1:0];
  49. FRAM_go <= 1'h0;
  50. FRAM_RW <= 1'h0;
  51. clk_cntr <= 0;
  52. end
  53. else if(clk_cntr > 50 && FRAM_RW == 1'h0) begin
  54. FRAM_go <= 1'h0;
  55. clk_cntr <= 0;
  56. end
  57. end
  58. FRAM FRAM_ut(
  59. .i_clk(b.oszi_clk),
  60. .i_nreset(b.dip[0]),
  61. .i_adr(FRAM_Adr),
  62. .i_data(FRAM_DATA_IN),
  63. .o_data(FRAM_DATA_OUT),
  64. .i_rw(FRAM_RW),
  65. .i_status(FRAM_RSTATUS),
  66. .i_hbn(FRAM_hbn),
  67. .i_cready(FRAM_go),
  68. .o_busy(FRAM_busy),
  69. .o_SPI_Clk(i.sclk),
  70. .i_SPI_MISO(i.mosi),
  71. .o_SPI_MOSI(i.mosi),
  72. .o_SPI_CS_n(i.ss)
  73. );
  74. endmodule