ESY1_Projekt_2023/uebung_projekt/hdl_src/sv/timer.sv

//------------------------------------------------------
//                                                        
//  File          :  Timer.sv
//  Related Files :                                                     
//  Author(s)     :                                
//  Email         :      
//  Organization  :  Georg-Simon-Ohm-Hochschule Nuernberg 
//  Notes         :   
//
//------------------------------------------------------
//                   History    
//------------------------------------------------------
//    Version| Author   | Mod. Date  | Changes Made:
//    v1.00  |  		| 11.05.2023 | 
//------------------------------------------------------
//eoh


module timer(bus.timer_port fpga_bus, clock_if.clock_port_top c); // (bus.timer b, clock_if.clock_port_top i)

  integer counter = 0;	// internal count reg
  integer reload_val;

     
  always @ (posedge c.clk or fpga_bus.dip[0]) begin	
    if (!fpga_bus.dip[0]) begin
      counter <= 0;
	  fpga_bus.timer <= 0; 
    end else begin
  	  if(counter <= 800) begin  // zu testzwecken kürzer 1000000
		counter++;
		fpga_bus.timer <= 0;
	  end else begin
		counter <= 0;
		fpga_bus.timer <= 1;
      end
	end

  end

  //give the input clock on the bus
  always@(posedge c.clk or negedge c.clk)
  	fpga_bus.clk = c.clk;

endmodule : timer