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// ==================================================================
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// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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// ------------------------------------------------------------------
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// Copyright (c) 2017 by Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// ------------------------------------------------------------------
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//
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// Permission:
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//
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// Lattice SG Pte. Ltd. grants permission to use this code
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// pursuant to the terms of the Lattice Reference Design License Agreement.
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//
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//
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// Disclaimer:
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//
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// This VHDL or Verilog source code is intended as a design reference
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// which illustrates how these types of functions can be implemented.
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// It is the user's responsibility to verify their design for
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// consistency and functionality through the use of formal
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// verification methods. Lattice provides no warranty
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// regarding the use or functionality of this code.
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//
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// --------------------------------------------------------------------
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//
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// Lattice SG Pte. Lt++++++++++++++++d.
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// 101 Thomson Road, United Square #07-02
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// Singapore 307591
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//
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//
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// TEL: 1-800-Lattice (USA and Canada)
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// +65-6631-2000 (Singapore)
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// +1-503-268-8001 (other locations)
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//
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// web: http://www.latticesemi.com/
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// email: techsupport@latticesemi.com
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//
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// --------------------------------------------------------------------
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//
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// Project: iCE5UP 5K RGB LED Tutorial
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// File: testbench.v
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// Title: LED PWM control
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// Description: Creates RGB PWM per control inputs
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//
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//
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// --------------------------------------------------------------------
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//
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//------------------------------------------------------------
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// Notes:
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//
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//
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//------------------------------------------------------------
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// Development History:
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//
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// __DATE__ _BY_ _REV_ _DESCRIPTION___________________________
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// 04/05/17 RK 1.0 Initial tutorial design for Lattice Radiant
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//
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//------------------------------------------------------------
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// Dependencies:
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//
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//
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//
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//------------------------------------------------------------
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//------------------------------------------------------------
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//
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//
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// Testbench
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//
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//------------------------------------------------------------
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`timescale 1ns/1ps
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module tb;
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//GSR GSR_INST ( .GSR(1));
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//PUR PUR_INST ( .PUR(1));
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reg clk12M;
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reg rst;
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reg [1:0]color_sel;
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reg RGB_Blink_En;
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wire REDn;
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wire BLUn;
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wire GRNn;
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wire RED;
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wire BLU;
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wire GRN;
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led_top dut(.clk12M(clk12M),
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.rst(rst),
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.color_sel(color_sel),
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.RGB_Blink_En(RGB_Blink_En),
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.REDn(REDn),
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.BLUn(BLUn),
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.GRNn(GRNn),
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.RED(RED),
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.BLU(BLU),
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.GRN(GRN)
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);
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initial
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begin
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clk12M=1'b0;
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end
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always
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#41.666666 clk12M=~clk12M; //clock generation
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initial
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begin
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rst=1'b1;
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color_sel=2'b01;
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RGB_Blink_En=1'b0;
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#1000
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rst=1'b0;
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#3000000
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color_sel=2'b11;
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#3000000
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$stop;
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end
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initial
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begin
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$monitor("time=%t,RGB_Blink_En=%d,rst=%d,color_sel=%2d, REDn=%d, BLUn=%d, GRNn=%d",$time,RGB_Blink_En,rst,color_sel,REDn,BLUn,GRNn);
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end
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endmodule |