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Niklas Boese 2023-06-15 12:36:24 +00:00
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commit 17e6108c43
1 changed files with 70 additions and 69 deletions
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interface.sv
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//------------------------------------------------------ //------------------------------------------------------
// //
// File : interface.sv // File : interface.sv
// Related Files : // Related Files :
// Author(s) : Mueller // Author(s) : Mueller
// Email : muelleral82290@th-nuernberg.de // Email : muelleral82290@th-nuernberg.de
// Organization : Georg-Simon-Ohm-Hochschule Nuernberg // Organization : Georg-Simon-Ohm-Hochschule Nuernberg
// Notes : Stimuli Modul // Notes : Stimuli Modul
// //
//------------------------------------------------------ //------------------------------------------------------
// History // History
//------------------------------------------------------ //------------------------------------------------------
// Version| Author | Mod. Date | Changes Made: // Version| Author | Mod. Date | Changes Made:
// v1.00 | Mueller | 11/05/2023 | first code // v1.00 | Mueller | 11/05/2023 | first code
//------------------------------------------------------ //------------------------------------------------------
//eoh //eoh
//interface for LED //interface for LED
//reg [2:0]rbg stores rgb values that depend on dip[3:2] //reg [2:0]rbg stores rgb values that depend on dip[3:2]
interface led_if(); interface led_if();
logic [2:0]rgb; logic [2:0]rgb;
logic [2:0]rgbn;
modport led_port_stim(input rgb);
modport led_port_top(output rgb); modport led_port_stim(input rgb, rgbn);
modport led_port_top(output rgb, rgbn);
endinterface : led_if
endinterface : led_if
//interface for DIPSCHALER
// dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0 //interface for DIPSCHALER
interface dip_if(); // dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
interface dip_if();
logic [3:0]dip;
logic [3:0]dip;
modport dip_port_stim(output dip);
modport dip_port_top(input dip); modport dip_port_stim(output dip);
modport dip_port_top(input dip);
endinterface : dip_if
endinterface : dip_if
//interface for FRAM
// sck -> 0 ~ cummonication enabled, 1 ~ communication disabled //interface for FRAM
// clk -> system clock / timer // sck -> 0 ~ cummonication enabled, 1 ~ communication disabled
// miso -> testbench output // clk -> system clock / timer
// mosi -> testbench input // miso -> testbench output
interface fram_if(); // mosi -> testbench input
interface fram_if();
logic ss;
logic mosi; logic ss;
logic miso; logic mosi;
logic sclk; logic miso;
logic sclk;
modport fram_port_stim(input mosi, sclk, ss, output miso);
modport fram_port_top(output mosi, sclk, ss, input miso); modport fram_port_stim(input mosi, sclk, ss, output miso);
modport fram_port_top(output mosi, sclk, ss, input miso);
endinterface : fram_if
endinterface : fram_if
//testbenchclock replaces the oscillator on the board
interface clock_if(); //testbenchclock replaces the oscillator on the board
interface clock_if();
logic clk;
logic clk;
modport clock_port_stim(output clk);
modport clock_port_top(input clk); modport clock_port_stim(output clk);
modport clock_port_top(input clk);
endinterface : clock_if
endinterface : clock_if